drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8
   9 #include "mlx5_prm.h"
  10 #include "mlx5_devx_cmds.h"
  11 #include "mlx5_common_utils.h"
  12 #include "mlx5_malloc.h"
  13
  14
  15 /**
  16  * Perform read access to the registers. Reads data from register
  17  * and writes ones to the specified buffer.
  18  *
  19  * @param[in] ctx
  20  *   Context returned from mlx5 open_device() glue function.
  21  * @param[in] reg_id
  22  *   Register identifier according to the PRM.
  23  * @param[in] arg
  24  *   Register access auxiliary parameter according to the PRM.
  25  * @param[out] data
  26  *   Pointer to the buffer to store read data.
  27  * @param[in] dw_cnt
  28  *   Buffer size in double words.
  29  *
  30  * @return
  31  *   0 on success, a negative value otherwise.
  32  */
  33 int
  34 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  35                             uint32_t *data, uint32_t dw_cnt)
  36 {
  37         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  38         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  39                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  40         int status, rc;
  41
  42         MLX5_ASSERT(data && dw_cnt);
  43         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  44         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  45                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  46                 return -1;
  47         }
  48         MLX5_SET(access_register_in, in, opcode,
  49                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  50         MLX5_SET(access_register_in, in, op_mod,
  51                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  52         MLX5_SET(access_register_in, in, register_id, reg_id);
  53         MLX5_SET(access_register_in, in, argument, arg);
  54         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  55                                          MLX5_ST_SZ_DW(access_register_out) *
  56                                          sizeof(uint32_t) + dw_cnt);
  57         if (rc)
  58                 goto error;
  59         status = MLX5_GET(access_register_out, out, status);
  60         if (status) {
  61                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  62
  63                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  64                                "status %x, syndrome = %x",
  65                                reg_id, status, syndrome);
  66                 return -1;
  67         }
  68         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  69                dw_cnt * sizeof(uint32_t));
  70         return 0;
  71 error:
  72         rc = (rc > 0) ? -rc : rc;
  73         return rc;
  74 }
  75
  76 /**
  77  * Allocate flow counters via devx interface.
  78  *
  79  * @param[in] ctx
  80  *   Context returned from mlx5 open_device() glue function.
  81  * @param dcs
  82  *   Pointer to counters properties structure to be filled by the routine.
  83  * @param bulk_n_128
  84  *   Bulk counter numbers in 128 counters units.
  85  *
  86  * @return
  87  *   Pointer to counter object on success, a negative value otherwise and
  88  *   rte_errno is set.
  89  */
  90 struct mlx5_devx_obj *
  91 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  92 {
  93         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  94                                                 0, SOCKET_ID_ANY);
  95         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  96         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  97
  98         if (!dcs) {
  99                 rte_errno = ENOMEM;
 100                 return NULL;
 101         }
 102         MLX5_SET(alloc_flow_counter_in, in, opcode,
 103                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 104         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 105         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 106                                               sizeof(in), out, sizeof(out));
 107         if (!dcs->obj) {
 108                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 109                 rte_errno = errno;
 110                 mlx5_free(dcs);
 111                 return NULL;
 112         }
 113         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 114         return dcs;
 115 }
 116
 117 /**
 118  * Query flow counters values.
 119  *
 120  * @param[in] dcs
 121  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 122  * @param[in] clear
 123  *   Whether hardware should clear the counters after the query or not.
 124  * @param[in] n_counters
 125  *   0 in case of 1 counter to read, otherwise the counter number to read.
 126  *  @param pkts
 127  *   The number of packets that matched the flow.
 128  *  @param bytes
 129  *    The number of bytes that matched the flow.
 130  *  @param mkey
 131  *   The mkey key for batch query.
 132  *  @param addr
 133  *    The address in the mkey range for batch query.
 134  *  @param cmd_comp
 135  *   The completion object for asynchronous batch query.
 136  *  @param async_id
 137  *    The ID to be returned in the asynchronous batch query response.
 138  *
 139  * @return
 140  *   0 on success, a negative value otherwise.
 141  */
 142 int
 143 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 144                                  int clear, uint32_t n_counters,
 145                                  uint64_t *pkts, uint64_t *bytes,
 146                                  uint32_t mkey, void *addr,
 147                                  void *cmd_comp,
 148                                  uint64_t async_id)
 149 {
 150         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 151                         MLX5_ST_SZ_BYTES(traffic_counter);
 152         uint32_t out[out_len];
 153         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 154         void *stats;
 155         int rc;
 156
 157         MLX5_SET(query_flow_counter_in, in, opcode,
 158                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 159         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 160         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 161         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 162
 163         if (n_counters) {
 164                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 165                          n_counters);
 166                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 167                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 168                 MLX5_SET64(query_flow_counter_in, in, address,
 169                            (uint64_t)(uintptr_t)addr);
 170         }
 171         if (!cmd_comp)
 172                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 173                                                out_len);
 174         else
 175                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 176                                                      out_len, async_id,
 177                                                      cmd_comp);
 178         if (rc) {
 179                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 180                 rte_errno = rc;
 181                 return -rc;
 182         }
 183         if (!n_counters) {
 184                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 185                                      out, flow_statistics);
 186                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 187                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 188         }
 189         return 0;
 190 }
 191
 192 /**
 193  * Create a new mkey.
 194  *
 195  * @param[in] ctx
 196  *   Context returned from mlx5 open_device() glue function.
 197  * @param[in] attr
 198  *   Attributes of the requested mkey.
 199  *
 200  * @return
 201  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 202  *   is set.
 203  */
 204 struct mlx5_devx_obj *
 205 mlx5_devx_cmd_mkey_create(void *ctx,
 206                           struct mlx5_devx_mkey_attr *attr)
 207 {
 208         struct mlx5_klm *klm_array = attr->klm_array;
 209         int klm_num = attr->klm_num;
 210         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 211                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 212         uint32_t in[in_size_dw];
 213         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 214         void *mkc;
 215         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 216                                                  0, SOCKET_ID_ANY);
 217         size_t pgsize;
 218         uint32_t translation_size;
 219
 220         if (!mkey) {
 221                 rte_errno = ENOMEM;
 222                 return NULL;
 223         }
 224         memset(in, 0, in_size_dw * 4);
 225         pgsize = sysconf(_SC_PAGESIZE);
 226         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 227         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 228         if (klm_num > 0) {
 229                 int i;
 230                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 231                                                        klm_pas_mtt);
 232                 translation_size = RTE_ALIGN(klm_num, 4);
 233                 for (i = 0; i < klm_num; i++) {
 234                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 235                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 236                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 237                         klm += MLX5_ST_SZ_BYTES(klm);
 238                 }
 239                 for (; i < (int)translation_size; i++) {
 240                         MLX5_SET(klm, klm, mkey, 0x0);
 241                         MLX5_SET64(klm, klm, address, 0x0);
 242                         klm += MLX5_ST_SZ_BYTES(klm);
 243                 }
 244                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 245                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 246                          MLX5_MKC_ACCESS_MODE_KLM);
 247                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 248         } else {
 249                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 250                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 251                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 252         }
 253         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 254                  translation_size);
 255         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 256         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 257         MLX5_SET(mkc, mkc, lw, 0x1);
 258         MLX5_SET(mkc, mkc, lr, 0x1);
 259         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 260         MLX5_SET(mkc, mkc, pd, attr->pd);
 261         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 262         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 263         if (attr->relaxed_ordering == 1) {
 264                 MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1);
 265                 MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1);
 266         }
 267         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 268         MLX5_SET64(mkc, mkc, len, attr->size);
 269         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 270                                                sizeof(out));
 271         if (!mkey->obj) {
 272                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
 273                         klm_num ? "an in" : "a ", errno);
 274                 rte_errno = errno;
 275                 mlx5_free(mkey);
 276                 return NULL;
 277         }
 278         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 279         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 280         return mkey;
 281 }
 282
 283 /**
 284  * Get status of devx command response.
 285  * Mainly used for asynchronous commands.
 286  *
 287  * @param[in] out
 288  *   The out response buffer.
 289  *
 290  * @return
 291  *   0 on success, non-zero value otherwise.
 292  */
 293 int
 294 mlx5_devx_get_out_command_status(void *out)
 295 {
 296         int status;
 297
 298         if (!out)
 299                 return -EINVAL;
 300         status = MLX5_GET(query_flow_counter_out, out, status);
 301         if (status) {
 302                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 303
 304                 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
 305                         syndrome);
 306         }
 307         return status;
 308 }
 309
 310 /**
 311  * Destroy any object allocated by a Devx API.
 312  *
 313  * @param[in] obj
 314  *   Pointer to a general object.
 315  *
 316  * @return
 317  *   0 on success, a negative value otherwise.
 318  */
 319 int
 320 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 321 {
 322         int ret;
 323
 324         if (!obj)
 325                 return 0;
 326         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 327         mlx5_free(obj);
 328         return ret;
 329 }
 330
 331 /**
 332  * Query NIC vport context.
 333  * Fills minimal inline attribute.
 334  *
 335  * @param[in] ctx
 336  *   ibv contexts returned from mlx5dv_open_device.
 337  * @param[in] vport
 338  *   vport index
 339  * @param[out] attr
 340  *   Attributes device values.
 341  *
 342  * @return
 343  *   0 on success, a negative value otherwise.
 344  */
 345 static int
 346 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 347                                       unsigned int vport,
 348                                       struct mlx5_hca_attr *attr)
 349 {
 350         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 351         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 352         void *vctx;
 353         int status, syndrome, rc;
 354
 355         /* Query NIC vport context to determine inline mode. */
 356         MLX5_SET(query_nic_vport_context_in, in, opcode,
 357                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 358         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 359         if (vport)
 360                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 361         rc = mlx5_glue->devx_general_cmd(ctx,
 362                                          in, sizeof(in),
 363                                          out, sizeof(out));
 364         if (rc)
 365                 goto error;
 366         status = MLX5_GET(query_nic_vport_context_out, out, status);
 367         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 368         if (status) {
 369                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 370                         "status %x, syndrome = %x",
 371                         status, syndrome);
 372                 return -1;
 373         }
 374         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 375                             nic_vport_context);
 376         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 377                                            min_wqe_inline_mode);
 378         return 0;
 379 error:
 380         rc = (rc > 0) ? -rc : rc;
 381         return rc;
 382 }
 383
 384 /**
 385  * Query NIC vDPA attributes.
 386  *
 387  * @param[in] ctx
 388  *   Context returned from mlx5 open_device() glue function.
 389  * @param[out] vdpa_attr
 390  *   vDPA Attributes structure to fill.
 391  */
 392 static void
 393 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 394                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 395 {
 396         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 397         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 398         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 399         int status, syndrome, rc;
 400
 401         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 402         MLX5_SET(query_hca_cap_in, in, op_mod,
 403                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 404                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 405         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 406         status = MLX5_GET(query_hca_cap_out, out, status);
 407         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 408         if (rc || status) {
 409                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 410                         " status %x, syndrome = %x", status, syndrome);
 411                 vdpa_attr->valid = 0;
 412         } else {
 413                 vdpa_attr->valid = 1;
 414                 vdpa_attr->desc_tunnel_offload_type =
 415                         MLX5_GET(virtio_emulation_cap, hcattr,
 416                                  desc_tunnel_offload_type);
 417                 vdpa_attr->eth_frame_offload_type =
 418                         MLX5_GET(virtio_emulation_cap, hcattr,
 419                                  eth_frame_offload_type);
 420                 vdpa_attr->virtio_version_1_0 =
 421                         MLX5_GET(virtio_emulation_cap, hcattr,
 422                                  virtio_version_1_0);
 423                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 424                                                tso_ipv4);
 425                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 426                                                tso_ipv6);
 427                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 428                                               tx_csum);
 429                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 430                                               rx_csum);
 431                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 432                                                  event_mode);
 433                 vdpa_attr->virtio_queue_type =
 434                         MLX5_GET(virtio_emulation_cap, hcattr,
 435                                  virtio_queue_type);
 436                 vdpa_attr->log_doorbell_stride =
 437                         MLX5_GET(virtio_emulation_cap, hcattr,
 438                                  log_doorbell_stride);
 439                 vdpa_attr->log_doorbell_bar_size =
 440                         MLX5_GET(virtio_emulation_cap, hcattr,
 441                                  log_doorbell_bar_size);
 442                 vdpa_attr->doorbell_bar_offset =
 443                         MLX5_GET64(virtio_emulation_cap, hcattr,
 444                                    doorbell_bar_offset);
 445                 vdpa_attr->max_num_virtio_queues =
 446                         MLX5_GET(virtio_emulation_cap, hcattr,
 447                                  max_num_virtio_queues);
 448                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 449                                                  umem_1_buffer_param_a);
 450                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 451                                                  umem_1_buffer_param_b);
 452                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 453                                                  umem_2_buffer_param_a);
 454                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 455                                                  umem_2_buffer_param_b);
 456                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 457                                                  umem_3_buffer_param_a);
 458                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 459                                                  umem_3_buffer_param_b);
 460         }
 461 }
 462
 463 int
 464 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 465                                   uint32_t ids[], uint32_t num)
 466 {
 467         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 468         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 469         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 470         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 471         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 472         int ret;
 473         uint32_t idx = 0;
 474         uint32_t i;
 475
 476         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 477                 rte_errno = EINVAL;
 478                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 479                 return -rte_errno;
 480         }
 481         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 482                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 483         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 484                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 485         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 486         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 487                                         out, sizeof(out));
 488         if (ret) {
 489                 rte_errno = ret;
 490                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 491                         (void *)flex_obj);
 492                 return -rte_errno;
 493         }
 494         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 495                 void *s_off = (void *)((char *)sample + i *
 496                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 497                 uint32_t en;
 498
 499                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 500                               flow_match_sample_en);
 501                 if (!en)
 502                         continue;
 503                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 504                                   flow_match_sample_field_id);
 505         }
 506         if (num != idx) {
 507                 rte_errno = EINVAL;
 508                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 509                 return -rte_errno;
 510         }
 511         return ret;
 512 }
 513
 514
 515 struct mlx5_devx_obj *
 516 mlx5_devx_cmd_create_flex_parser(void *ctx,
 517                               struct mlx5_devx_graph_node_attr *data)
 518 {
 519         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 520         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 521         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 522         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 523         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 524         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 525         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 526         struct mlx5_devx_obj *parse_flex_obj = NULL;
 527         uint32_t i;
 528
 529         parse_flex_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0,
 530                                      SOCKET_ID_ANY);
 531         if (!parse_flex_obj) {
 532                 DRV_LOG(ERR, "Failed to allocate flex parser data");
 533                 rte_errno = ENOMEM;
 534                 mlx5_free(in);
 535                 return NULL;
 536         }
 537         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 538                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 539         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 540                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 541         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 542                  data->header_length_mode);
 543         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 544                  data->header_length_base_value);
 545         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 546                  data->header_length_field_offset);
 547         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 548                  data->header_length_field_shift);
 549         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 550                  data->header_length_field_mask);
 551         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 552                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 553                 void *s_off = (void *)((char *)sample + i *
 554                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 555
 556                 if (!s->flow_match_sample_en)
 557                         continue;
 558                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 559                          flow_match_sample_en, !!s->flow_match_sample_en);
 560                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 561                          flow_match_sample_field_offset,
 562                          s->flow_match_sample_field_offset);
 563                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 564                          flow_match_sample_offset_mode,
 565                          s->flow_match_sample_offset_mode);
 566                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 567                          flow_match_sample_field_offset_mask,
 568                          s->flow_match_sample_field_offset_mask);
 569                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 570                          flow_match_sample_field_offset_shift,
 571                          s->flow_match_sample_field_offset_shift);
 572                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 573                          flow_match_sample_field_base_offset,
 574                          s->flow_match_sample_field_base_offset);
 575                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 576                          flow_match_sample_tunnel_mode,
 577                          s->flow_match_sample_tunnel_mode);
 578         }
 579         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 580                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 581                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 582                 void *in_off = (void *)((char *)in_arc + i *
 583                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 584                 void *out_off = (void *)((char *)out_arc + i *
 585                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 586
 587                 if (ia->arc_parse_graph_node != 0) {
 588                         MLX5_SET(parse_graph_arc, in_off,
 589                                  compare_condition_value,
 590                                  ia->compare_condition_value);
 591                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 592                                  ia->start_inner_tunnel);
 593                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 594                                  ia->arc_parse_graph_node);
 595                         MLX5_SET(parse_graph_arc, in_off,
 596                                  parse_graph_node_handle,
 597                                  ia->parse_graph_node_handle);
 598                 }
 599                 if (oa->arc_parse_graph_node != 0) {
 600                         MLX5_SET(parse_graph_arc, out_off,
 601                                  compare_condition_value,
 602                                  oa->compare_condition_value);
 603                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 604                                  oa->start_inner_tunnel);
 605                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 606                                  oa->arc_parse_graph_node);
 607                         MLX5_SET(parse_graph_arc, out_off,
 608                                  parse_graph_node_handle,
 609                                  oa->parse_graph_node_handle);
 610                 }
 611         }
 612         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 613                                                          out, sizeof(out));
 614         if (!parse_flex_obj->obj) {
 615                 rte_errno = errno;
 616                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 617                         "by using DevX.");
 618                 mlx5_free(parse_flex_obj);
 619                 return NULL;
 620         }
 621         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 622         return parse_flex_obj;
 623 }
 624
 625 /**
 626  * Query HCA attributes.
 627  * Using those attributes we can check on run time if the device
 628  * is having the required capabilities.
 629  *
 630  * @param[in] ctx
 631  *   Context returned from mlx5 open_device() glue function.
 632  * @param[out] attr
 633  *   Attributes device values.
 634  *
 635  * @return
 636  *   0 on success, a negative value otherwise.
 637  */
 638 int
 639 mlx5_devx_cmd_query_hca_attr(void *ctx,
 640                              struct mlx5_hca_attr *attr)
 641 {
 642         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 643         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 644         void *hcattr;
 645         int status, syndrome, rc, i;
 646
 647         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 648         MLX5_SET(query_hca_cap_in, in, op_mod,
 649                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 650                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 651
 652         rc = mlx5_glue->devx_general_cmd(ctx,
 653                                          in, sizeof(in), out, sizeof(out));
 654         if (rc)
 655                 goto error;
 656         status = MLX5_GET(query_hca_cap_out, out, status);
 657         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 658         if (status) {
 659                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 660                         "status %x, syndrome = %x",
 661                         status, syndrome);
 662                 return -1;
 663         }
 664         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 665         attr->flow_counter_bulk_alloc_bitmap =
 666                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 667         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 668                                             flow_counters_dump);
 669         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 670                                           log_max_rqt_size);
 671         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 672         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 673         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 674                                                 log_max_hairpin_queues);
 675         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 676                                                     log_max_hairpin_wq_data_sz);
 677         attr->log_max_hairpin_num_packets = MLX5_GET
 678                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 679         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 680         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 681                         relaxed_ordering_write);
 682         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 683                         relaxed_ordering_read);
 684         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 685                                           eth_net_offloads);
 686         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 687         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 688                                                flex_parser_protocols);
 689         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 690         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 691                                          general_obj_types) &
 692                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 693         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 694                                                         general_obj_types) &
 695                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 696         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 697                                          general_obj_types) &
 698                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 699         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 700                                           wqe_index_ignore_cap);
 701         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 702         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 703         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 704                                               log_max_static_sq_wq);
 705         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 706                                       device_frequency_khz);
 707         attr->scatter_fcs_w_decap_disable =
 708                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 709         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 710         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 711                                                regexp_num_of_engines);
 712         if (attr->qos.sup) {
 713                 MLX5_SET(query_hca_cap_in, in, op_mod,
 714                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 715                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 716                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 717                                                  out, sizeof(out));
 718                 if (rc)
 719                         goto error;
 720                 if (status) {
 721                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 722                                 " status %x, syndrome = %x",
 723                                 status, syndrome);
 724                         return -1;
 725                 }
 726                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 727                 attr->qos.srtcm_sup =
 728                                 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
 729                 attr->qos.log_max_flow_meter =
 730                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 731                 attr->qos.flow_meter_reg_c_ids =
 732                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 733                 attr->qos.flow_meter_reg_share =
 734                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
 735                 attr->qos.packet_pacing =
 736                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 737                 attr->qos.wqe_rate_pp =
 738                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 739         }
 740         if (attr->vdpa.valid)
 741                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 742         if (!attr->eth_net_offloads)
 743                 return 0;
 744
 745         /* Query HCA offloads for Ethernet protocol. */
 746         memset(in, 0, sizeof(in));
 747         memset(out, 0, sizeof(out));
 748         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 749         MLX5_SET(query_hca_cap_in, in, op_mod,
 750                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 751                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 752
 753         rc = mlx5_glue->devx_general_cmd(ctx,
 754                                          in, sizeof(in),
 755                                          out, sizeof(out));
 756         if (rc) {
 757                 attr->eth_net_offloads = 0;
 758                 goto error;
 759         }
 760         status = MLX5_GET(query_hca_cap_out, out, status);
 761         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 762         if (status) {
 763                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 764                         "status %x, syndrome = %x",
 765                         status, syndrome);
 766                 attr->eth_net_offloads = 0;
 767                 return -1;
 768         }
 769         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 770         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 771                                          hcattr, wqe_vlan_insert);
 772         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 773                                  lro_cap);
 774         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 775                                         hcattr, tunnel_lro_gre);
 776         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 777                                           hcattr, tunnel_lro_vxlan);
 778         attr->lro_max_msg_sz_mode = MLX5_GET
 779                                         (per_protocol_networking_offload_caps,
 780                                          hcattr, lro_max_msg_sz_mode);
 781         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 782                 attr->lro_timer_supported_periods[i] =
 783                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 784                                  lro_timer_supported_periods[i]);
 785         }
 786         attr->tunnel_stateless_geneve_rx =
 787                             MLX5_GET(per_protocol_networking_offload_caps,
 788                                      hcattr, tunnel_stateless_geneve_rx);
 789         attr->geneve_max_opt_len =
 790                     MLX5_GET(per_protocol_networking_offload_caps,
 791                              hcattr, max_geneve_opt_len);
 792         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 793                                          hcattr, wqe_inline_mode);
 794         attr->tunnel_stateless_gtp = MLX5_GET
 795                                         (per_protocol_networking_offload_caps,
 796                                          hcattr, tunnel_stateless_gtp);
 797         if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
 798                 return 0;
 799         if (attr->eth_virt) {
 800                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 801                 if (rc) {
 802                         attr->eth_virt = 0;
 803                         goto error;
 804                 }
 805         }
 806         return 0;
 807 error:
 808         rc = (rc > 0) ? -rc : rc;
 809         return rc;
 810 }
 811
 812 /**
 813  * Query TIS transport domain from QP verbs object using DevX API.
 814  *
 815  * @param[in] qp
 816  *   Pointer to verbs QP returned by ibv_create_qp .
 817  * @param[in] tis_num
 818  *   TIS number of TIS to query.
 819  * @param[out] tis_td
 820  *   Pointer to TIS transport domain variable, to be set by the routine.
 821  *
 822  * @return
 823  *   0 on success, a negative value otherwise.
 824  */
 825 int
 826 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 827                               uint32_t *tis_td)
 828 {
 829 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 830         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 831         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 832         int rc;
 833         void *tis_ctx;
 834
 835         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 836         MLX5_SET(query_tis_in, in, tisn, tis_num);
 837         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 838         if (rc) {
 839                 DRV_LOG(ERR, "Failed to query QP using DevX");
 840                 return -rc;
 841         };
 842         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 843         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 844         return 0;
 845 #else
 846         (void)qp;
 847         (void)tis_num;
 848         (void)tis_td;
 849         return -ENOTSUP;
 850 #endif
 851 }
 852
 853 /**
 854  * Fill WQ data for DevX API command.
 855  * Utility function for use when creating DevX objects containing a WQ.
 856  *
 857  * @param[in] wq_ctx
 858  *   Pointer to WQ context to fill with data.
 859  * @param [in] wq_attr
 860  *   Pointer to WQ attributes structure to fill in WQ context.
 861  */
 862 static void
 863 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 864 {
 865         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 866         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 867         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 868         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 869         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 870         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 871         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 872         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 873         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
 874         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
 875         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
 876         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
 877         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
 878         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
 879         MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
 880         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
 881         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
 882         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
 883         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
 884                  wq_attr->log_hairpin_num_packets);
 885         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
 886         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
 887                  wq_attr->single_wqe_log_num_of_strides);
 888         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
 889         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
 890                  wq_attr->single_stride_log_num_of_bytes);
 891         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
 892         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
 893         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
 894 }
 895
 896 /**
 897  * Create RQ using DevX API.
 898  *
 899  * @param[in] ctx
 900  *   Context returned from mlx5 open_device() glue function.
 901  * @param [in] rq_attr
 902  *   Pointer to create RQ attributes structure.
 903  * @param [in] socket
 904  *   CPU socket ID for allocations.
 905  *
 906  * @return
 907  *   The DevX object created, NULL otherwise and rte_errno is set.
 908  */
 909 struct mlx5_devx_obj *
 910 mlx5_devx_cmd_create_rq(void *ctx,
 911                         struct mlx5_devx_create_rq_attr *rq_attr,
 912                         int socket)
 913 {
 914         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
 915         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
 916         void *rq_ctx, *wq_ctx;
 917         struct mlx5_devx_wq_attr *wq_attr;
 918         struct mlx5_devx_obj *rq = NULL;
 919
 920         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
 921         if (!rq) {
 922                 DRV_LOG(ERR, "Failed to allocate RQ data");
 923                 rte_errno = ENOMEM;
 924                 return NULL;
 925         }
 926         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
 927         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
 928         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
 929         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
 930         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 931         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 932         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
 933         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 934         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
 935         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
 936         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
 937         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
 938         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 939         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
 940         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 941         wq_attr = &rq_attr->wq_attr;
 942         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 943         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 944                                                   out, sizeof(out));
 945         if (!rq->obj) {
 946                 DRV_LOG(ERR, "Failed to create RQ using DevX");
 947                 rte_errno = errno;
 948                 mlx5_free(rq);
 949                 return NULL;
 950         }
 951         rq->id = MLX5_GET(create_rq_out, out, rqn);
 952         return rq;
 953 }
 954
 955 /**
 956  * Modify RQ using DevX API.
 957  *
 958  * @param[in] rq
 959  *   Pointer to RQ object structure.
 960  * @param [in] rq_attr
 961  *   Pointer to modify RQ attributes structure.
 962  *
 963  * @return
 964  *   0 on success, a negative errno value otherwise and rte_errno is set.
 965  */
 966 int
 967 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
 968                         struct mlx5_devx_modify_rq_attr *rq_attr)
 969 {
 970         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
 971         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
 972         void *rq_ctx, *wq_ctx;
 973         int ret;
 974
 975         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
 976         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
 977         MLX5_SET(modify_rq_in, in, rqn, rq->id);
 978         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
 979         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 980         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 981         if (rq_attr->modify_bitmask &
 982                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
 983                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 984         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
 985                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 986         if (rq_attr->modify_bitmask &
 987                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
 988                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 989         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
 990         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
 991         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
 992                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 993                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
 994         }
 995         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
 996                                          out, sizeof(out));
 997         if (ret) {
 998                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
 999                 rte_errno = errno;
1000                 return -errno;
1001         }
1002         return ret;
1003 }
1004
1005 /**
1006  * Create TIR using DevX API.
1007  *
1008  * @param[in] ctx
1009  *  Context returned from mlx5 open_device() glue function.
1010  * @param [in] tir_attr
1011  *   Pointer to TIR attributes structure.
1012  *
1013  * @return
1014  *   The DevX object created, NULL otherwise and rte_errno is set.
1015  */
1016 struct mlx5_devx_obj *
1017 mlx5_devx_cmd_create_tir(void *ctx,
1018                          struct mlx5_devx_tir_attr *tir_attr)
1019 {
1020         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1021         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1022         void *tir_ctx, *outer, *inner, *rss_key;
1023         struct mlx5_devx_obj *tir = NULL;
1024
1025         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1026         if (!tir) {
1027                 DRV_LOG(ERR, "Failed to allocate TIR data");
1028                 rte_errno = ENOMEM;
1029                 return NULL;
1030         }
1031         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1032         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1033         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1034         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1035                  tir_attr->lro_timeout_period_usecs);
1036         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1037         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1038         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1039         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1040         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1041                  tir_attr->tunneled_offload_en);
1042         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1043         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1044         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1045         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1046         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1047         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1048         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1049         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1050                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1051         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1052                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1053         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1054                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1055         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1056         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1057                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1058         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1059                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1060         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1061                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1062         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1063                                                    out, sizeof(out));
1064         if (!tir->obj) {
1065                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1066                 rte_errno = errno;
1067                 mlx5_free(tir);
1068                 return NULL;
1069         }
1070         tir->id = MLX5_GET(create_tir_out, out, tirn);
1071         return tir;
1072 }
1073
1074 /**
1075  * Create RQT using DevX API.
1076  *
1077  * @param[in] ctx
1078  *   Context returned from mlx5 open_device() glue function.
1079  * @param [in] rqt_attr
1080  *   Pointer to RQT attributes structure.
1081  *
1082  * @return
1083  *   The DevX object created, NULL otherwise and rte_errno is set.
1084  */
1085 struct mlx5_devx_obj *
1086 mlx5_devx_cmd_create_rqt(void *ctx,
1087                          struct mlx5_devx_rqt_attr *rqt_attr)
1088 {
1089         uint32_t *in = NULL;
1090         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1091                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1092         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1093         void *rqt_ctx;
1094         struct mlx5_devx_obj *rqt = NULL;
1095         int i;
1096
1097         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1098         if (!in) {
1099                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1100                 rte_errno = ENOMEM;
1101                 return NULL;
1102         }
1103         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1104         if (!rqt) {
1105                 DRV_LOG(ERR, "Failed to allocate RQT data");
1106                 rte_errno = ENOMEM;
1107                 mlx5_free(in);
1108                 return NULL;
1109         }
1110         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1111         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1112         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1113         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1114         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1115         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1116                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1117         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1118         mlx5_free(in);
1119         if (!rqt->obj) {
1120                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1121                 rte_errno = errno;
1122                 mlx5_free(rqt);
1123                 return NULL;
1124         }
1125         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1126         return rqt;
1127 }
1128
1129 /**
1130  * Modify RQT using DevX API.
1131  *
1132  * @param[in] rqt
1133  *   Pointer to RQT DevX object structure.
1134  * @param [in] rqt_attr
1135  *   Pointer to RQT attributes structure.
1136  *
1137  * @return
1138  *   0 on success, a negative errno value otherwise and rte_errno is set.
1139  */
1140 int
1141 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1142                          struct mlx5_devx_rqt_attr *rqt_attr)
1143 {
1144         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1145                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1146         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1147         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1148         void *rqt_ctx;
1149         int i;
1150         int ret;
1151
1152         if (!in) {
1153                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1154                 rte_errno = ENOMEM;
1155                 return -ENOMEM;
1156         }
1157         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1158         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1159         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1160         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1161         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1162         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1163         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1164         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1165                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1166         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1167         mlx5_free(in);
1168         if (ret) {
1169                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1170                 rte_errno = errno;
1171                 return -rte_errno;
1172         }
1173         return ret;
1174 }
1175
1176 /**
1177  * Create SQ using DevX API.
1178  *
1179  * @param[in] ctx
1180  *   Context returned from mlx5 open_device() glue function.
1181  * @param [in] sq_attr
1182  *   Pointer to SQ attributes structure.
1183  * @param [in] socket
1184  *   CPU socket ID for allocations.
1185  *
1186  * @return
1187  *   The DevX object created, NULL otherwise and rte_errno is set.
1188  **/
1189 struct mlx5_devx_obj *
1190 mlx5_devx_cmd_create_sq(void *ctx,
1191                         struct mlx5_devx_create_sq_attr *sq_attr)
1192 {
1193         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1194         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1195         void *sq_ctx;
1196         void *wq_ctx;
1197         struct mlx5_devx_wq_attr *wq_attr;
1198         struct mlx5_devx_obj *sq = NULL;
1199
1200         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1201         if (!sq) {
1202                 DRV_LOG(ERR, "Failed to allocate SQ data");
1203                 rte_errno = ENOMEM;
1204                 return NULL;
1205         }
1206         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1207         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1208         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1209         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1210         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1211         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1212         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1213                  sq_attr->flush_in_error_en);
1214         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1215                  sq_attr->min_wqe_inline_mode);
1216         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1217         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1218         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1219         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1220         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1221         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1222         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1223         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1224         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1225                  sq_attr->packet_pacing_rate_limit_index);
1226         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1227         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1228         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1229         wq_attr = &sq_attr->wq_attr;
1230         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1231         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1232                                              out, sizeof(out));
1233         if (!sq->obj) {
1234                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1235                 rte_errno = errno;
1236                 mlx5_free(sq);
1237                 return NULL;
1238         }
1239         sq->id = MLX5_GET(create_sq_out, out, sqn);
1240         return sq;
1241 }
1242
1243 /**
1244  * Modify SQ using DevX API.
1245  *
1246  * @param[in] sq
1247  *   Pointer to SQ object structure.
1248  * @param [in] sq_attr
1249  *   Pointer to SQ attributes structure.
1250  *
1251  * @return
1252  *   0 on success, a negative errno value otherwise and rte_errno is set.
1253  */
1254 int
1255 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1256                         struct mlx5_devx_modify_sq_attr *sq_attr)
1257 {
1258         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1259         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1260         void *sq_ctx;
1261         int ret;
1262
1263         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1264         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1265         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1266         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1267         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1268         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1269         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1270         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1271                                          out, sizeof(out));
1272         if (ret) {
1273                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1274                 rte_errno = errno;
1275                 return -rte_errno;
1276         }
1277         return ret;
1278 }
1279
1280 /**
1281  * Create TIS using DevX API.
1282  *
1283  * @param[in] ctx
1284  *   Context returned from mlx5 open_device() glue function.
1285  * @param [in] tis_attr
1286  *   Pointer to TIS attributes structure.
1287  *
1288  * @return
1289  *   The DevX object created, NULL otherwise and rte_errno is set.
1290  */
1291 struct mlx5_devx_obj *
1292 mlx5_devx_cmd_create_tis(void *ctx,
1293                          struct mlx5_devx_tis_attr *tis_attr)
1294 {
1295         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1296         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1297         struct mlx5_devx_obj *tis = NULL;
1298         void *tis_ctx;
1299
1300         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1301         if (!tis) {
1302                 DRV_LOG(ERR, "Failed to allocate TIS object");
1303                 rte_errno = ENOMEM;
1304                 return NULL;
1305         }
1306         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1307         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1308         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1309                  tis_attr->strict_lag_tx_port_affinity);
1310         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1311                  tis_attr->strict_lag_tx_port_affinity);
1312         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1313         MLX5_SET(tisc, tis_ctx, transport_domain,
1314                  tis_attr->transport_domain);
1315         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1316                                               out, sizeof(out));
1317         if (!tis->obj) {
1318                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1319                 rte_errno = errno;
1320                 mlx5_free(tis);
1321                 return NULL;
1322         }
1323         tis->id = MLX5_GET(create_tis_out, out, tisn);
1324         return tis;
1325 }
1326
1327 /**
1328  * Create transport domain using DevX API.
1329  *
1330  * @param[in] ctx
1331  *   Context returned from mlx5 open_device() glue function.
1332  * @return
1333  *   The DevX object created, NULL otherwise and rte_errno is set.
1334  */
1335 struct mlx5_devx_obj *
1336 mlx5_devx_cmd_create_td(void *ctx)
1337 {
1338         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1339         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1340         struct mlx5_devx_obj *td = NULL;
1341
1342         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1343         if (!td) {
1344                 DRV_LOG(ERR, "Failed to allocate TD object");
1345                 rte_errno = ENOMEM;
1346                 return NULL;
1347         }
1348         MLX5_SET(alloc_transport_domain_in, in, opcode,
1349                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1350         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1351                                              out, sizeof(out));
1352         if (!td->obj) {
1353                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1354                 rte_errno = errno;
1355                 mlx5_free(td);
1356                 return NULL;
1357         }
1358         td->id = MLX5_GET(alloc_transport_domain_out, out,
1359                            transport_domain);
1360         return td;
1361 }
1362
1363 /**
1364  * Dump all flows to file.
1365  *
1366  * @param[in] fdb_domain
1367  *   FDB domain.
1368  * @param[in] rx_domain
1369  *   RX domain.
1370  * @param[in] tx_domain
1371  *   TX domain.
1372  * @param[out] file
1373  *   Pointer to file stream.
1374  *
1375  * @return
1376  *   0 on success, a nagative value otherwise.
1377  */
1378 int
1379 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1380                         void *rx_domain __rte_unused,
1381                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1382 {
1383         int ret = 0;
1384
1385 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1386         if (fdb_domain) {
1387                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1388                 if (ret)
1389                         return ret;
1390         }
1391         MLX5_ASSERT(rx_domain);
1392         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1393         if (ret)
1394                 return ret;
1395         MLX5_ASSERT(tx_domain);
1396         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1397 #else
1398         ret = ENOTSUP;
1399 #endif
1400         return -ret;
1401 }
1402
1403 /*
1404  * Create CQ using DevX API.
1405  *
1406  * @param[in] ctx
1407  *   Context returned from mlx5 open_device() glue function.
1408  * @param [in] attr
1409  *   Pointer to CQ attributes structure.
1410  *
1411  * @return
1412  *   The DevX object created, NULL otherwise and rte_errno is set.
1413  */
1414 struct mlx5_devx_obj *
1415 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1416 {
1417         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1418         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1419         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1420                                                    sizeof(*cq_obj),
1421                                                    0, SOCKET_ID_ANY);
1422         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1423
1424         if (!cq_obj) {
1425                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1426                 rte_errno = ENOMEM;
1427                 return NULL;
1428         }
1429         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1430         if (attr->db_umem_valid) {
1431                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1432                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1433                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1434         } else {
1435                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1436         }
1437         MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1438         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1439         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1440         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1441         MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
1442                  MLX5_ADAPTER_PAGE_SHIFT);
1443         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1444         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1445         if (attr->q_umem_valid) {
1446                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1447                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1448                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1449                            attr->q_umem_offset);
1450         }
1451         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1452                                                  sizeof(out));
1453         if (!cq_obj->obj) {
1454                 rte_errno = errno;
1455                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1456                 mlx5_free(cq_obj);
1457                 return NULL;
1458         }
1459         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1460         return cq_obj;
1461 }
1462
1463 /**
1464  * Create VIRTQ using DevX API.
1465  *
1466  * @param[in] ctx
1467  *   Context returned from mlx5 open_device() glue function.
1468  * @param [in] attr
1469  *   Pointer to VIRTQ attributes structure.
1470  *
1471  * @return
1472  *   The DevX object created, NULL otherwise and rte_errno is set.
1473  */
1474 struct mlx5_devx_obj *
1475 mlx5_devx_cmd_create_virtq(void *ctx,
1476                            struct mlx5_devx_virtq_attr *attr)
1477 {
1478         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1479         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1480         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1481                                                      sizeof(*virtq_obj),
1482                                                      0, SOCKET_ID_ANY);
1483         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1484         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1485         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1486
1487         if (!virtq_obj) {
1488                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1489                 rte_errno = ENOMEM;
1490                 return NULL;
1491         }
1492         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1493                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1494         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1495                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1496         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1497                    attr->hw_available_index);
1498         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1499         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1500         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1501         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1502         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1503         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1504                    attr->virtio_version_1_0);
1505         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1506         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1507         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1508         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1509         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1510         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1511         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1512         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1513         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1514         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1515         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1516         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1517         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1518         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1519         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1520         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1521         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1522         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1523         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1524         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1525         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1526                                                     sizeof(out));
1527         if (!virtq_obj->obj) {
1528                 rte_errno = errno;
1529                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1530                 mlx5_free(virtq_obj);
1531                 return NULL;
1532         }
1533         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1534         return virtq_obj;
1535 }
1536
1537 /**
1538  * Modify VIRTQ using DevX API.
1539  *
1540  * @param[in] virtq_obj
1541  *   Pointer to virtq object structure.
1542  * @param [in] attr
1543  *   Pointer to modify virtq attributes structure.
1544  *
1545  * @return
1546  *   0 on success, a negative errno value otherwise and rte_errno is set.
1547  */
1548 int
1549 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1550                            struct mlx5_devx_virtq_attr *attr)
1551 {
1552         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1553         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1554         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1555         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1556         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1557         int ret;
1558
1559         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1560                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1561         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1562                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1563         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1564         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1565         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1566         switch (attr->type) {
1567         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1568                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1569                 break;
1570         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1571                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1572                          attr->dirty_bitmap_mkey);
1573                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1574                          attr->dirty_bitmap_addr);
1575                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1576                          attr->dirty_bitmap_size);
1577                 break;
1578         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1579                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1580                          attr->dirty_bitmap_dump_enable);
1581                 break;
1582         default:
1583                 rte_errno = EINVAL;
1584                 return -rte_errno;
1585         }
1586         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1587                                          out, sizeof(out));
1588         if (ret) {
1589                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1590                 rte_errno = errno;
1591                 return -rte_errno;
1592         }
1593         return ret;
1594 }
1595
1596 /**
1597  * Query VIRTQ using DevX API.
1598  *
1599  * @param[in] virtq_obj
1600  *   Pointer to virtq object structure.
1601  * @param [in/out] attr
1602  *   Pointer to virtq attributes structure.
1603  *
1604  * @return
1605  *   0 on success, a negative errno value otherwise and rte_errno is set.
1606  */
1607 int
1608 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1609                            struct mlx5_devx_virtq_attr *attr)
1610 {
1611         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1612         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1613         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1614         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1615         int ret;
1616
1617         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1618                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1619         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1620                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1621         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1622         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1623                                          out, sizeof(out));
1624         if (ret) {
1625                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1626                 rte_errno = errno;
1627                 return -errno;
1628         }
1629         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1630                                               hw_available_index);
1631         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1632         return ret;
1633 }
1634
1635 /**
1636  * Create QP using DevX API.
1637  *
1638  * @param[in] ctx
1639  *   Context returned from mlx5 open_device() glue function.
1640  * @param [in] attr
1641  *   Pointer to QP attributes structure.
1642  *
1643  * @return
1644  *   The DevX object created, NULL otherwise and rte_errno is set.
1645  */
1646 struct mlx5_devx_obj *
1647 mlx5_devx_cmd_create_qp(void *ctx,
1648                         struct mlx5_devx_qp_attr *attr)
1649 {
1650         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1651         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1652         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1653                                                    sizeof(*qp_obj),
1654                                                    0, SOCKET_ID_ANY);
1655         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1656
1657         if (!qp_obj) {
1658                 DRV_LOG(ERR, "Failed to allocate QP data.");
1659                 rte_errno = ENOMEM;
1660                 return NULL;
1661         }
1662         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1663         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1664         MLX5_SET(qpc, qpc, pd, attr->pd);
1665         if (attr->uar_index) {
1666                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1667                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1668                 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
1669                          MLX5_ADAPTER_PAGE_SHIFT);
1670                 if (attr->sq_size) {
1671                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1672                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1673                         MLX5_SET(qpc, qpc, log_sq_size,
1674                                  rte_log2_u32(attr->sq_size));
1675                 } else {
1676                         MLX5_SET(qpc, qpc, no_sq, 1);
1677                 }
1678                 if (attr->rq_size) {
1679                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1680                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1681                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1682                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1683                         MLX5_SET(qpc, qpc, log_rq_size,
1684                                  rte_log2_u32(attr->rq_size));
1685                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1686                 } else {
1687                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1688                 }
1689                 if (attr->dbr_umem_valid) {
1690                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1691                                  attr->dbr_umem_valid);
1692                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1693                 }
1694                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1695                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1696                            attr->wq_umem_offset);
1697                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1698                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1699         } else {
1700                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1701                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1702                 MLX5_SET(qpc, qpc, no_sq, 1);
1703         }
1704         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1705                                                  sizeof(out));
1706         if (!qp_obj->obj) {
1707                 rte_errno = errno;
1708                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1709                 mlx5_free(qp_obj);
1710                 return NULL;
1711         }
1712         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1713         return qp_obj;
1714 }
1715
1716 /**
1717  * Modify QP using DevX API.
1718  * Currently supports only force loop-back QP.
1719  *
1720  * @param[in] qp
1721  *   Pointer to QP object structure.
1722  * @param [in] qp_st_mod_op
1723  *   The QP state modification operation.
1724  * @param [in] remote_qp_id
1725  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1726  *
1727  * @return
1728  *   0 on success, a negative errno value otherwise and rte_errno is set.
1729  */
1730 int
1731 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1732                               uint32_t remote_qp_id)
1733 {
1734         union {
1735                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1736                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1737                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1738         } in;
1739         union {
1740                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1741                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1742                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1743         } out;
1744         void *qpc;
1745         int ret;
1746         unsigned int inlen;
1747         unsigned int outlen;
1748
1749         memset(&in, 0, sizeof(in));
1750         memset(&out, 0, sizeof(out));
1751         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1752         switch (qp_st_mod_op) {
1753         case MLX5_CMD_OP_RST2INIT_QP:
1754                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1755                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1756                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1757                 MLX5_SET(qpc, qpc, rre, 1);
1758                 MLX5_SET(qpc, qpc, rwe, 1);
1759                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1760                 inlen = sizeof(in.rst2init);
1761                 outlen = sizeof(out.rst2init);
1762                 break;
1763         case MLX5_CMD_OP_INIT2RTR_QP:
1764                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1765                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1766                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1767                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1768                 MLX5_SET(qpc, qpc, mtu, 1);
1769                 MLX5_SET(qpc, qpc, log_msg_max, 30);
1770                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1771                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1772                 inlen = sizeof(in.init2rtr);
1773                 outlen = sizeof(out.init2rtr);
1774                 break;
1775         case MLX5_CMD_OP_RTR2RTS_QP:
1776                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1777                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1778                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1779                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1780                 MLX5_SET(qpc, qpc, retry_count, 7);
1781                 MLX5_SET(qpc, qpc, rnr_retry, 7);
1782                 inlen = sizeof(in.rtr2rts);
1783                 outlen = sizeof(out.rtr2rts);
1784                 break;
1785         default:
1786                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1787                         qp_st_mod_op);
1788                 rte_errno = EINVAL;
1789                 return -rte_errno;
1790         }
1791         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1792         if (ret) {
1793                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
1794                 rte_errno = errno;
1795                 return -rte_errno;
1796         }
1797         return ret;
1798 }
1799
1800 struct mlx5_devx_obj *
1801 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
1802 {
1803         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
1804         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1805         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
1806                                                        sizeof(*couners_obj), 0,
1807                                                        SOCKET_ID_ANY);
1808         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
1809
1810         if (!couners_obj) {
1811                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
1812                 rte_errno = ENOMEM;
1813                 return NULL;
1814         }
1815         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1816                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1817         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1818                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1819         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1820                                                       sizeof(out));
1821         if (!couners_obj->obj) {
1822                 rte_errno = errno;
1823                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
1824                         " DevX.");
1825                 mlx5_free(couners_obj);
1826                 return NULL;
1827         }
1828         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1829         return couners_obj;
1830 }
1831
1832 int
1833 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
1834                                    struct mlx5_devx_virtio_q_couners_attr *attr)
1835 {
1836         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1837         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
1838         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
1839         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
1840                                                virtio_q_counters);
1841         int ret;
1842
1843         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1844                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1845         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1846                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1847         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
1848         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
1849                                         sizeof(out));
1850         if (ret) {
1851                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
1852                 rte_errno = errno;
1853                 return -errno;
1854         }
1855         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1856                                          received_desc);
1857         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1858                                           completed_desc);
1859         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
1860                                     error_cqes);
1861         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
1862                                          bad_desc_errors);
1863         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
1864                                           exceed_max_chain);
1865         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
1866                                         invalid_buffer);
1867         return ret;
1868 }