common/mlx5: query scatter FCS with decap capability
authorSuanming Mou <suanmingm@mellanox.com>
Wed, 15 Jul 2020 13:10:20 +0000 (21:10 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 21 Jul 2020 13:46:30 +0000 (15:46 +0200)
As scatter FCS might be not supported for decapsulated tunnel
packets in some NIC HW, a new capability bit which indicates
if scatter FCS works with decap is added.

Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
doc/guides/nics/mlx5.rst
drivers/common/mlx5/mlx5_devx_cmds.c
drivers/common/mlx5/mlx5_devx_cmds.h
drivers/common/mlx5/mlx5_prm.h

index 00427b0..efb9cd5 100644 (file)
@@ -297,6 +297,12 @@ Limitations
 
     Other TCP packets (e.g. with MPLS label) received on Rx queue with LRO enabled, will be received with bad checksum.
 
+- CRC:
+
+  - ``DEV_RX_OFFLOAD_KEEP_CRC`` cannot be supported with decapsulation
+    for some NICs (such as ConnectX-6 Dx and BlueField 2).
+    The capability bit ``scatter_fcs_w_decap_disable`` shows NIC support.
+
 Statistics
 ----------
 
index bc7ce64..66b8d24 100644 (file)
@@ -704,6 +704,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
                                              log_max_static_sq_wq);
        attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
                                      device_frequency_khz);
+       attr->scatter_fcs_w_decap_disable =
+               MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
        attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
        attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
                                               regexp_num_of_engines);
index 620d285..ab61454 100644 (file)
@@ -98,6 +98,7 @@ struct mlx5_hca_attr {
        uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
        uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
        uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
+       uint32_t scatter_fcs_w_decap_disable:1;
        uint32_t regex:1;
        uint32_t regexp_num_of_engines;
        struct mlx5_hca_qos_attr qos;
index c424c6b..adf5299 100644 (file)
@@ -1100,7 +1100,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8 log_max_srq[0x5];
        u8 reserved_at_b0[0x3];
        u8 regexp_log_crspace_size[0x5];
-       u8 reserved_at_b8[0x8];
+       u8 reserved_at_b8[0x3];
+       u8 scatter_fcs_w_decap_disable[0x1];
+       u8 reserved_at_bc[0x4];
        u8 reserved_at_c0[0x8];
        u8 log_max_cq_sz[0x8];
        u8 reserved_at_d0[0xb];