1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* This is limitation of libibverbs: in length variable type is u16. */
13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
16 struct mlx5_devx_mkey_attr {
21 uint32_t log_entity_size;
23 uint32_t relaxed_ordering:1;
24 struct mlx5_klm *klm_array;
28 /* HCA qos attributes. */
29 struct mlx5_hca_qos_attr {
30 uint32_t sup:1; /* Whether QOS is supported. */
31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
32 uint32_t packet_pacing:1; /* Packet pacing is supported. */
33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
34 uint32_t flow_meter_reg_share:1;
35 /* Whether reg_c share is supported. */
36 uint8_t log_max_flow_meter;
37 /* Power of the maximum supported meters. */
38 uint8_t flow_meter_reg_c_ids;
39 /* Bitmap of the reg_Cs available for flow meter to use. */
43 struct mlx5_hca_vdpa_attr {
44 uint8_t virtio_queue_type;
46 uint32_t desc_tunnel_offload_type:1;
47 uint32_t eth_frame_offload_type:1;
48 uint32_t virtio_version_1_0:1;
53 uint32_t event_mode:3;
54 uint32_t log_doorbell_stride:5;
55 uint32_t log_doorbell_bar_size:5;
56 uint32_t queue_counters_valid:1;
57 uint32_t max_num_virtio_queues;
62 uint64_t doorbell_bar_offset;
65 /* HCA supports this number of time periods for LRO. */
66 #define MLX5_LRO_NUM_SUPP_PERIODS 4
69 struct mlx5_hca_attr {
70 uint32_t eswitch_manager:1;
71 uint32_t flow_counters_dump:1;
72 uint32_t log_max_rqt_size:5;
73 uint32_t parse_graph_flex_node:1;
74 uint8_t flow_counter_bulk_alloc_bitmap;
75 uint32_t eth_net_offloads:1;
77 uint32_t wqe_vlan_insert:1;
78 uint32_t wqe_inline_mode:2;
79 uint32_t vport_inline_mode:3;
80 uint32_t tunnel_stateless_geneve_rx:1;
81 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
82 uint32_t tunnel_stateless_gtp:1;
84 uint32_t tunnel_lro_gre:1;
85 uint32_t tunnel_lro_vxlan:1;
86 uint32_t lro_max_msg_sz_mode:2;
87 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
88 uint32_t flex_parser_protocols;
90 uint32_t log_max_hairpin_queues:5;
91 uint32_t log_max_hairpin_wq_data_sz:5;
92 uint32_t log_max_hairpin_num_packets:5;
94 uint32_t relaxed_ordering_write:1;
95 uint32_t relaxed_ordering_read:1;
96 uint32_t wqe_index_ignore:1;
97 uint32_t cross_channel:1;
98 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
99 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
100 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
101 uint32_t scatter_fcs_w_decap_disable:1;
103 uint32_t regexp_num_of_engines;
104 struct mlx5_hca_qos_attr qos;
105 struct mlx5_hca_vdpa_attr vdpa;
108 struct mlx5_devx_wq_attr {
110 uint32_t wq_signature:1;
111 uint32_t end_padding_mode:2;
113 uint32_t hds_skip_first_sge:1;
114 uint32_t log2_hds_buf_size:3;
115 uint32_t page_offset:5;
118 uint32_t uar_page:24;
122 uint32_t log_wq_stride:4;
123 uint32_t log_wq_pg_sz:5;
124 uint32_t log_wq_sz:5;
125 uint32_t dbr_umem_valid:1;
126 uint32_t wq_umem_valid:1;
127 uint32_t log_hairpin_num_packets:5;
128 uint32_t log_hairpin_data_sz:5;
129 uint32_t single_wqe_log_num_of_strides:4;
130 uint32_t two_byte_shift_en:1;
131 uint32_t single_stride_log_num_of_bytes:3;
132 uint32_t dbr_umem_id;
134 uint64_t wq_umem_offset;
137 /* Create RQ attributes structure, used by create RQ operation. */
138 struct mlx5_devx_create_rq_attr {
140 uint32_t delay_drop_en:1;
141 uint32_t scatter_fcs:1;
143 uint32_t mem_rq_type:4;
145 uint32_t flush_in_error_en:1;
147 uint32_t user_index:24;
149 uint32_t counter_set_id:8;
151 struct mlx5_devx_wq_attr wq_attr;
154 /* Modify RQ attributes structure, used by modify RQ operation. */
155 struct mlx5_devx_modify_rq_attr {
157 uint32_t rq_state:4; /* Current RQ state. */
158 uint32_t state:4; /* Required RQ state. */
159 uint32_t scatter_fcs:1;
161 uint32_t counter_set_id:8;
162 uint32_t hairpin_peer_sq:24;
163 uint32_t hairpin_peer_vhca:16;
164 uint64_t modify_bitmask;
165 uint32_t lwm:16; /* Contained WQ lwm. */
168 struct mlx5_rx_hash_field_select {
169 uint32_t l3_prot_type:1;
170 uint32_t l4_prot_type:1;
171 uint32_t selected_fields:30;
174 /* TIR attributes structure, used by TIR operations. */
175 struct mlx5_devx_tir_attr {
176 uint32_t disp_type:4;
177 uint32_t lro_timeout_period_usecs:16;
178 uint32_t lro_enable_mask:4;
179 uint32_t lro_max_msg_sz:8;
180 uint32_t inline_rqn:24;
181 uint32_t rx_hash_symmetric:1;
182 uint32_t tunneled_offload_en:1;
183 uint32_t indirect_table:24;
184 uint32_t rx_hash_fn:4;
185 uint32_t self_lb_block:2;
186 uint32_t transport_domain:24;
187 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
188 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
189 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
192 /* RQT attributes structure, used by RQT operations. */
193 struct mlx5_devx_rqt_attr {
195 uint32_t rqt_max_size:16;
196 uint32_t rqt_actual_size:16;
200 /* TIS attributes structure. */
201 struct mlx5_devx_tis_attr {
202 uint32_t strict_lag_tx_port_affinity:1;
204 uint32_t lag_tx_port_affinity:4;
206 uint32_t transport_domain:24;
209 /* SQ attributes structure, used by SQ create operation. */
210 struct mlx5_devx_create_sq_attr {
212 uint32_t cd_master:1;
214 uint32_t flush_in_error_en:1;
215 uint32_t allow_multi_pkt_send_wqe:1;
216 uint32_t min_wqe_inline_mode:3;
219 uint32_t allow_swp:1;
222 uint32_t static_sq_wq:1;
223 uint32_t user_index:24;
225 uint32_t packet_pacing_rate_limit_index:16;
226 uint32_t tis_lst_sz:16;
228 struct mlx5_devx_wq_attr wq_attr;
231 /* SQ attributes structure, used by SQ modify operation. */
232 struct mlx5_devx_modify_sq_attr {
235 uint32_t hairpin_peer_rq:24;
236 uint32_t hairpin_peer_vhca:16;
240 /* CQ attributes structure, used by CQ operations. */
241 struct mlx5_devx_cq_attr {
242 uint32_t q_umem_valid:1;
243 uint32_t db_umem_valid:1;
244 uint32_t use_first_only:1;
245 uint32_t overrun_ignore:1;
247 uint32_t log_cq_size:5;
248 uint32_t log_page_size:5;
249 uint32_t uar_page_id;
251 uint64_t q_umem_offset;
253 uint64_t db_umem_offset;
258 /* Virtq attributes structure, used by VIRTQ operations. */
259 struct mlx5_devx_virtq_attr {
260 uint16_t hw_available_index;
261 uint16_t hw_used_index;
264 uint32_t virtio_version_1_0:1;
269 uint32_t event_mode:3;
271 uint32_t dirty_bitmap_dump_enable:1;
272 uint32_t dirty_bitmap_mkey;
273 uint32_t dirty_bitmap_size;
276 uint32_t queue_index;
278 uint32_t counters_obj_id;
279 uint64_t dirty_bitmap_addr;
283 uint64_t available_addr;
292 struct mlx5_devx_qp_attr {
294 uint32_t uar_index:24;
296 uint32_t log_page_size:5;
297 uint32_t rq_size:17; /* Must be power of 2. */
298 uint32_t log_rq_stride:3;
299 uint32_t sq_size:17; /* Must be power of 2. */
300 uint32_t dbr_umem_valid:1;
301 uint32_t dbr_umem_id;
302 uint64_t dbr_address;
304 uint64_t wq_umem_offset;
307 struct mlx5_devx_virtio_q_couners_attr {
308 uint64_t received_desc;
309 uint64_t completed_desc;
311 uint32_t bad_desc_errors;
312 uint32_t exceed_max_chain;
313 uint32_t invalid_buffer;
317 * graph flow match sample attributes structure,
318 * used by flex parser operations.
320 struct mlx5_devx_match_sample_attr {
321 uint32_t flow_match_sample_en:1;
322 uint32_t flow_match_sample_field_offset:16;
323 uint32_t flow_match_sample_offset_mode:4;
324 uint32_t flow_match_sample_field_offset_mask;
325 uint32_t flow_match_sample_field_offset_shift:4;
326 uint32_t flow_match_sample_field_base_offset:8;
327 uint32_t flow_match_sample_tunnel_mode:3;
328 uint32_t flow_match_sample_field_id;
331 /* graph node arc attributes structure, used by flex parser operations. */
332 struct mlx5_devx_graph_arc_attr {
333 uint32_t compare_condition_value:16;
334 uint32_t start_inner_tunnel:1;
335 uint32_t arc_parse_graph_node:8;
336 uint32_t parse_graph_node_handle;
339 /* Maximal number of samples per graph node. */
340 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
342 /* Maximal number of input/output arcs per graph node. */
343 #define MLX5_GRAPH_NODE_ARC_NUM 8
345 /* parse graph node attributes structure, used by flex parser operations. */
346 struct mlx5_devx_graph_node_attr {
347 uint32_t modify_field_select;
348 uint32_t header_length_mode:4;
349 uint32_t header_length_base_value:16;
350 uint32_t header_length_field_shift:4;
351 uint32_t header_length_field_offset:16;
352 uint32_t header_length_field_mask;
353 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
354 uint32_t next_header_field_offset:16;
355 uint32_t next_header_field_size:5;
356 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
357 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
360 /* mlx5_devx_cmds.c */
363 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
366 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
368 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
369 int clear, uint32_t n_counters,
370 uint64_t *pkts, uint64_t *bytes,
371 uint32_t mkey, void *addr,
375 int mlx5_devx_cmd_query_hca_attr(void *ctx,
376 struct mlx5_hca_attr *attr);
378 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
379 struct mlx5_devx_mkey_attr *attr);
381 int mlx5_devx_get_out_command_status(void *out);
383 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
386 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
387 struct mlx5_devx_create_rq_attr *rq_attr,
390 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
391 struct mlx5_devx_modify_rq_attr *rq_attr);
393 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
394 struct mlx5_devx_tir_attr *tir_attr);
396 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
397 struct mlx5_devx_rqt_attr *rqt_attr);
399 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
400 struct mlx5_devx_create_sq_attr *sq_attr);
402 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
403 struct mlx5_devx_modify_sq_attr *sq_attr);
405 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
406 struct mlx5_devx_tis_attr *tis_attr);
408 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
410 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
413 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
414 struct mlx5_devx_cq_attr *attr);
416 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
417 struct mlx5_devx_virtq_attr *attr);
419 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
420 struct mlx5_devx_virtq_attr *attr);
422 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
423 struct mlx5_devx_virtq_attr *attr);
425 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
426 struct mlx5_devx_qp_attr *attr);
428 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
429 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
431 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
432 struct mlx5_devx_rqt_attr *rqt_attr);
434 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
435 uint32_t ids[], uint32_t num);
438 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
439 struct mlx5_devx_graph_node_attr *data);
442 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
443 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
445 * Create virtio queue counters object DevX API.
451 * The DevX object created, NULL otherwise and rte_errno is set.
454 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
457 * Query virtio queue counters object using DevX API.
459 * @param[in] couners_obj
460 * Pointer to virtq object structure.
461 * @param [in/out] attr
462 * Pointer to virtio queue counters attributes structure.
465 * 0 on success, a negative errno value otherwise and rte_errno is set.
468 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
469 struct mlx5_devx_virtio_q_couners_attr *attr);
471 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */