drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_byteorder.h>
  35 #include <rte_common.h>
  36 #include <rte_cycles.h>
  37 #include <rte_malloc.h>
  38 #include <rte_memzone.h>
  39 #include <rte_version.h>
  40
  41 #include "bnxt.h"
  42 #include "bnxt_cpr.h"
  43 #include "bnxt_filter.h"
  44 #include "bnxt_hwrm.h"
  45 #include "bnxt_rxq.h"
  46 #include "bnxt_ring.h"
  47 #include "bnxt_txq.h"
  48 #include "bnxt_vnic.h"
  49 #include "hsi_struct_def_dpdk.h"
  50
  51 #define HWRM_CMD_TIMEOUT                2000
  52
  53 /*
  54  * HWRM Functions (sent to HWRM)
  55  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  56  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  57  * command was failed by the ChiMP.
  58  */
  59
  60 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
  61                                         uint32_t msg_len)
  62 {
  63         unsigned int i;
  64         struct input *req = msg;
  65         struct output *resp = bp->hwrm_cmd_resp_addr;
  66         uint32_t *data = msg;
  67         uint8_t *bar;
  68         uint8_t *valid;
  69
  70         /* Write request msg to hwrm channel */
  71         for (i = 0; i < msg_len; i += 4) {
  72                 bar = (uint8_t *)bp->bar0 + i;
  73                 *(volatile uint32_t *)bar = *data;
  74                 data++;
  75         }
  76
  77         /* Zero the rest of the request space */
  78         for (; i < bp->max_req_len; i += 4) {
  79                 bar = (uint8_t *)bp->bar0 + i;
  80                 *(volatile uint32_t *)bar = 0;
  81         }
  82
  83         /* Ring channel doorbell */
  84         bar = (uint8_t *)bp->bar0 + 0x100;
  85         *(volatile uint32_t *)bar = 1;
  86
  87         /* Poll for the valid bit */
  88         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
  89                 /* Sanity check on the resp->resp_len */
  90                 rte_rmb();
  91                 if (resp->resp_len && resp->resp_len <=
  92                                 bp->max_resp_len) {
  93                         /* Last byte of resp contains the valid key */
  94                         valid = (uint8_t *)resp + resp->resp_len - 1;
  95                         if (*valid == HWRM_RESP_VALID_KEY)
  96                                 break;
  97                 }
  98                 rte_delay_us(600);
  99         }
 100
 101         if (i >= HWRM_CMD_TIMEOUT) {
 102                 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
 103                         req->req_type);
 104                 goto err_ret;
 105         }
 106         return 0;
 107
 108 err_ret:
 109         return -1;
 110 }
 111
 112 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 113 {
 114         int rc;
 115
 116         rte_spinlock_lock(&bp->hwrm_lock);
 117         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 118         rte_spinlock_unlock(&bp->hwrm_lock);
 119         return rc;
 120 }
 121
 122 #define HWRM_PREP(req, type, cr, resp) \
 123         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 124         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 125         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 126         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 127         req.target_id = rte_cpu_to_le_16(0xffff); \
 128         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 129
 130 #define HWRM_CHECK_RESULT \
 131         { \
 132                 if (rc) { \
 133                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 134                                 __func__, rc); \
 135                         return rc; \
 136                 } \
 137                 if (resp->error_code) { \
 138                         rc = rte_le_to_cpu_16(resp->error_code); \
 139                         RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
 140                         return rc; \
 141                 } \
 142         }
 143
 144 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 145                            struct bnxt_filter_info *filter)
 146 {
 147         int rc = 0;
 148         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 149         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 150
 151         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 152
 153         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 154
 155         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 156
 157         HWRM_CHECK_RESULT;
 158
 159         filter->fw_l2_filter_id = -1;
 160
 161         return 0;
 162 }
 163
 164 int bnxt_hwrm_set_filter(struct bnxt *bp,
 165                          struct bnxt_vnic_info *vnic,
 166                          struct bnxt_filter_info *filter)
 167 {
 168         int rc = 0;
 169         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 170         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 171         uint32_t enables = 0;
 172
 173         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 174
 175         req.flags = rte_cpu_to_le_32(filter->flags);
 176
 177         enables = filter->enables |
 178               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 179         req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 180
 181         if (enables &
 182             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 183                 memcpy(req.l2_addr, filter->l2_addr,
 184                        ETHER_ADDR_LEN);
 185         if (enables &
 186             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 187                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 188                        ETHER_ADDR_LEN);
 189         if (enables &
 190             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 191                 req.l2_ovlan = filter->l2_ovlan;
 192         if (enables &
 193             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 194                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 195
 196         req.enables = rte_cpu_to_le_32(enables);
 197
 198         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 199
 200         HWRM_CHECK_RESULT;
 201
 202         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 203
 204         return rc;
 205 }
 206
 207 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
 208 {
 209         int rc;
 210         struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
 211         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
 212
 213         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
 214
 215         memcpy(req.encap_request, fwd_cmd,
 216                sizeof(req.encap_request));
 217
 218         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 219
 220         HWRM_CHECK_RESULT;
 221
 222         return rc;
 223 }
 224
 225 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 226 {
 227         int rc = 0;
 228         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 229         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 230
 231         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 232
 233         req.fid = rte_cpu_to_le_16(0xffff);
 234
 235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 236
 237         HWRM_CHECK_RESULT;
 238
 239         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 240         if (BNXT_PF(bp)) {
 241                 struct bnxt_pf_info *pf = &bp->pf;
 242
 243                 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
 244                 pf->port_id = resp->port_id;
 245                 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
 246                 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 247                 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 248                 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 249                 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 250                 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 251                 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 252                 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 253                 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
 254         } else {
 255                 struct bnxt_vf_info *vf = &bp->vf;
 256
 257                 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
 258                 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
 259                 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 260                 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 261                 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 262                 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 263                 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 264                 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 265         }
 266
 267         return rc;
 268 }
 269
 270 int bnxt_hwrm_func_reset(struct bnxt *bp)
 271 {
 272         int rc = 0;
 273         struct hwrm_func_reset_input req = {.req_type = 0 };
 274         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 275
 276         HWRM_PREP(req, FUNC_RESET, -1, resp);
 277
 278         req.enables = rte_cpu_to_le_32(0);
 279
 280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 281
 282         HWRM_CHECK_RESULT;
 283
 284         return rc;
 285 }
 286
 287 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
 288                                    uint32_t *vf_req_fwd)
 289 {
 290         int rc;
 291         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 292         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 293
 294         if (bp->flags & BNXT_FLAG_REGISTERED)
 295                 return 0;
 296
 297         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 298         req.flags = flags;
 299         req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
 300         req.ver_maj = RTE_VER_YEAR;
 301         req.ver_min = RTE_VER_MONTH;
 302         req.ver_upd = RTE_VER_MINOR;
 303
 304         memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
 305
 306         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 307
 308         HWRM_CHECK_RESULT;
 309
 310         bp->flags |= BNXT_FLAG_REGISTERED;
 311
 312         return rc;
 313 }
 314
 315 int bnxt_hwrm_ver_get(struct bnxt *bp)
 316 {
 317         int rc = 0;
 318         struct hwrm_ver_get_input req = {.req_type = 0 };
 319         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 320         uint32_t my_version;
 321         uint32_t fw_version;
 322         uint16_t max_resp_len;
 323         char type[RTE_MEMZONE_NAMESIZE];
 324
 325         HWRM_PREP(req, VER_GET, -1, resp);
 326
 327         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 328         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 329         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 330
 331         /*
 332          * Hold the lock since we may be adjusting the response pointers.
 333          */
 334         rte_spinlock_lock(&bp->hwrm_lock);
 335         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 336
 337         HWRM_CHECK_RESULT;
 338
 339         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 340                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 341                 resp->hwrm_intf_upd,
 342                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 343
 344         my_version = HWRM_VERSION_MAJOR << 16;
 345         my_version |= HWRM_VERSION_MINOR << 8;
 346         my_version |= HWRM_VERSION_UPDATE;
 347
 348         fw_version = resp->hwrm_intf_maj << 16;
 349         fw_version |= resp->hwrm_intf_min << 8;
 350         fw_version |= resp->hwrm_intf_upd;
 351
 352         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 353                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 354                 rc = -EINVAL;
 355                 goto error;
 356         }
 357
 358         if (my_version != fw_version) {
 359                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 360                 if (my_version < fw_version) {
 361                         RTE_LOG(INFO, PMD,
 362                                 "Firmware API version is newer than driver.\n");
 363                         RTE_LOG(INFO, PMD,
 364                                 "The driver may be missing features.\n");
 365                 } else {
 366                         RTE_LOG(INFO, PMD,
 367                                 "Firmware API version is older than driver.\n");
 368                         RTE_LOG(INFO, PMD,
 369                                 "Not all driver features may be functional.\n");
 370                 }
 371         }
 372
 373         if (bp->max_req_len > resp->max_req_win_len) {
 374                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 375                 rc = -EINVAL;
 376         }
 377         bp->max_req_len = resp->max_req_win_len;
 378         max_resp_len = resp->max_resp_len;
 379         if (bp->max_resp_len != max_resp_len) {
 380                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 381                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 382                         bp->pdev->addr.devid, bp->pdev->addr.function);
 383
 384                 rte_free(bp->hwrm_cmd_resp_addr);
 385
 386                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 387                 if (bp->hwrm_cmd_resp_addr == NULL) {
 388                         rc = -ENOMEM;
 389                         goto error;
 390                 }
 391                 bp->hwrm_cmd_resp_dma_addr =
 392                         rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
 393                 bp->max_resp_len = max_resp_len;
 394         }
 395
 396 error:
 397         rte_spinlock_unlock(&bp->hwrm_lock);
 398         return rc;
 399 }
 400
 401 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 402 {
 403         int rc;
 404         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 405         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 406
 407         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 408                 return 0;
 409
 410         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 411         req.flags = flags;
 412
 413         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 414
 415         HWRM_CHECK_RESULT;
 416
 417         bp->flags &= ~BNXT_FLAG_REGISTERED;
 418
 419         return rc;
 420 }
 421
 422 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 423 {
 424         int rc = 0;
 425         struct hwrm_port_phy_cfg_input req = {.req_type = 0};
 426         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 427
 428         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 429
 430         req.flags = conf->phy_flags;
 431         if (conf->link_up) {
 432                 req.force_link_speed = conf->link_speed;
 433                 /*
 434                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 435                  * any auto mode, even "none".
 436                  */
 437                 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
 438                         req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
 439                 } else {
 440                         req.auto_mode = conf->auto_mode;
 441                         req.enables |=
 442                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 443                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
 444                         req.enables |=
 445                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 446                         req.auto_link_speed = conf->auto_link_speed;
 447                         req.enables |=
 448                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 449                 }
 450                 req.auto_duplex = conf->duplex;
 451                 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 452                 req.auto_pause = conf->auto_pause;
 453                 /* Set force_pause if there is no auto or if there is a force */
 454                 if (req.auto_pause)
 455                         req.enables |=
 456                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 457                 else
 458                         req.enables |=
 459                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 460                 req.force_pause = conf->force_pause;
 461                 if (req.force_pause)
 462                         req.enables |=
 463                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 464         } else {
 465                 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
 466                 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
 467                 req.force_link_speed = 0;
 468         }
 469
 470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 471
 472         HWRM_CHECK_RESULT;
 473
 474         return rc;
 475 }
 476
 477 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 478 {
 479         int rc = 0;
 480         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 481         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 482
 483         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 484
 485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 486
 487         HWRM_CHECK_RESULT;
 488
 489 #define GET_QUEUE_INFO(x) \
 490         bp->cos_queue[x].id = resp->queue_id##x; \
 491         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 492
 493         GET_QUEUE_INFO(0);
 494         GET_QUEUE_INFO(1);
 495         GET_QUEUE_INFO(2);
 496         GET_QUEUE_INFO(3);
 497         GET_QUEUE_INFO(4);
 498         GET_QUEUE_INFO(5);
 499         GET_QUEUE_INFO(6);
 500         GET_QUEUE_INFO(7);
 501
 502         return rc;
 503 }
 504
 505 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 506 {
 507         int rc = 0;
 508         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 509         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 510
 511         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 512
 513         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 514                 return rc;
 515
 516         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 517         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 518
 519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 520
 521         HWRM_CHECK_RESULT;
 522
 523         return rc;
 524 }
 525
 526 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 527 {
 528         int rc = 0, i, j;
 529         struct hwrm_vnic_alloc_input req = {.req_type = 0 };
 530         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 531
 532         /* map ring groups to this vnic */
 533         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
 534                 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
 535                         RTE_LOG(ERR, PMD,
 536                                 "Not enough ring groups avail:%x req:%x\n", j,
 537                                 (vnic->end_grp_id - vnic->start_grp_id) + 1);
 538                         break;
 539                 }
 540                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 541         }
 542
 543         vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
 544         vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
 545
 546         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 547
 548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 549
 550         HWRM_CHECK_RESULT;
 551
 552         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 553         return rc;
 554 }
 555
 556 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 557 {
 558         int rc = 0;
 559         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
 560         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 561
 562         HWRM_PREP(req, VNIC_CFG, -1, resp);
 563
 564         /* Only RSS support for now TBD: COS & LB */
 565         req.enables =
 566             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
 567                              HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
 568                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
 569         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 570         req.dflt_ring_grp =
 571                 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
 572         req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 573         req.cos_rule = rte_cpu_to_le_16(0xffff);
 574         req.lb_rule = rte_cpu_to_le_16(0xffff);
 575         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 576                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
 577         if (vnic->func_default)
 578                 req.flags = 1;
 579         if (vnic->vlan_strip)
 580                 req.flags |=
 581                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 584
 585         HWRM_CHECK_RESULT;
 586
 587         return rc;
 588 }
 589
 590 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 591 {
 592         int rc = 0;
 593         struct hwrm_vnic_free_input req = {.req_type = 0 };
 594         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
 595
 596         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 597                 return rc;
 598
 599         HWRM_PREP(req, VNIC_FREE, -1, resp);
 600
 601         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 602
 603         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 604
 605         HWRM_CHECK_RESULT;
 606
 607         vnic->fw_vnic_id = INVALID_HW_RING_ID;
 608         return rc;
 609 }
 610
 611 /*
 612  * HWRM utility functions
 613  */
 614
 615 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
 616 {
 617         unsigned int i;
 618         int rc = 0;
 619
 620         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 621                 struct bnxt_tx_queue *txq;
 622                 struct bnxt_rx_queue *rxq;
 623                 struct bnxt_cp_ring_info *cpr;
 624
 625                 if (i >= bp->rx_cp_nr_rings) {
 626                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
 627                         cpr = txq->cp_ring;
 628                 } else {
 629                         rxq = bp->rx_queues[i];
 630                         cpr = rxq->cp_ring;
 631                 }
 632
 633                 rc = bnxt_hwrm_stat_clear(bp, cpr);
 634                 if (rc)
 635                         return rc;
 636         }
 637         return 0;
 638 }
 639
 640 void bnxt_free_hwrm_resources(struct bnxt *bp)
 641 {
 642         /* Release memzone */
 643         rte_free(bp->hwrm_cmd_resp_addr);
 644         bp->hwrm_cmd_resp_addr = NULL;
 645         bp->hwrm_cmd_resp_dma_addr = 0;
 646 }
 647
 648 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
 649 {
 650         struct rte_pci_device *pdev = bp->pdev;
 651         char type[RTE_MEMZONE_NAMESIZE];
 652
 653         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
 654                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 655         bp->max_req_len = HWRM_MAX_REQ_LEN;
 656         bp->max_resp_len = HWRM_MAX_RESP_LEN;
 657         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
 658         if (bp->hwrm_cmd_resp_addr == NULL)
 659                 return -ENOMEM;
 660         bp->hwrm_cmd_resp_dma_addr =
 661                 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
 662         rte_spinlock_init(&bp->hwrm_lock);
 663
 664         return 0;
 665 }
 666
 667 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
 668 {
 669         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
 670
 671         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
 672                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
 673
 674         switch (conf_link_speed) {
 675         case ETH_LINK_SPEED_10M_HD:
 676         case ETH_LINK_SPEED_100M_HD:
 677                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
 678         }
 679         return hw_link_duplex;
 680 }
 681
 682 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
 683 {
 684         uint16_t eth_link_speed = 0;
 685
 686         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
 687                 return ETH_LINK_SPEED_AUTONEG;
 688
 689         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
 690         case ETH_LINK_SPEED_100M:
 691         case ETH_LINK_SPEED_100M_HD:
 692                 eth_link_speed =
 693                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
 694                 break;
 695         case ETH_LINK_SPEED_1G:
 696                 eth_link_speed =
 697                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
 698                 break;
 699         case ETH_LINK_SPEED_2_5G:
 700                 eth_link_speed =
 701                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
 702                 break;
 703         case ETH_LINK_SPEED_10G:
 704                 eth_link_speed =
 705                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
 706                 break;
 707         case ETH_LINK_SPEED_20G:
 708                 eth_link_speed =
 709                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
 710                 break;
 711         case ETH_LINK_SPEED_25G:
 712                 eth_link_speed =
 713                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
 714                 break;
 715         case ETH_LINK_SPEED_40G:
 716                 eth_link_speed =
 717                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
 718                 break;
 719         case ETH_LINK_SPEED_50G:
 720                 eth_link_speed =
 721                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
 722                 break;
 723         default:
 724                 RTE_LOG(ERR, PMD,
 725                         "Unsupported link speed %d; default to AUTO\n",
 726                         conf_link_speed);
 727                 break;
 728         }
 729         return eth_link_speed;
 730 }
 731
 732 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
 733                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
 734                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
 735                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
 736
 737 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
 738 {
 739         uint32_t one_speed;
 740
 741         if (link_speed == ETH_LINK_SPEED_AUTONEG)
 742                 return 0;
 743
 744         if (link_speed & ETH_LINK_SPEED_FIXED) {
 745                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
 746
 747                 if (one_speed & (one_speed - 1)) {
 748                         RTE_LOG(ERR, PMD,
 749                                 "Invalid advertised speeds (%u) for port %u\n",
 750                                 link_speed, port_id);
 751                         return -EINVAL;
 752                 }
 753                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
 754                         RTE_LOG(ERR, PMD,
 755                                 "Unsupported advertised speed (%u) for port %u\n",
 756                                 link_speed, port_id);
 757                         return -EINVAL;
 758                 }
 759         } else {
 760                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
 761                         RTE_LOG(ERR, PMD,
 762                                 "Unsupported advertised speeds (%u) for port %u\n",
 763                                 link_speed, port_id);
 764                         return -EINVAL;
 765                 }
 766         }
 767         return 0;
 768 }
 769
 770 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
 771 {
 772         uint16_t ret = 0;
 773
 774         if (link_speed == ETH_LINK_SPEED_AUTONEG)
 775                 link_speed = BNXT_SUPPORTED_SPEEDS;
 776
 777         if (link_speed & ETH_LINK_SPEED_100M)
 778                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
 779         if (link_speed & ETH_LINK_SPEED_100M_HD)
 780                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
 781         if (link_speed & ETH_LINK_SPEED_1G)
 782                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
 783         if (link_speed & ETH_LINK_SPEED_2_5G)
 784                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
 785         if (link_speed & ETH_LINK_SPEED_10G)
 786                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
 787         if (link_speed & ETH_LINK_SPEED_20G)
 788                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
 789         if (link_speed & ETH_LINK_SPEED_25G)
 790                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
 791         if (link_speed & ETH_LINK_SPEED_40G)
 792                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
 793         if (link_speed & ETH_LINK_SPEED_50G)
 794                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
 795         return ret;
 796 }
 797
 798 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
 799 {
 800         int rc = 0;
 801         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 802         struct bnxt_link_info link_req;
 803         uint16_t speed;
 804
 805         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
 806                         bp->eth_dev->data->port_id);
 807         if (rc)
 808                 goto error;
 809
 810         memset(&link_req, 0, sizeof(link_req));
 811         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
 812         link_req.link_up = link_up;
 813         if (speed == 0) {
 814                 link_req.phy_flags =
 815                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
 816                 link_req.auto_mode =
 817                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
 818                 link_req.auto_link_speed_mask =
 819                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
 820                 link_req.auto_link_speed =
 821                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
 822         } else {
 823                 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 824                 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
 825                         HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
 826                 link_req.link_speed = speed;
 827         }
 828         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
 829         link_req.auto_pause = bp->link_info.auto_pause;
 830         link_req.force_pause = bp->link_info.force_pause;
 831
 832         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
 833         if (rc) {
 834                 RTE_LOG(ERR, PMD,
 835                         "Set link config failed with rc %d\n", rc);
 836         }
 837
 838 error:
 839         return rc;
 840 }