drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34 #define DRIVER_TX_CONF "drv_tx_conf"
  35 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  36 #define CHECK_INTERVAL         100  /* 100ms */
  37 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  38
  39 /* Supported Rx offloads */
  40 static uint64_t dev_rx_offloads_sup =
  41                 RTE_ETH_RX_OFFLOAD_CHECKSUM |
  42                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
  43                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  44                 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
  45                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
  46                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
  47                 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  48
  49 /* Rx offloads which cannot be disabled */
  50 static uint64_t dev_rx_offloads_nodis =
  51                 RTE_ETH_RX_OFFLOAD_RSS_HASH |
  52                 RTE_ETH_RX_OFFLOAD_SCATTER;
  53
  54 /* Supported Tx offloads */
  55 static uint64_t dev_tx_offloads_sup =
  56                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
  57                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
  58                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
  59                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
  60                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
  61                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
  63                 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
  64
  65 /* Tx offloads which cannot be disabled */
  66 static uint64_t dev_tx_offloads_nodis =
  67                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
  68
  69 /* enable timestamp in mbuf */
  70 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  71 uint64_t dpaa2_timestamp_rx_dynflag;
  72 int dpaa2_timestamp_dynfield_offset = -1;
  73
  74 /* Enable error queue */
  75 bool dpaa2_enable_err_queue;
  76
  77 struct rte_dpaa2_xstats_name_off {
  78         char name[RTE_ETH_XSTATS_NAME_SIZE];
  79         uint8_t page_id; /* dpni statistics page id */
  80         uint8_t stats_id; /* stats id in the given page */
  81 };
  82
  83 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  84         {"ingress_multicast_frames", 0, 2},
  85         {"ingress_multicast_bytes", 0, 3},
  86         {"ingress_broadcast_frames", 0, 4},
  87         {"ingress_broadcast_bytes", 0, 5},
  88         {"egress_multicast_frames", 1, 2},
  89         {"egress_multicast_bytes", 1, 3},
  90         {"egress_broadcast_frames", 1, 4},
  91         {"egress_broadcast_bytes", 1, 5},
  92         {"ingress_filtered_frames", 2, 0},
  93         {"ingress_discarded_frames", 2, 1},
  94         {"ingress_nobuffer_discards", 2, 2},
  95         {"egress_discarded_frames", 2, 3},
  96         {"egress_confirmed_frames", 2, 4},
  97         {"cgr_reject_frames", 4, 0},
  98         {"cgr_reject_bytes", 4, 1},
  99 };
 100
 101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 102 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 103                                  int wait_to_complete);
 104 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 107
 108 static int
 109 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 110 {
 111         int ret;
 112         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 113         struct fsl_mc_io *dpni = dev->process_private;
 114
 115         PMD_INIT_FUNC_TRACE();
 116
 117         if (dpni == NULL) {
 118                 DPAA2_PMD_ERR("dpni is NULL");
 119                 return -1;
 120         }
 121
 122         if (on)
 123                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 124                                        vlan_id, 0, 0, 0);
 125         else
 126                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 127                                           priv->token, vlan_id);
 128
 129         if (ret < 0)
 130                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 131                               ret, vlan_id, priv->hw_id);
 132
 133         return ret;
 134 }
 135
 136 static int
 137 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 138 {
 139         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 140         struct fsl_mc_io *dpni = dev->process_private;
 141         int ret = 0;
 142
 143         PMD_INIT_FUNC_TRACE();
 144
 145         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
 146                 /* VLAN Filter not avaialble */
 147                 if (!priv->max_vlan_filters) {
 148                         DPAA2_PMD_INFO("VLAN filter not available");
 149                         return -ENOTSUP;
 150                 }
 151
 152                 if (dev->data->dev_conf.rxmode.offloads &
 153                         RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 154                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 155                                                       priv->token, true);
 156                 else
 157                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 158                                                       priv->token, false);
 159                 if (ret < 0)
 160                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 161         }
 162
 163         return ret;
 164 }
 165
 166 static int
 167 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 168                       enum rte_vlan_type vlan_type __rte_unused,
 169                       uint16_t tpid)
 170 {
 171         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 172         struct fsl_mc_io *dpni = dev->process_private;
 173         int ret = -ENOTSUP;
 174
 175         PMD_INIT_FUNC_TRACE();
 176
 177         /* nothing to be done for standard vlan tpids */
 178         if (tpid == 0x8100 || tpid == 0x88A8)
 179                 return 0;
 180
 181         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 182                                    priv->token, tpid);
 183         if (ret < 0)
 184                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 185         /* if already configured tpids, remove them first */
 186         if (ret == -EBUSY) {
 187                 struct dpni_custom_tpid_cfg tpid_list = {0};
 188
 189                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 190                                    priv->token, &tpid_list);
 191                 if (ret < 0)
 192                         goto fail;
 193                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 194                                    priv->token, tpid_list.tpid1);
 195                 if (ret < 0)
 196                         goto fail;
 197                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 198                                            priv->token, tpid);
 199         }
 200 fail:
 201         return ret;
 202 }
 203
 204 static int
 205 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 206                      char *fw_version,
 207                      size_t fw_size)
 208 {
 209         int ret;
 210         struct fsl_mc_io *dpni = dev->process_private;
 211         struct mc_soc_version mc_plat_info = {0};
 212         struct mc_version mc_ver_info = {0};
 213
 214         PMD_INIT_FUNC_TRACE();
 215
 216         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 217                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 218
 219         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 220                 DPAA2_PMD_WARN("\tmc_get_version failed");
 221
 222         ret = snprintf(fw_version, fw_size,
 223                        "%x-%d.%d.%d",
 224                        mc_plat_info.svr,
 225                        mc_ver_info.major,
 226                        mc_ver_info.minor,
 227                        mc_ver_info.revision);
 228         if (ret < 0)
 229                 return -EINVAL;
 230
 231         ret += 1; /* add the size of '\0' */
 232         if (fw_size < (size_t)ret)
 233                 return ret;
 234         else
 235                 return 0;
 236 }
 237
 238 static int
 239 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 240 {
 241         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 242
 243         PMD_INIT_FUNC_TRACE();
 244
 245         dev_info->max_mac_addrs = priv->max_mac_filters;
 246         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 247         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 248         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 249         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 250         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 251                                         dev_rx_offloads_nodis;
 252         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 253                                         dev_tx_offloads_nodis;
 254         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
 255                         RTE_ETH_LINK_SPEED_2_5G |
 256                         RTE_ETH_LINK_SPEED_10G;
 257
 258         dev_info->max_hash_mac_addrs = 0;
 259         dev_info->max_vfs = 0;
 260         dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
 261         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 262
 263         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 264         /* same is rx size for best perf */
 265         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 266
 267         dev_info->default_rxportconf.nb_queues = 1;
 268         dev_info->default_txportconf.nb_queues = 1;
 269         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 270         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 271
 272         if (dpaa2_svr_family == SVR_LX2160A) {
 273                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
 274                                 RTE_ETH_LINK_SPEED_40G |
 275                                 RTE_ETH_LINK_SPEED_50G |
 276                                 RTE_ETH_LINK_SPEED_100G;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static int
 283 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 284                         __rte_unused uint16_t queue_id,
 285                         struct rte_eth_burst_mode *mode)
 286 {
 287         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 288         int ret = -EINVAL;
 289         unsigned int i;
 290         const struct burst_info {
 291                 uint64_t flags;
 292                 const char *output;
 293         } rx_offload_map[] = {
 294                         {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 295                         {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 296                         {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 297                         {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 298                         {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 299                         {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 300                         {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 301                         {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
 302                         {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
 303         };
 304
 305         /* Update Rx offload info */
 306         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 307                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 308                         snprintf(mode->info, sizeof(mode->info), "%s",
 309                                 rx_offload_map[i].output);
 310                         ret = 0;
 311                         break;
 312                 }
 313         }
 314         return ret;
 315 }
 316
 317 static int
 318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 319                         __rte_unused uint16_t queue_id,
 320                         struct rte_eth_burst_mode *mode)
 321 {
 322         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 323         int ret = -EINVAL;
 324         unsigned int i;
 325         const struct burst_info {
 326                 uint64_t flags;
 327                 const char *output;
 328         } tx_offload_map[] = {
 329                         {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 330                         {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 331                         {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 332                         {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 333                         {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 334                         {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 335                         {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 336                         {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 337                         {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 338         };
 339
 340         /* Update Tx offload info */
 341         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 342                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 343                         snprintf(mode->info, sizeof(mode->info), "%s",
 344                                 tx_offload_map[i].output);
 345                         ret = 0;
 346                         break;
 347                 }
 348         }
 349         return ret;
 350 }
 351
 352 static int
 353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 354 {
 355         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 356         uint16_t dist_idx;
 357         uint32_t vq_id;
 358         uint8_t num_rxqueue_per_tc;
 359         struct dpaa2_queue *mc_q, *mcq;
 360         uint32_t tot_queues;
 361         int i;
 362         struct dpaa2_queue *dpaa2_q;
 363
 364         PMD_INIT_FUNC_TRACE();
 365
 366         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 367         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 368                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 369         else
 370                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 371         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 372                           RTE_CACHE_LINE_SIZE);
 373         if (!mc_q) {
 374                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 375                 return -1;
 376         }
 377
 378         for (i = 0; i < priv->nb_rx_queues; i++) {
 379                 mc_q->eth_data = dev->data;
 380                 priv->rx_vq[i] = mc_q++;
 381                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 382                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 383                                         sizeof(struct queue_storage_info_t),
 384                                         RTE_CACHE_LINE_SIZE);
 385                 if (!dpaa2_q->q_storage)
 386                         goto fail;
 387
 388                 memset(dpaa2_q->q_storage, 0,
 389                        sizeof(struct queue_storage_info_t));
 390                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 391                         goto fail;
 392         }
 393
 394         if (dpaa2_enable_err_queue) {
 395                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 396                         sizeof(struct dpaa2_queue), 0);
 397
 398                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 399                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 400                                         sizeof(struct queue_storage_info_t) *
 401                                         RTE_MAX_LCORE,
 402                                         RTE_CACHE_LINE_SIZE);
 403                 if (!dpaa2_q->q_storage)
 404                         goto fail;
 405
 406                 memset(dpaa2_q->q_storage, 0,
 407                        sizeof(struct queue_storage_info_t));
 408                 for (i = 0; i < RTE_MAX_LCORE; i++)
 409                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 410                                 goto fail;
 411         }
 412
 413         for (i = 0; i < priv->nb_tx_queues; i++) {
 414                 mc_q->eth_data = dev->data;
 415                 mc_q->flow_id = 0xffff;
 416                 priv->tx_vq[i] = mc_q++;
 417                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 418                 dpaa2_q->cscn = rte_malloc(NULL,
 419                                            sizeof(struct qbman_result), 16);
 420                 if (!dpaa2_q->cscn)
 421                         goto fail_tx;
 422         }
 423
 424         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 425                 /*Setup tx confirmation queues*/
 426                 for (i = 0; i < priv->nb_tx_queues; i++) {
 427                         mc_q->eth_data = dev->data;
 428                         mc_q->tc_index = i;
 429                         mc_q->flow_id = 0;
 430                         priv->tx_conf_vq[i] = mc_q++;
 431                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 432                         dpaa2_q->q_storage =
 433                                 rte_malloc("dq_storage",
 434                                         sizeof(struct queue_storage_info_t),
 435                                         RTE_CACHE_LINE_SIZE);
 436                         if (!dpaa2_q->q_storage)
 437                                 goto fail_tx_conf;
 438
 439                         memset(dpaa2_q->q_storage, 0,
 440                                sizeof(struct queue_storage_info_t));
 441                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 442                                 goto fail_tx_conf;
 443                 }
 444         }
 445
 446         vq_id = 0;
 447         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 448                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 449                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 450                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 451                 vq_id++;
 452         }
 453
 454         return 0;
 455 fail_tx_conf:
 456         i -= 1;
 457         while (i >= 0) {
 458                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 459                 rte_free(dpaa2_q->q_storage);
 460                 priv->tx_conf_vq[i--] = NULL;
 461         }
 462         i = priv->nb_tx_queues;
 463 fail_tx:
 464         i -= 1;
 465         while (i >= 0) {
 466                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 467                 rte_free(dpaa2_q->cscn);
 468                 priv->tx_vq[i--] = NULL;
 469         }
 470         i = priv->nb_rx_queues;
 471 fail:
 472         i -= 1;
 473         mc_q = priv->rx_vq[0];
 474         while (i >= 0) {
 475                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 476                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 477                 rte_free(dpaa2_q->q_storage);
 478                 priv->rx_vq[i--] = NULL;
 479         }
 480
 481         if (dpaa2_enable_err_queue) {
 482                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 483                 if (dpaa2_q->q_storage)
 484                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 485                 rte_free(dpaa2_q->q_storage);
 486         }
 487
 488         rte_free(mc_q);
 489         return -1;
 490 }
 491
 492 static void
 493 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 494 {
 495         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 496         struct dpaa2_queue *dpaa2_q;
 497         int i;
 498
 499         PMD_INIT_FUNC_TRACE();
 500
 501         /* Queue allocation base */
 502         if (priv->rx_vq[0]) {
 503                 /* cleaning up queue storage */
 504                 for (i = 0; i < priv->nb_rx_queues; i++) {
 505                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 506                         if (dpaa2_q->q_storage)
 507                                 rte_free(dpaa2_q->q_storage);
 508                 }
 509                 /* cleanup tx queue cscn */
 510                 for (i = 0; i < priv->nb_tx_queues; i++) {
 511                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 512                         rte_free(dpaa2_q->cscn);
 513                 }
 514                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 515                         /* cleanup tx conf queue storage */
 516                         for (i = 0; i < priv->nb_tx_queues; i++) {
 517                                 dpaa2_q = (struct dpaa2_queue *)
 518                                                 priv->tx_conf_vq[i];
 519                                 rte_free(dpaa2_q->q_storage);
 520                         }
 521                 }
 522                 /*free memory for all queues (RX+TX) */
 523                 rte_free(priv->rx_vq[0]);
 524                 priv->rx_vq[0] = NULL;
 525         }
 526 }
 527
 528 static int
 529 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 530 {
 531         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 532         struct fsl_mc_io *dpni = dev->process_private;
 533         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 534         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 535         uint64_t tx_offloads = eth_conf->txmode.offloads;
 536         int rx_l3_csum_offload = false;
 537         int rx_l4_csum_offload = false;
 538         int tx_l3_csum_offload = false;
 539         int tx_l4_csum_offload = false;
 540         int ret, tc_index;
 541         uint32_t max_rx_pktlen;
 542
 543         PMD_INIT_FUNC_TRACE();
 544
 545         /* Rx offloads which are enabled by default */
 546         if (dev_rx_offloads_nodis & ~rx_offloads) {
 547                 DPAA2_PMD_INFO(
 548                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 549                 " fixed are 0x%" PRIx64,
 550                 rx_offloads, dev_rx_offloads_nodis);
 551         }
 552
 553         /* Tx offloads which are enabled by default */
 554         if (dev_tx_offloads_nodis & ~tx_offloads) {
 555                 DPAA2_PMD_INFO(
 556                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 557                 " fixed are 0x%" PRIx64,
 558                 tx_offloads, dev_tx_offloads_nodis);
 559         }
 560
 561         max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
 562                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
 563         if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
 564                 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 565                         priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
 566                 if (ret != 0) {
 567                         DPAA2_PMD_ERR("Unable to set mtu. check config");
 568                         return ret;
 569                 }
 570                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 571                                 dev->data->mtu);
 572         } else {
 573                 return -1;
 574         }
 575
 576         if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
 577                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 578                         ret = dpaa2_setup_flow_dist(dev,
 579                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 580                                         tc_index);
 581                         if (ret) {
 582                                 DPAA2_PMD_ERR(
 583                                         "Unable to set flow distribution on tc%d."
 584                                         "Check queue config", tc_index);
 585                                 return ret;
 586                         }
 587                 }
 588         }
 589
 590         if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
 591                 rx_l3_csum_offload = true;
 592
 593         if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
 594                 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
 595                 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
 596                 rx_l4_csum_offload = true;
 597
 598         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 599                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 600         if (ret) {
 601                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 602                 return ret;
 603         }
 604
 605         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 606                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 607         if (ret) {
 608                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 609                 return ret;
 610         }
 611
 612 #if !defined(RTE_LIBRTE_IEEE1588)
 613         if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 614 #endif
 615         {
 616                 ret = rte_mbuf_dyn_rx_timestamp_register(
 617                                 &dpaa2_timestamp_dynfield_offset,
 618                                 &dpaa2_timestamp_rx_dynflag);
 619                 if (ret != 0) {
 620                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 621                         return -rte_errno;
 622                 }
 623                 dpaa2_enable_ts[dev->data->port_id] = true;
 624         }
 625
 626         if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
 627                 tx_l3_csum_offload = true;
 628
 629         if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
 630                 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
 631                 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
 632                 tx_l4_csum_offload = true;
 633
 634         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 635                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 636         if (ret) {
 637                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 638                 return ret;
 639         }
 640
 641         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 642                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 643         if (ret) {
 644                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 645                 return ret;
 646         }
 647
 648         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 649          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 650          * to 0 for LS2 in the hardware thus disabling data/annotation
 651          * stashing. For LX2 this is fixed in hardware and thus hash result and
 652          * parse results can be received in FD using this option.
 653          */
 654         if (dpaa2_svr_family == SVR_LX2160A) {
 655                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 656                                        DPNI_FLCTYPE_HASH, true);
 657                 if (ret) {
 658                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 659                         return ret;
 660                 }
 661         }
 662
 663         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 664                 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
 665
 666         dpaa2_tm_init(dev);
 667
 668         return 0;
 669 }
 670
 671 /* Function to setup RX flow information. It contains traffic class ID,
 672  * flow ID, destination configuration etc.
 673  */
 674 static int
 675 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 676                          uint16_t rx_queue_id,
 677                          uint16_t nb_rx_desc,
 678                          unsigned int socket_id __rte_unused,
 679                          const struct rte_eth_rxconf *rx_conf,
 680                          struct rte_mempool *mb_pool)
 681 {
 682         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 683         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 684         struct dpaa2_queue *dpaa2_q;
 685         struct dpni_queue cfg;
 686         uint8_t options = 0;
 687         uint8_t flow_id;
 688         uint32_t bpid;
 689         int i, ret;
 690
 691         PMD_INIT_FUNC_TRACE();
 692
 693         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 694                         dev, rx_queue_id, mb_pool, rx_conf);
 695
 696         /* Rx deferred start is not supported */
 697         if (rx_conf->rx_deferred_start) {
 698                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 699                                 (void *)dev);
 700                 return -EINVAL;
 701         }
 702
 703         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 704                 bpid = mempool_to_bpid(mb_pool);
 705                 ret = dpaa2_attach_bp_list(priv,
 706                                            rte_dpaa2_bpid_info[bpid].bp_list);
 707                 if (ret)
 708                         return ret;
 709         }
 710         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 711         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 712         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 713         dpaa2_q->nb_desc = UINT16_MAX;
 714         dpaa2_q->offloads = rx_conf->offloads;
 715
 716         /*Get the flow id from given VQ id*/
 717         flow_id = dpaa2_q->flow_id;
 718         memset(&cfg, 0, sizeof(struct dpni_queue));
 719
 720         options = options | DPNI_QUEUE_OPT_USER_CTX;
 721         cfg.user_context = (size_t)(dpaa2_q);
 722
 723         /* check if a private cgr available. */
 724         for (i = 0; i < priv->max_cgs; i++) {
 725                 if (!priv->cgid_in_use[i]) {
 726                         priv->cgid_in_use[i] = 1;
 727                         break;
 728                 }
 729         }
 730
 731         if (i < priv->max_cgs) {
 732                 options |= DPNI_QUEUE_OPT_SET_CGID;
 733                 cfg.cgid = i;
 734                 dpaa2_q->cgid = cfg.cgid;
 735         } else {
 736                 dpaa2_q->cgid = 0xff;
 737         }
 738
 739         /*if ls2088 or rev2 device, enable the stashing */
 740
 741         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 742                 options |= DPNI_QUEUE_OPT_FLC;
 743                 cfg.flc.stash_control = true;
 744                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 745                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 746                  * data stashing setting 01 01 00 (0x14)
 747                  * (in following order ->DS AS CS)
 748                  * to enable 1 line data, 1 line annotation.
 749                  * For LX2, this setting should be 01 00 00 (0x10)
 750                  */
 751                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 752                         cfg.flc.value |= 0x10;
 753                 else
 754                         cfg.flc.value |= 0x14;
 755         }
 756         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 757                              dpaa2_q->tc_index, flow_id, options, &cfg);
 758         if (ret) {
 759                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 760                 return -1;
 761         }
 762
 763         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 764                 struct dpni_taildrop taildrop;
 765
 766                 taildrop.enable = 1;
 767                 dpaa2_q->nb_desc = nb_rx_desc;
 768                 /* Private CGR will use tail drop length as nb_rx_desc.
 769                  * for rest cases we can use standard byte based tail drop.
 770                  * There is no HW restriction, but number of CGRs are limited,
 771                  * hence this restriction is placed.
 772                  */
 773                 if (dpaa2_q->cgid != 0xff) {
 774                         /*enabling per rx queue congestion control */
 775                         taildrop.threshold = nb_rx_desc;
 776                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 777                         taildrop.oal = 0;
 778                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 779                                         rx_queue_id);
 780                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 781                                                 DPNI_CP_CONGESTION_GROUP,
 782                                                 DPNI_QUEUE_RX,
 783                                                 dpaa2_q->tc_index,
 784                                                 dpaa2_q->cgid, &taildrop);
 785                 } else {
 786                         /*enabling per rx queue congestion control */
 787                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 788                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 789                         taildrop.oal = CONG_RX_OAL;
 790                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 791                                         rx_queue_id);
 792                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 793                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 794                                                 dpaa2_q->tc_index, flow_id,
 795                                                 &taildrop);
 796                 }
 797                 if (ret) {
 798                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 799                                       ret);
 800                         return -1;
 801                 }
 802         } else { /* Disable tail Drop */
 803                 struct dpni_taildrop taildrop = {0};
 804                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 805
 806                 taildrop.enable = 0;
 807                 if (dpaa2_q->cgid != 0xff) {
 808                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 809                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 810                                         dpaa2_q->tc_index,
 811                                         dpaa2_q->cgid, &taildrop);
 812                 } else {
 813                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 814                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 815                                         dpaa2_q->tc_index, flow_id, &taildrop);
 816                 }
 817                 if (ret) {
 818                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 819                                       ret);
 820                         return -1;
 821                 }
 822         }
 823
 824         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 825         return 0;
 826 }
 827
 828 static int
 829 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 830                          uint16_t tx_queue_id,
 831                          uint16_t nb_tx_desc,
 832                          unsigned int socket_id __rte_unused,
 833                          const struct rte_eth_txconf *tx_conf)
 834 {
 835         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 836         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 837                 priv->tx_vq[tx_queue_id];
 838         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 839                 priv->tx_conf_vq[tx_queue_id];
 840         struct fsl_mc_io *dpni = dev->process_private;
 841         struct dpni_queue tx_conf_cfg;
 842         struct dpni_queue tx_flow_cfg;
 843         uint8_t options = 0, flow_id;
 844         struct dpni_queue_id qid;
 845         uint32_t tc_id;
 846         int ret;
 847
 848         PMD_INIT_FUNC_TRACE();
 849
 850         /* Tx deferred start is not supported */
 851         if (tx_conf->tx_deferred_start) {
 852                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 853                                 (void *)dev);
 854                 return -EINVAL;
 855         }
 856
 857         dpaa2_q->nb_desc = UINT16_MAX;
 858         dpaa2_q->offloads = tx_conf->offloads;
 859
 860         /* Return if queue already configured */
 861         if (dpaa2_q->flow_id != 0xffff) {
 862                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 863                 return 0;
 864         }
 865
 866         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 867         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 868
 869         tc_id = tx_queue_id;
 870         flow_id = 0;
 871
 872         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 873                         tc_id, flow_id, options, &tx_flow_cfg);
 874         if (ret) {
 875                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 876                         "tc_id=%d, flow=%d err=%d",
 877                         tc_id, flow_id, ret);
 878                         return -1;
 879         }
 880
 881         dpaa2_q->flow_id = flow_id;
 882
 883         if (tx_queue_id == 0) {
 884                 /*Set tx-conf and error configuration*/
 885                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 886                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 887                                                             priv->token,
 888                                                             DPNI_CONF_AFFINE);
 889                 else
 890                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 891                                                             priv->token,
 892                                                             DPNI_CONF_DISABLE);
 893                 if (ret) {
 894                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 895                                       "err=%d", ret);
 896                         return -1;
 897                 }
 898         }
 899         dpaa2_q->tc_index = tc_id;
 900
 901         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 902                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 903                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 904         if (ret) {
 905                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 906                 return -1;
 907         }
 908         dpaa2_q->fqid = qid.fqid;
 909
 910         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 911                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 912
 913                 dpaa2_q->nb_desc = nb_tx_desc;
 914
 915                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 916                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 917                 /* Notify that the queue is not congested when the data in
 918                  * the queue is below this thershold.(90% of value)
 919                  */
 920                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 921                 cong_notif_cfg.message_ctx = 0;
 922                 cong_notif_cfg.message_iova =
 923                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 924                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 925                 cong_notif_cfg.notification_mode =
 926                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 927                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 928                                          DPNI_CONG_OPT_COHERENT_WRITE;
 929                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 930
 931                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 932                                                        priv->token,
 933                                                        DPNI_QUEUE_TX,
 934                                                        tc_id,
 935                                                        &cong_notif_cfg);
 936                 if (ret) {
 937                         DPAA2_PMD_ERR(
 938                            "Error in setting tx congestion notification: "
 939                            "err=%d", ret);
 940                         return -ret;
 941                 }
 942         }
 943         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 944         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 945
 946         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 947                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 948                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 949                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 950                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 951                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 952                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 953                 if (ret) {
 954                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 955                               "tc_index=%d, flow=%d err=%d",
 956                               dpaa2_tx_conf_q->tc_index,
 957                               dpaa2_tx_conf_q->flow_id, ret);
 958                         return -1;
 959                 }
 960
 961                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 962                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 963                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 964                 if (ret) {
 965                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 966                         return -1;
 967                 }
 968                 dpaa2_tx_conf_q->fqid = qid.fqid;
 969         }
 970         return 0;
 971 }
 972
 973 static void
 974 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 975 {
 976         struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
 977         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 978         struct fsl_mc_io *dpni =
 979                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 980         uint8_t options = 0;
 981         int ret;
 982         struct dpni_queue cfg;
 983
 984         memset(&cfg, 0, sizeof(struct dpni_queue));
 985         PMD_INIT_FUNC_TRACE();
 986         if (dpaa2_q->cgid != 0xff) {
 987                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 988                 cfg.cgid = dpaa2_q->cgid;
 989
 990                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 991                                      DPNI_QUEUE_RX,
 992                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
 993                                      options, &cfg);
 994                 if (ret)
 995                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
 996                                         dpaa2_q->fqid, ret);
 997                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
 998                 dpaa2_q->cgid = 0xff;
 999         }
1000 }
1001
1002 static uint32_t
1003 dpaa2_dev_rx_queue_count(void *rx_queue)
1004 {
1005         int32_t ret;
1006         struct dpaa2_queue *dpaa2_q;
1007         struct qbman_swp *swp;
1008         struct qbman_fq_query_np_rslt state;
1009         uint32_t frame_cnt = 0;
1010
1011         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1012                 ret = dpaa2_affine_qbman_swp();
1013                 if (ret) {
1014                         DPAA2_PMD_ERR(
1015                                 "Failed to allocate IO portal, tid: %d\n",
1016                                 rte_gettid());
1017                         return -EINVAL;
1018                 }
1019         }
1020         swp = DPAA2_PER_LCORE_PORTAL;
1021
1022         dpaa2_q = rx_queue;
1023
1024         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1025                 frame_cnt = qbman_fq_state_frame_count(&state);
1026                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1027                                 rx_queue, frame_cnt);
1028         }
1029         return frame_cnt;
1030 }
1031
1032 static const uint32_t *
1033 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1034 {
1035         static const uint32_t ptypes[] = {
1036                 /*todo -= add more types */
1037                 RTE_PTYPE_L2_ETHER,
1038                 RTE_PTYPE_L3_IPV4,
1039                 RTE_PTYPE_L3_IPV4_EXT,
1040                 RTE_PTYPE_L3_IPV6,
1041                 RTE_PTYPE_L3_IPV6_EXT,
1042                 RTE_PTYPE_L4_TCP,
1043                 RTE_PTYPE_L4_UDP,
1044                 RTE_PTYPE_L4_SCTP,
1045                 RTE_PTYPE_L4_ICMP,
1046                 RTE_PTYPE_UNKNOWN
1047         };
1048
1049         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1050                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1051                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1052                 return ptypes;
1053         return NULL;
1054 }
1055
1056 /**
1057  * Dpaa2 link Interrupt handler
1058  *
1059  * @param param
1060  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1061  *
1062  * @return
1063  *  void
1064  */
1065 static void
1066 dpaa2_interrupt_handler(void *param)
1067 {
1068         struct rte_eth_dev *dev = param;
1069         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1070         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1071         int ret;
1072         int irq_index = DPNI_IRQ_INDEX;
1073         unsigned int status = 0, clear = 0;
1074
1075         PMD_INIT_FUNC_TRACE();
1076
1077         if (dpni == NULL) {
1078                 DPAA2_PMD_ERR("dpni is NULL");
1079                 return;
1080         }
1081
1082         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1083                                   irq_index, &status);
1084         if (unlikely(ret)) {
1085                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1086                 clear = 0xffffffff;
1087                 goto out;
1088         }
1089
1090         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1091                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1092                 dpaa2_dev_link_update(dev, 0);
1093                 /* calling all the apps registered for link status event */
1094                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1095         }
1096 out:
1097         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1098                                     irq_index, clear);
1099         if (unlikely(ret))
1100                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1101 }
1102
1103 static int
1104 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1105 {
1106         int err = 0;
1107         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1108         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1109         int irq_index = DPNI_IRQ_INDEX;
1110         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1111
1112         PMD_INIT_FUNC_TRACE();
1113
1114         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1115                                 irq_index, mask);
1116         if (err < 0) {
1117                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1118                               strerror(-err));
1119                 return err;
1120         }
1121
1122         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1123                                   irq_index, enable);
1124         if (err < 0)
1125                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1126                               strerror(-err));
1127
1128         return err;
1129 }
1130
1131 static int
1132 dpaa2_dev_start(struct rte_eth_dev *dev)
1133 {
1134         struct rte_device *rdev = dev->device;
1135         struct rte_dpaa2_device *dpaa2_dev;
1136         struct rte_eth_dev_data *data = dev->data;
1137         struct dpaa2_dev_priv *priv = data->dev_private;
1138         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1139         struct dpni_queue cfg;
1140         struct dpni_error_cfg   err_cfg;
1141         uint16_t qdid;
1142         struct dpni_queue_id qid;
1143         struct dpaa2_queue *dpaa2_q;
1144         int ret, i;
1145         struct rte_intr_handle *intr_handle;
1146
1147         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1148         intr_handle = dpaa2_dev->intr_handle;
1149
1150         PMD_INIT_FUNC_TRACE();
1151
1152         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1153         if (ret) {
1154                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1155                               priv->hw_id, ret);
1156                 return ret;
1157         }
1158
1159         /* Power up the phy. Needed to make the link go UP */
1160         dpaa2_dev_set_link_up(dev);
1161
1162         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1163                             DPNI_QUEUE_TX, &qdid);
1164         if (ret) {
1165                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1166                 return ret;
1167         }
1168         priv->qdid = qdid;
1169
1170         for (i = 0; i < data->nb_rx_queues; i++) {
1171                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1172                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1173                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1174                                        dpaa2_q->flow_id, &cfg, &qid);
1175                 if (ret) {
1176                         DPAA2_PMD_ERR("Error in getting flow information: "
1177                                       "err=%d", ret);
1178                         return ret;
1179                 }
1180                 dpaa2_q->fqid = qid.fqid;
1181         }
1182
1183         if (dpaa2_enable_err_queue) {
1184                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1185                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1186                 if (ret) {
1187                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1188                                                 ret);
1189                         return ret;
1190                 }
1191                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1192                 dpaa2_q->fqid = qid.fqid;
1193                 dpaa2_q->eth_data = dev->data;
1194
1195                 err_cfg.errors =  DPNI_ERROR_DISC;
1196                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1197         } else {
1198                 /* checksum errors, send them to normal path
1199                  * and set it in annotation
1200                  */
1201                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1202
1203                 /* if packet with parse error are not to be dropped */
1204                 err_cfg.errors |= DPNI_ERROR_PHE;
1205
1206                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1207         }
1208         err_cfg.set_frame_annotation = true;
1209
1210         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1211                                        priv->token, &err_cfg);
1212         if (ret) {
1213                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1214                               ret);
1215                 return ret;
1216         }
1217
1218         /* if the interrupts were configured on this devices*/
1219         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1220             dev->data->dev_conf.intr_conf.lsc != 0) {
1221                 /* Registering LSC interrupt handler */
1222                 rte_intr_callback_register(intr_handle,
1223                                            dpaa2_interrupt_handler,
1224                                            (void *)dev);
1225
1226                 /* enable vfio intr/eventfd mapping
1227                  * Interrupt index 0 is required, so we can not use
1228                  * rte_intr_enable.
1229                  */
1230                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1231
1232                 /* enable dpni_irqs */
1233                 dpaa2_eth_setup_irqs(dev, 1);
1234         }
1235
1236         /* Change the tx burst function if ordered queues are used */
1237         if (priv->en_ordered)
1238                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1239
1240         return 0;
1241 }
1242
1243 /**
1244  *  This routine disables all traffic on the adapter by issuing a
1245  *  global reset on the MAC.
1246  */
1247 static int
1248 dpaa2_dev_stop(struct rte_eth_dev *dev)
1249 {
1250         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1251         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1252         int ret;
1253         struct rte_eth_link link;
1254         struct rte_intr_handle *intr_handle = dev->intr_handle;
1255
1256         PMD_INIT_FUNC_TRACE();
1257
1258         /* reset interrupt callback  */
1259         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1260             dev->data->dev_conf.intr_conf.lsc != 0) {
1261                 /*disable dpni irqs */
1262                 dpaa2_eth_setup_irqs(dev, 0);
1263
1264                 /* disable vfio intr before callback unregister */
1265                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1266
1267                 /* Unregistering LSC interrupt handler */
1268                 rte_intr_callback_unregister(intr_handle,
1269                                              dpaa2_interrupt_handler,
1270                                              (void *)dev);
1271         }
1272
1273         dpaa2_dev_set_link_down(dev);
1274
1275         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1276         if (ret) {
1277                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1278                               ret, priv->hw_id);
1279                 return ret;
1280         }
1281
1282         /* clear the recorded link status */
1283         memset(&link, 0, sizeof(link));
1284         rte_eth_linkstatus_set(dev, &link);
1285
1286         return 0;
1287 }
1288
1289 static int
1290 dpaa2_dev_close(struct rte_eth_dev *dev)
1291 {
1292         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1293         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1294         int i, ret;
1295         struct rte_eth_link link;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return 0;
1301
1302         if (!dpni) {
1303                 DPAA2_PMD_WARN("Already closed or not started");
1304                 return -1;
1305         }
1306
1307         dpaa2_tm_deinit(dev);
1308         dpaa2_flow_clean(dev);
1309         /* Clean the device first */
1310         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1311         if (ret) {
1312                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1313                 return -1;
1314         }
1315
1316         memset(&link, 0, sizeof(link));
1317         rte_eth_linkstatus_set(dev, &link);
1318
1319         /* Free private queues memory */
1320         dpaa2_free_rx_tx_queues(dev);
1321         /* Close the device at underlying layer*/
1322         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1323         if (ret) {
1324                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1325                               ret);
1326         }
1327
1328         /* Free the allocated memory for ethernet private data and dpni*/
1329         priv->hw = NULL;
1330         dev->process_private = NULL;
1331         rte_free(dpni);
1332
1333         for (i = 0; i < MAX_TCS; i++)
1334                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1335
1336         if (priv->extract.qos_extract_param)
1337                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1338
1339         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1340         return 0;
1341 }
1342
1343 static int
1344 dpaa2_dev_promiscuous_enable(
1345                 struct rte_eth_dev *dev)
1346 {
1347         int ret;
1348         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1349         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1350
1351         PMD_INIT_FUNC_TRACE();
1352
1353         if (dpni == NULL) {
1354                 DPAA2_PMD_ERR("dpni is NULL");
1355                 return -ENODEV;
1356         }
1357
1358         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1359         if (ret < 0)
1360                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1361
1362         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1363         if (ret < 0)
1364                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1365
1366         return ret;
1367 }
1368
1369 static int
1370 dpaa2_dev_promiscuous_disable(
1371                 struct rte_eth_dev *dev)
1372 {
1373         int ret;
1374         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1375         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1376
1377         PMD_INIT_FUNC_TRACE();
1378
1379         if (dpni == NULL) {
1380                 DPAA2_PMD_ERR("dpni is NULL");
1381                 return -ENODEV;
1382         }
1383
1384         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1385         if (ret < 0)
1386                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1387
1388         if (dev->data->all_multicast == 0) {
1389                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1390                                                  priv->token, false);
1391                 if (ret < 0)
1392                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1393                                       ret);
1394         }
1395
1396         return ret;
1397 }
1398
1399 static int
1400 dpaa2_dev_allmulticast_enable(
1401                 struct rte_eth_dev *dev)
1402 {
1403         int ret;
1404         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1405         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1406
1407         PMD_INIT_FUNC_TRACE();
1408
1409         if (dpni == NULL) {
1410                 DPAA2_PMD_ERR("dpni is NULL");
1411                 return -ENODEV;
1412         }
1413
1414         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1415         if (ret < 0)
1416                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1417
1418         return ret;
1419 }
1420
1421 static int
1422 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1423 {
1424         int ret;
1425         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1426         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1427
1428         PMD_INIT_FUNC_TRACE();
1429
1430         if (dpni == NULL) {
1431                 DPAA2_PMD_ERR("dpni is NULL");
1432                 return -ENODEV;
1433         }
1434
1435         /* must remain on for all promiscuous */
1436         if (dev->data->promiscuous == 1)
1437                 return 0;
1438
1439         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1440         if (ret < 0)
1441                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1442
1443         return ret;
1444 }
1445
1446 static int
1447 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1448 {
1449         int ret;
1450         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1451         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1452         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1453                                 + VLAN_TAG_SIZE;
1454
1455         PMD_INIT_FUNC_TRACE();
1456
1457         if (dpni == NULL) {
1458                 DPAA2_PMD_ERR("dpni is NULL");
1459                 return -EINVAL;
1460         }
1461
1462         /* Set the Max Rx frame length as 'mtu' +
1463          * Maximum Ethernet header length
1464          */
1465         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1466                                         frame_size - RTE_ETHER_CRC_LEN);
1467         if (ret) {
1468                 DPAA2_PMD_ERR("Setting the max frame length failed");
1469                 return -1;
1470         }
1471         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1472         return 0;
1473 }
1474
1475 static int
1476 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1477                        struct rte_ether_addr *addr,
1478                        __rte_unused uint32_t index,
1479                        __rte_unused uint32_t pool)
1480 {
1481         int ret;
1482         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1483         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1484
1485         PMD_INIT_FUNC_TRACE();
1486
1487         if (dpni == NULL) {
1488                 DPAA2_PMD_ERR("dpni is NULL");
1489                 return -1;
1490         }
1491
1492         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1493                                 addr->addr_bytes, 0, 0, 0);
1494         if (ret)
1495                 DPAA2_PMD_ERR(
1496                         "error: Adding the MAC ADDR failed: err = %d", ret);
1497         return 0;
1498 }
1499
1500 static void
1501 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1502                           uint32_t index)
1503 {
1504         int ret;
1505         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1506         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1507         struct rte_eth_dev_data *data = dev->data;
1508         struct rte_ether_addr *macaddr;
1509
1510         PMD_INIT_FUNC_TRACE();
1511
1512         macaddr = &data->mac_addrs[index];
1513
1514         if (dpni == NULL) {
1515                 DPAA2_PMD_ERR("dpni is NULL");
1516                 return;
1517         }
1518
1519         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1520                                    priv->token, macaddr->addr_bytes);
1521         if (ret)
1522                 DPAA2_PMD_ERR(
1523                         "error: Removing the MAC ADDR failed: err = %d", ret);
1524 }
1525
1526 static int
1527 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1528                        struct rte_ether_addr *addr)
1529 {
1530         int ret;
1531         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1532         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1533
1534         PMD_INIT_FUNC_TRACE();
1535
1536         if (dpni == NULL) {
1537                 DPAA2_PMD_ERR("dpni is NULL");
1538                 return -EINVAL;
1539         }
1540
1541         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1542                                         priv->token, addr->addr_bytes);
1543
1544         if (ret)
1545                 DPAA2_PMD_ERR(
1546                         "error: Setting the MAC ADDR failed %d", ret);
1547
1548         return ret;
1549 }
1550
1551 static
1552 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1553                          struct rte_eth_stats *stats)
1554 {
1555         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1556         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1557         int32_t  retcode;
1558         uint8_t page0 = 0, page1 = 1, page2 = 2;
1559         union dpni_statistics value;
1560         int i;
1561         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1562
1563         memset(&value, 0, sizeof(union dpni_statistics));
1564
1565         PMD_INIT_FUNC_TRACE();
1566
1567         if (!dpni) {
1568                 DPAA2_PMD_ERR("dpni is NULL");
1569                 return -EINVAL;
1570         }
1571
1572         if (!stats) {
1573                 DPAA2_PMD_ERR("stats is NULL");
1574                 return -EINVAL;
1575         }
1576
1577         /*Get Counters from page_0*/
1578         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1579                                       page0, 0, &value);
1580         if (retcode)
1581                 goto err;
1582
1583         stats->ipackets = value.page_0.ingress_all_frames;
1584         stats->ibytes = value.page_0.ingress_all_bytes;
1585
1586         /*Get Counters from page_1*/
1587         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1588                                       page1, 0, &value);
1589         if (retcode)
1590                 goto err;
1591
1592         stats->opackets = value.page_1.egress_all_frames;
1593         stats->obytes = value.page_1.egress_all_bytes;
1594
1595         /*Get Counters from page_2*/
1596         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1597                                       page2, 0, &value);
1598         if (retcode)
1599                 goto err;
1600
1601         /* Ingress drop frame count due to configured rules */
1602         stats->ierrors = value.page_2.ingress_filtered_frames;
1603         /* Ingress drop frame count due to error */
1604         stats->ierrors += value.page_2.ingress_discarded_frames;
1605
1606         stats->oerrors = value.page_2.egress_discarded_frames;
1607         stats->imissed = value.page_2.ingress_nobuffer_discards;
1608
1609         /* Fill in per queue stats */
1610         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1611                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1612                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1613                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1614                 if (dpaa2_rxq)
1615                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1616                 if (dpaa2_txq)
1617                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1618
1619                 /* Byte counting is not implemented */
1620                 stats->q_ibytes[i]   = 0;
1621                 stats->q_obytes[i]   = 0;
1622         }
1623
1624         return 0;
1625
1626 err:
1627         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1628         return retcode;
1629 };
1630
1631 static int
1632 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1633                      unsigned int n)
1634 {
1635         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1636         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1637         int32_t  retcode;
1638         union dpni_statistics value[5] = {};
1639         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1640
1641         if (n < num)
1642                 return num;
1643
1644         if (xstats == NULL)
1645                 return 0;
1646
1647         /* Get Counters from page_0*/
1648         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1649                                       0, 0, &value[0]);
1650         if (retcode)
1651                 goto err;
1652
1653         /* Get Counters from page_1*/
1654         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1655                                       1, 0, &value[1]);
1656         if (retcode)
1657                 goto err;
1658
1659         /* Get Counters from page_2*/
1660         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1661                                       2, 0, &value[2]);
1662         if (retcode)
1663                 goto err;
1664
1665         for (i = 0; i < priv->max_cgs; i++) {
1666                 if (!priv->cgid_in_use[i]) {
1667                         /* Get Counters from page_4*/
1668                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1669                                                       priv->token,
1670                                                       4, 0, &value[4]);
1671                         if (retcode)
1672                                 goto err;
1673                         break;
1674                 }
1675         }
1676
1677         for (i = 0; i < num; i++) {
1678                 xstats[i].id = i;
1679                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1680                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1681         }
1682         return i;
1683 err:
1684         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1685         return retcode;
1686 }
1687
1688 static int
1689 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1690                        struct rte_eth_xstat_name *xstats_names,
1691                        unsigned int limit)
1692 {
1693         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1694
1695         if (limit < stat_cnt)
1696                 return stat_cnt;
1697
1698         if (xstats_names != NULL)
1699                 for (i = 0; i < stat_cnt; i++)
1700                         strlcpy(xstats_names[i].name,
1701                                 dpaa2_xstats_strings[i].name,
1702                                 sizeof(xstats_names[i].name));
1703
1704         return stat_cnt;
1705 }
1706
1707 static int
1708 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1709                        uint64_t *values, unsigned int n)
1710 {
1711         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1712         uint64_t values_copy[stat_cnt];
1713
1714         if (!ids) {
1715                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1716                 struct fsl_mc_io *dpni =
1717                         (struct fsl_mc_io *)dev->process_private;
1718                 int32_t  retcode;
1719                 union dpni_statistics value[5] = {};
1720
1721                 if (n < stat_cnt)
1722                         return stat_cnt;
1723
1724                 if (!values)
1725                         return 0;
1726
1727                 /* Get Counters from page_0*/
1728                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1729                                               0, 0, &value[0]);
1730                 if (retcode)
1731                         return 0;
1732
1733                 /* Get Counters from page_1*/
1734                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1735                                               1, 0, &value[1]);
1736                 if (retcode)
1737                         return 0;
1738
1739                 /* Get Counters from page_2*/
1740                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1741                                               2, 0, &value[2]);
1742                 if (retcode)
1743                         return 0;
1744
1745                 /* Get Counters from page_4*/
1746                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1747                                               4, 0, &value[4]);
1748                 if (retcode)
1749                         return 0;
1750
1751                 for (i = 0; i < stat_cnt; i++) {
1752                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1753                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1754                 }
1755                 return stat_cnt;
1756         }
1757
1758         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1759
1760         for (i = 0; i < n; i++) {
1761                 if (ids[i] >= stat_cnt) {
1762                         DPAA2_PMD_ERR("xstats id value isn't valid");
1763                         return -1;
1764                 }
1765                 values[i] = values_copy[ids[i]];
1766         }
1767         return n;
1768 }
1769
1770 static int
1771 dpaa2_xstats_get_names_by_id(
1772         struct rte_eth_dev *dev,
1773         const uint64_t *ids,
1774         struct rte_eth_xstat_name *xstats_names,
1775         unsigned int limit)
1776 {
1777         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1778         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1779
1780         if (!ids)
1781                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1782
1783         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1784
1785         for (i = 0; i < limit; i++) {
1786                 if (ids[i] >= stat_cnt) {
1787                         DPAA2_PMD_ERR("xstats id value isn't valid");
1788                         return -1;
1789                 }
1790                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1791         }
1792         return limit;
1793 }
1794
1795 static int
1796 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1797 {
1798         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1799         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1800         int retcode;
1801         int i;
1802         struct dpaa2_queue *dpaa2_q;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         if (dpni == NULL) {
1807                 DPAA2_PMD_ERR("dpni is NULL");
1808                 return -EINVAL;
1809         }
1810
1811         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1812         if (retcode)
1813                 goto error;
1814
1815         /* Reset the per queue stats in dpaa2_queue structure */
1816         for (i = 0; i < priv->nb_rx_queues; i++) {
1817                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1818                 if (dpaa2_q)
1819                         dpaa2_q->rx_pkts = 0;
1820         }
1821
1822         for (i = 0; i < priv->nb_tx_queues; i++) {
1823                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1824                 if (dpaa2_q)
1825                         dpaa2_q->tx_pkts = 0;
1826         }
1827
1828         return 0;
1829
1830 error:
1831         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1832         return retcode;
1833 };
1834
1835 /* return 0 means link status changed, -1 means not changed */
1836 static int
1837 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1838                       int wait_to_complete)
1839 {
1840         int ret;
1841         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1842         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1843         struct rte_eth_link link;
1844         struct dpni_link_state state = {0};
1845         uint8_t count;
1846
1847         if (dpni == NULL) {
1848                 DPAA2_PMD_ERR("dpni is NULL");
1849                 return 0;
1850         }
1851
1852         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1853                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1854                                           &state);
1855                 if (ret < 0) {
1856                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1857                         return -1;
1858                 }
1859                 if (state.up == RTE_ETH_LINK_DOWN &&
1860                     wait_to_complete)
1861                         rte_delay_ms(CHECK_INTERVAL);
1862                 else
1863                         break;
1864         }
1865
1866         memset(&link, 0, sizeof(struct rte_eth_link));
1867         link.link_status = state.up;
1868         link.link_speed = state.rate;
1869
1870         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1871                 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1872         else
1873                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1874
1875         ret = rte_eth_linkstatus_set(dev, &link);
1876         if (ret == -1)
1877                 DPAA2_PMD_DEBUG("No change in status");
1878         else
1879                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1880                                link.link_status ? "Up" : "Down");
1881
1882         return ret;
1883 }
1884
1885 /**
1886  * Toggle the DPNI to enable, if not already enabled.
1887  * This is not strictly PHY up/down - it is more of logical toggling.
1888  */
1889 static int
1890 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1891 {
1892         int ret = -EINVAL;
1893         struct dpaa2_dev_priv *priv;
1894         struct fsl_mc_io *dpni;
1895         int en = 0;
1896         struct dpni_link_state state = {0};
1897
1898         priv = dev->data->dev_private;
1899         dpni = (struct fsl_mc_io *)dev->process_private;
1900
1901         if (dpni == NULL) {
1902                 DPAA2_PMD_ERR("dpni is NULL");
1903                 return ret;
1904         }
1905
1906         /* Check if DPNI is currently enabled */
1907         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1908         if (ret) {
1909                 /* Unable to obtain dpni status; Not continuing */
1910                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1911                 return -EINVAL;
1912         }
1913
1914         /* Enable link if not already enabled */
1915         if (!en) {
1916                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1917                 if (ret) {
1918                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1919                         return -EINVAL;
1920                 }
1921         }
1922         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1923         if (ret < 0) {
1924                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1925                 return -1;
1926         }
1927
1928         /* changing tx burst function to start enqueues */
1929         dev->tx_pkt_burst = dpaa2_dev_tx;
1930         dev->data->dev_link.link_status = state.up;
1931         dev->data->dev_link.link_speed = state.rate;
1932
1933         if (state.up)
1934                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1935         else
1936                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1937         return ret;
1938 }
1939
1940 /**
1941  * Toggle the DPNI to disable, if not already disabled.
1942  * This is not strictly PHY up/down - it is more of logical toggling.
1943  */
1944 static int
1945 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1946 {
1947         int ret = -EINVAL;
1948         struct dpaa2_dev_priv *priv;
1949         struct fsl_mc_io *dpni;
1950         int dpni_enabled = 0;
1951         int retries = 10;
1952
1953         PMD_INIT_FUNC_TRACE();
1954
1955         priv = dev->data->dev_private;
1956         dpni = (struct fsl_mc_io *)dev->process_private;
1957
1958         if (dpni == NULL) {
1959                 DPAA2_PMD_ERR("Device has not yet been configured");
1960                 return ret;
1961         }
1962
1963         /*changing  tx burst function to avoid any more enqueues */
1964         dev->tx_pkt_burst = dummy_dev_tx;
1965
1966         /* Loop while dpni_disable() attempts to drain the egress FQs
1967          * and confirm them back to us.
1968          */
1969         do {
1970                 ret = dpni_disable(dpni, 0, priv->token);
1971                 if (ret) {
1972                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1973                         return ret;
1974                 }
1975                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1976                 if (ret) {
1977                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1978                         return ret;
1979                 }
1980                 if (dpni_enabled)
1981                         /* Allow the MC some slack */
1982                         rte_delay_us(100 * 1000);
1983         } while (dpni_enabled && --retries);
1984
1985         if (!retries) {
1986                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1987                 /* todo- we may have to manually cleanup queues.
1988                  */
1989         } else {
1990                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1991                                dev->data->port_id);
1992         }
1993
1994         dev->data->dev_link.link_status = 0;
1995
1996         return ret;
1997 }
1998
1999 static int
2000 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2001 {
2002         int ret = -EINVAL;
2003         struct dpaa2_dev_priv *priv;
2004         struct fsl_mc_io *dpni;
2005         struct dpni_link_state state = {0};
2006
2007         PMD_INIT_FUNC_TRACE();
2008
2009         priv = dev->data->dev_private;
2010         dpni = (struct fsl_mc_io *)dev->process_private;
2011
2012         if (dpni == NULL || fc_conf == NULL) {
2013                 DPAA2_PMD_ERR("device not configured");
2014                 return ret;
2015         }
2016
2017         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2018         if (ret) {
2019                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2020                 return ret;
2021         }
2022
2023         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2024         if (state.options & DPNI_LINK_OPT_PAUSE) {
2025                 /* DPNI_LINK_OPT_PAUSE set
2026                  *  if ASYM_PAUSE not set,
2027                  *      RX Side flow control (handle received Pause frame)
2028                  *      TX side flow control (send Pause frame)
2029                  *  if ASYM_PAUSE set,
2030                  *      RX Side flow control (handle received Pause frame)
2031                  *      No TX side flow control (send Pause frame disabled)
2032                  */
2033                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2034                         fc_conf->mode = RTE_ETH_FC_FULL;
2035                 else
2036                         fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2037         } else {
2038                 /* DPNI_LINK_OPT_PAUSE not set
2039                  *  if ASYM_PAUSE set,
2040                  *      TX side flow control (send Pause frame)
2041                  *      No RX side flow control (No action on pause frame rx)
2042                  *  if ASYM_PAUSE not set,
2043                  *      Flow control disabled
2044                  */
2045                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2046                         fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2047                 else
2048                         fc_conf->mode = RTE_ETH_FC_NONE;
2049         }
2050
2051         return ret;
2052 }
2053
2054 static int
2055 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2056 {
2057         int ret = -EINVAL;
2058         struct dpaa2_dev_priv *priv;
2059         struct fsl_mc_io *dpni;
2060         struct dpni_link_state state = {0};
2061         struct dpni_link_cfg cfg = {0};
2062
2063         PMD_INIT_FUNC_TRACE();
2064
2065         priv = dev->data->dev_private;
2066         dpni = (struct fsl_mc_io *)dev->process_private;
2067
2068         if (dpni == NULL) {
2069                 DPAA2_PMD_ERR("dpni is NULL");
2070                 return ret;
2071         }
2072
2073         /* It is necessary to obtain the current state before setting fc_conf
2074          * as MC would return error in case rate, autoneg or duplex values are
2075          * different.
2076          */
2077         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2078         if (ret) {
2079                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2080                 return -1;
2081         }
2082
2083         /* Disable link before setting configuration */
2084         dpaa2_dev_set_link_down(dev);
2085
2086         /* Based on fc_conf, update cfg */
2087         cfg.rate = state.rate;
2088         cfg.options = state.options;
2089
2090         /* update cfg with fc_conf */
2091         switch (fc_conf->mode) {
2092         case RTE_ETH_FC_FULL:
2093                 /* Full flow control;
2094                  * OPT_PAUSE set, ASYM_PAUSE not set
2095                  */
2096                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2097                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2098                 break;
2099         case RTE_ETH_FC_TX_PAUSE:
2100                 /* Enable RX flow control
2101                  * OPT_PAUSE not set;
2102                  * ASYM_PAUSE set;
2103                  */
2104                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2105                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2106                 break;
2107         case RTE_ETH_FC_RX_PAUSE:
2108                 /* Enable TX Flow control
2109                  * OPT_PAUSE set
2110                  * ASYM_PAUSE set
2111                  */
2112                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2113                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2114                 break;
2115         case RTE_ETH_FC_NONE:
2116                 /* Disable Flow control
2117                  * OPT_PAUSE not set
2118                  * ASYM_PAUSE not set
2119                  */
2120                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2121                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2122                 break;
2123         default:
2124                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2125                               fc_conf->mode);
2126                 return -1;
2127         }
2128
2129         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2130         if (ret)
2131                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2132                               ret);
2133
2134         /* Enable link */
2135         dpaa2_dev_set_link_up(dev);
2136
2137         return ret;
2138 }
2139
2140 static int
2141 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2142                           struct rte_eth_rss_conf *rss_conf)
2143 {
2144         struct rte_eth_dev_data *data = dev->data;
2145         struct dpaa2_dev_priv *priv = data->dev_private;
2146         struct rte_eth_conf *eth_conf = &data->dev_conf;
2147         int ret, tc_index;
2148
2149         PMD_INIT_FUNC_TRACE();
2150
2151         if (rss_conf->rss_hf) {
2152                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2153                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2154                                 tc_index);
2155                         if (ret) {
2156                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2157                                         tc_index);
2158                                 return ret;
2159                         }
2160                 }
2161         } else {
2162                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2163                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2164                         if (ret) {
2165                                 DPAA2_PMD_ERR(
2166                                         "Unable to remove flow dist on tc%d",
2167                                         tc_index);
2168                                 return ret;
2169                         }
2170                 }
2171         }
2172         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2173         return 0;
2174 }
2175
2176 static int
2177 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2178                             struct rte_eth_rss_conf *rss_conf)
2179 {
2180         struct rte_eth_dev_data *data = dev->data;
2181         struct rte_eth_conf *eth_conf = &data->dev_conf;
2182
2183         /* dpaa2 does not support rss_key, so length should be 0*/
2184         rss_conf->rss_key_len = 0;
2185         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2186         return 0;
2187 }
2188
2189 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2190                 int eth_rx_queue_id,
2191                 struct dpaa2_dpcon_dev *dpcon,
2192                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2193 {
2194         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2195         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2196         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2197         uint8_t flow_id = dpaa2_ethq->flow_id;
2198         struct dpni_queue cfg;
2199         uint8_t options, priority;
2200         int ret;
2201
2202         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2203                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2204         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2205                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2206         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2207                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2208         else
2209                 return -EINVAL;
2210
2211         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2212                    (dpcon->num_priorities - 1);
2213
2214         memset(&cfg, 0, sizeof(struct dpni_queue));
2215         options = DPNI_QUEUE_OPT_DEST;
2216         cfg.destination.type = DPNI_DEST_DPCON;
2217         cfg.destination.id = dpcon->dpcon_id;
2218         cfg.destination.priority = priority;
2219
2220         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2221                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2222                 cfg.destination.hold_active = 1;
2223         }
2224
2225         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2226                         !eth_priv->en_ordered) {
2227                 struct opr_cfg ocfg;
2228
2229                 /* Restoration window size = 256 frames */
2230                 ocfg.oprrws = 3;
2231                 /* Restoration window size = 512 frames for LX2 */
2232                 if (dpaa2_svr_family == SVR_LX2160A)
2233                         ocfg.oprrws = 4;
2234                 /* Auto advance NESN window enabled */
2235                 ocfg.oa = 1;
2236                 /* Late arrival window size disabled */
2237                 ocfg.olws = 0;
2238                 /* ORL resource exhaustaion advance NESN disabled */
2239                 ocfg.oeane = 0;
2240                 /* Loose ordering enabled */
2241                 ocfg.oloe = 1;
2242                 eth_priv->en_loose_ordered = 1;
2243                 /* Strict ordering enabled if explicitly set */
2244                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2245                         ocfg.oloe = 0;
2246                         eth_priv->en_loose_ordered = 0;
2247                 }
2248
2249                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2250                                    dpaa2_ethq->tc_index, flow_id,
2251                                    OPR_OPT_CREATE, &ocfg, 0);
2252                 if (ret) {
2253                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2254                         return ret;
2255                 }
2256
2257                 eth_priv->en_ordered = 1;
2258         }
2259
2260         options |= DPNI_QUEUE_OPT_USER_CTX;
2261         cfg.user_context = (size_t)(dpaa2_ethq);
2262
2263         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2264                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2265         if (ret) {
2266                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2267                 return ret;
2268         }
2269
2270         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2271
2272         return 0;
2273 }
2274
2275 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2276                 int eth_rx_queue_id)
2277 {
2278         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2279         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2280         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2281         uint8_t flow_id = dpaa2_ethq->flow_id;
2282         struct dpni_queue cfg;
2283         uint8_t options;
2284         int ret;
2285
2286         memset(&cfg, 0, sizeof(struct dpni_queue));
2287         options = DPNI_QUEUE_OPT_DEST;
2288         cfg.destination.type = DPNI_DEST_NONE;
2289
2290         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2291                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2292         if (ret)
2293                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2294
2295         return ret;
2296 }
2297
2298 static int
2299 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2300                        const struct rte_flow_ops **ops)
2301 {
2302         if (!dev)
2303                 return -ENODEV;
2304
2305         *ops = &dpaa2_flow_ops;
2306         return 0;
2307 }
2308
2309 static void
2310 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2311         struct rte_eth_rxq_info *qinfo)
2312 {
2313         struct dpaa2_queue *rxq;
2314         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2315         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2316         uint16_t max_frame_length;
2317
2318         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2319
2320         qinfo->mp = rxq->mb_pool;
2321         qinfo->scattered_rx = dev->data->scattered_rx;
2322         qinfo->nb_desc = rxq->nb_desc;
2323         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2324                                 &max_frame_length) == 0)
2325                 qinfo->rx_buf_size = max_frame_length;
2326
2327         qinfo->conf.rx_free_thresh = 1;
2328         qinfo->conf.rx_drop_en = 1;
2329         qinfo->conf.rx_deferred_start = 0;
2330         qinfo->conf.offloads = rxq->offloads;
2331 }
2332
2333 static void
2334 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2335         struct rte_eth_txq_info *qinfo)
2336 {
2337         struct dpaa2_queue *txq;
2338
2339         txq = dev->data->tx_queues[queue_id];
2340
2341         qinfo->nb_desc = txq->nb_desc;
2342         qinfo->conf.tx_thresh.pthresh = 0;
2343         qinfo->conf.tx_thresh.hthresh = 0;
2344         qinfo->conf.tx_thresh.wthresh = 0;
2345
2346         qinfo->conf.tx_free_thresh = 0;
2347         qinfo->conf.tx_rs_thresh = 0;
2348         qinfo->conf.offloads = txq->offloads;
2349         qinfo->conf.tx_deferred_start = 0;
2350 }
2351
2352 static int
2353 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2354 {
2355         *(const void **)ops = &dpaa2_tm_ops;
2356
2357         return 0;
2358 }
2359
2360 void
2361 rte_pmd_dpaa2_thread_init(void)
2362 {
2363         int ret;
2364
2365         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2366                 ret = dpaa2_affine_qbman_swp();
2367                 if (ret) {
2368                         DPAA2_PMD_ERR(
2369                                 "Failed to allocate IO portal, tid: %d\n",
2370                                 rte_gettid());
2371                         return;
2372                 }
2373         }
2374 }
2375
2376 static struct eth_dev_ops dpaa2_ethdev_ops = {
2377         .dev_configure    = dpaa2_eth_dev_configure,
2378         .dev_start            = dpaa2_dev_start,
2379         .dev_stop             = dpaa2_dev_stop,
2380         .dev_close            = dpaa2_dev_close,
2381         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2382         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2383         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2384         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2385         .dev_set_link_up      = dpaa2_dev_set_link_up,
2386         .dev_set_link_down    = dpaa2_dev_set_link_down,
2387         .link_update       = dpaa2_dev_link_update,
2388         .stats_get             = dpaa2_dev_stats_get,
2389         .xstats_get            = dpaa2_dev_xstats_get,
2390         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2391         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2392         .xstats_get_names      = dpaa2_xstats_get_names,
2393         .stats_reset       = dpaa2_dev_stats_reset,
2394         .xstats_reset         = dpaa2_dev_stats_reset,
2395         .fw_version_get    = dpaa2_fw_version_get,
2396         .dev_infos_get     = dpaa2_dev_info_get,
2397         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2398         .mtu_set           = dpaa2_dev_mtu_set,
2399         .vlan_filter_set      = dpaa2_vlan_filter_set,
2400         .vlan_offload_set     = dpaa2_vlan_offload_set,
2401         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2402         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2403         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2404         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2405         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2406         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2407         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2408         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2409         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2410         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2411         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2412         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2413         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2414         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2415         .rxq_info_get         = dpaa2_rxq_info_get,
2416         .txq_info_get         = dpaa2_txq_info_get,
2417         .tm_ops_get           = dpaa2_tm_ops_get,
2418 #if defined(RTE_LIBRTE_IEEE1588)
2419         .timesync_enable      = dpaa2_timesync_enable,
2420         .timesync_disable     = dpaa2_timesync_disable,
2421         .timesync_read_time   = dpaa2_timesync_read_time,
2422         .timesync_write_time  = dpaa2_timesync_write_time,
2423         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2424         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2425         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2426 #endif
2427 };
2428
2429 /* Populate the mac address from physically available (u-boot/firmware) and/or
2430  * one set by higher layers like MC (restool) etc.
2431  * Returns the table of MAC entries (multiple entries)
2432  */
2433 static int
2434 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2435                   struct rte_ether_addr *mac_entry)
2436 {
2437         int ret;
2438         struct rte_ether_addr phy_mac, prime_mac;
2439
2440         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2441         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2442
2443         /* Get the physical device MAC address */
2444         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2445                                      phy_mac.addr_bytes);
2446         if (ret) {
2447                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2448                 goto cleanup;
2449         }
2450
2451         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2452                                         prime_mac.addr_bytes);
2453         if (ret) {
2454                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2455                 goto cleanup;
2456         }
2457
2458         /* Now that both MAC have been obtained, do:
2459          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2460          *     and return phy
2461          *  If empty_mac(phy), return prime.
2462          *  if both are empty, create random MAC, set as prime and return
2463          */
2464         if (!rte_is_zero_ether_addr(&phy_mac)) {
2465                 /* If the addresses are not same, overwrite prime */
2466                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2467                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2468                                                         priv->token,
2469                                                         phy_mac.addr_bytes);
2470                         if (ret) {
2471                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2472                                               ret);
2473                                 goto cleanup;
2474                         }
2475                         memcpy(&prime_mac, &phy_mac,
2476                                 sizeof(struct rte_ether_addr));
2477                 }
2478         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2479                 /* In case phys and prime, both are zero, create random MAC */
2480                 rte_eth_random_addr(prime_mac.addr_bytes);
2481                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2482                                                 priv->token,
2483                                                 prime_mac.addr_bytes);
2484                 if (ret) {
2485                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2486                         goto cleanup;
2487                 }
2488         }
2489
2490         /* prime_mac the final MAC address */
2491         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2492         return 0;
2493
2494 cleanup:
2495         return -1;
2496 }
2497
2498 static int
2499 check_devargs_handler(__rte_unused const char *key, const char *value,
2500                       __rte_unused void *opaque)
2501 {
2502         if (strcmp(value, "1"))
2503                 return -1;
2504
2505         return 0;
2506 }
2507
2508 static int
2509 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2510 {
2511         struct rte_kvargs *kvlist;
2512
2513         if (!devargs)
2514                 return 0;
2515
2516         kvlist = rte_kvargs_parse(devargs->args, NULL);
2517         if (!kvlist)
2518                 return 0;
2519
2520         if (!rte_kvargs_count(kvlist, key)) {
2521                 rte_kvargs_free(kvlist);
2522                 return 0;
2523         }
2524
2525         if (rte_kvargs_process(kvlist, key,
2526                                check_devargs_handler, NULL) < 0) {
2527                 rte_kvargs_free(kvlist);
2528                 return 0;
2529         }
2530         rte_kvargs_free(kvlist);
2531
2532         return 1;
2533 }
2534
2535 static int
2536 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2537 {
2538         struct rte_device *dev = eth_dev->device;
2539         struct rte_dpaa2_device *dpaa2_dev;
2540         struct fsl_mc_io *dpni_dev;
2541         struct dpni_attr attr;
2542         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2543         struct dpni_buffer_layout layout;
2544         int ret, hw_id, i;
2545
2546         PMD_INIT_FUNC_TRACE();
2547
2548         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2549         if (!dpni_dev) {
2550                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2551                 return -1;
2552         }
2553         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2554         eth_dev->process_private = (void *)dpni_dev;
2555
2556         /* For secondary processes, the primary has done all the work */
2557         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2558                 /* In case of secondary, only burst and ops API need to be
2559                  * plugged.
2560                  */
2561                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2562                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2563                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2564                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2565                 else if (dpaa2_get_devargs(dev->devargs,
2566                                         DRIVER_NO_PREFETCH_MODE))
2567                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2568                 else
2569                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2570                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2571                 return 0;
2572         }
2573
2574         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2575
2576         hw_id = dpaa2_dev->object_id;
2577         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2578         if (ret) {
2579                 DPAA2_PMD_ERR(
2580                              "Failure in opening dpni@%d with err code %d",
2581                              hw_id, ret);
2582                 rte_free(dpni_dev);
2583                 return -1;
2584         }
2585
2586         /* Clean the device first */
2587         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2588         if (ret) {
2589                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2590                               hw_id, ret);
2591                 goto init_err;
2592         }
2593
2594         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2595         if (ret) {
2596                 DPAA2_PMD_ERR(
2597                              "Failure in get dpni@%d attribute, err code %d",
2598                              hw_id, ret);
2599                 goto init_err;
2600         }
2601
2602         priv->num_rx_tc = attr.num_rx_tcs;
2603         priv->qos_entries = attr.qos_entries;
2604         priv->fs_entries = attr.fs_entries;
2605         priv->dist_queues = attr.num_queues;
2606
2607         /* only if the custom CG is enabled */
2608         if (attr.options & DPNI_OPT_CUSTOM_CG)
2609                 priv->max_cgs = attr.num_cgs;
2610         else
2611                 priv->max_cgs = 0;
2612
2613         for (i = 0; i < priv->max_cgs; i++)
2614                 priv->cgid_in_use[i] = 0;
2615
2616         for (i = 0; i < attr.num_rx_tcs; i++)
2617                 priv->nb_rx_queues += attr.num_queues;
2618
2619         /* Using number of TX queues as number of TX TCs */
2620         priv->nb_tx_queues = attr.num_tx_tcs;
2621
2622         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2623                         priv->num_rx_tc, priv->nb_rx_queues,
2624                         priv->nb_tx_queues, priv->max_cgs);
2625
2626         priv->hw = dpni_dev;
2627         priv->hw_id = hw_id;
2628         priv->options = attr.options;
2629         priv->max_mac_filters = attr.mac_filter_entries;
2630         priv->max_vlan_filters = attr.vlan_filter_entries;
2631         priv->flags = 0;
2632 #if defined(RTE_LIBRTE_IEEE1588)
2633         printf("DPDK IEEE1588 is enabled\n");
2634         priv->flags |= DPAA2_TX_CONF_ENABLE;
2635 #endif
2636         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2637         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2638                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2639                 DPAA2_PMD_INFO("TX_CONF Enabled");
2640         }
2641
2642         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2643                 dpaa2_enable_err_queue = 1;
2644                 DPAA2_PMD_INFO("Enable error queue");
2645         }
2646
2647         /* Allocate memory for hardware structure for queues */
2648         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2649         if (ret) {
2650                 DPAA2_PMD_ERR("Queue allocation Failed");
2651                 goto init_err;
2652         }
2653
2654         /* Allocate memory for storing MAC addresses.
2655          * Table of mac_filter_entries size is allocated so that RTE ether lib
2656          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2657          */
2658         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2659                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2660         if (eth_dev->data->mac_addrs == NULL) {
2661                 DPAA2_PMD_ERR(
2662                    "Failed to allocate %d bytes needed to store MAC addresses",
2663                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2664                 ret = -ENOMEM;
2665                 goto init_err;
2666         }
2667
2668         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2669         if (ret) {
2670                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2671                 rte_free(eth_dev->data->mac_addrs);
2672                 eth_dev->data->mac_addrs = NULL;
2673                 goto init_err;
2674         }
2675
2676         /* ... tx buffer layout ... */
2677         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2678         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2679                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2680                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2681                 layout.pass_timestamp = true;
2682         } else {
2683                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2684         }
2685         layout.pass_frame_status = 1;
2686         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2687                                      DPNI_QUEUE_TX, &layout);
2688         if (ret) {
2689                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2690                 goto init_err;
2691         }
2692
2693         /* ... tx-conf and error buffer layout ... */
2694         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2695         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2696                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2697                 layout.pass_timestamp = true;
2698         }
2699         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2700         layout.pass_frame_status = 1;
2701         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2702                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2703         if (ret) {
2704                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2705                              ret);
2706                 goto init_err;
2707         }
2708
2709         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2710
2711         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2712                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2713                 DPAA2_PMD_INFO("Loopback mode");
2714         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2715                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2716                 DPAA2_PMD_INFO("No Prefetch mode");
2717         } else {
2718                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2719         }
2720         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2721
2722         /*Init fields w.r.t. classficaition*/
2723         memset(&priv->extract.qos_key_extract, 0,
2724                 sizeof(struct dpaa2_key_extract));
2725         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2726         if (!priv->extract.qos_extract_param) {
2727                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2728                             " classificaiton ", ret);
2729                 goto init_err;
2730         }
2731         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2732                 IP_ADDRESS_OFFSET_INVALID;
2733         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2734                 IP_ADDRESS_OFFSET_INVALID;
2735         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2736                 IP_ADDRESS_OFFSET_INVALID;
2737         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2738                 IP_ADDRESS_OFFSET_INVALID;
2739
2740         for (i = 0; i < MAX_TCS; i++) {
2741                 memset(&priv->extract.tc_key_extract[i], 0,
2742                         sizeof(struct dpaa2_key_extract));
2743                 priv->extract.tc_extract_param[i] =
2744                         (size_t)rte_malloc(NULL, 256, 64);
2745                 if (!priv->extract.tc_extract_param[i]) {
2746                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2747                                      ret);
2748                         goto init_err;
2749                 }
2750                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2751                         IP_ADDRESS_OFFSET_INVALID;
2752                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2753                         IP_ADDRESS_OFFSET_INVALID;
2754                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2755                         IP_ADDRESS_OFFSET_INVALID;
2756                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2757                         IP_ADDRESS_OFFSET_INVALID;
2758         }
2759
2760         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2761                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2762                                         + VLAN_TAG_SIZE);
2763         if (ret) {
2764                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2765                 goto init_err;
2766         }
2767
2768         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2769          * with external entity to receive byte code for software sequence
2770          * and same will be offload to the H/W using MC interface.
2771          * Currently it is assumed that DPAA2 driver has byte code by some
2772          * mean and same if offloaded to H/W.
2773          */
2774         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2775                 WRIOP_SS_INITIALIZER(priv);
2776                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2777                 if (ret < 0) {
2778                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2779                                       ret);
2780                         return ret;
2781                 }
2782
2783                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2784                                                          DPNI_SS_INGRESS);
2785                 if (ret < 0) {
2786                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2787                                       ret);
2788                         return ret;
2789                 }
2790         }
2791         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2792         return 0;
2793 init_err:
2794         dpaa2_dev_close(eth_dev);
2795
2796         return ret;
2797 }
2798
2799 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2800 {
2801         return dev->device->driver == &rte_dpaa2_pmd.driver;
2802 }
2803
2804 static int
2805 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2806                 struct rte_dpaa2_device *dpaa2_dev)
2807 {
2808         struct rte_eth_dev *eth_dev;
2809         struct dpaa2_dev_priv *dev_priv;
2810         int diag;
2811
2812         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2813                 RTE_PKTMBUF_HEADROOM) {
2814                 DPAA2_PMD_ERR(
2815                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2816                 RTE_PKTMBUF_HEADROOM,
2817                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2818
2819                 return -1;
2820         }
2821
2822         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2823                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2824                 if (!eth_dev)
2825                         return -ENODEV;
2826                 dev_priv = rte_zmalloc("ethdev private structure",
2827                                        sizeof(struct dpaa2_dev_priv),
2828                                        RTE_CACHE_LINE_SIZE);
2829                 if (dev_priv == NULL) {
2830                         DPAA2_PMD_CRIT(
2831                                 "Unable to allocate memory for private data");
2832                         rte_eth_dev_release_port(eth_dev);
2833                         return -ENOMEM;
2834                 }
2835                 eth_dev->data->dev_private = (void *)dev_priv;
2836                 /* Store a pointer to eth_dev in dev_private */
2837                 dev_priv->eth_dev = eth_dev;
2838         } else {
2839                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2840                 if (!eth_dev) {
2841                         DPAA2_PMD_DEBUG("returning enodev");
2842                         return -ENODEV;
2843                 }
2844         }
2845
2846         eth_dev->device = &dpaa2_dev->device;
2847
2848         dpaa2_dev->eth_dev = eth_dev;
2849         eth_dev->data->rx_mbuf_alloc_failed = 0;
2850
2851         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2852                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2853
2854         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2855
2856         /* Invoke PMD device initialization function */
2857         diag = dpaa2_dev_init(eth_dev);
2858         if (diag == 0) {
2859                 rte_eth_dev_probing_finish(eth_dev);
2860                 return 0;
2861         }
2862
2863         rte_eth_dev_release_port(eth_dev);
2864         return diag;
2865 }
2866
2867 static int
2868 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2869 {
2870         struct rte_eth_dev *eth_dev;
2871         int ret;
2872
2873         eth_dev = dpaa2_dev->eth_dev;
2874         dpaa2_dev_close(eth_dev);
2875         ret = rte_eth_dev_release_port(eth_dev);
2876
2877         return ret;
2878 }
2879
2880 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2881         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2882         .drv_type = DPAA2_ETH,
2883         .probe = rte_dpaa2_probe,
2884         .remove = rte_dpaa2_remove,
2885 };
2886
2887 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2888 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2889                 DRIVER_LOOPBACK_MODE "=<int> "
2890                 DRIVER_NO_PREFETCH_MODE "=<int>"
2891                 DRIVER_TX_CONF "=<int>"
2892                 DRIVER_ERROR_QUEUE "=<int>");
2893 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);