drivers/net/enetfec/enet_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020-2021 NXP
   3  */
   4
   5 #ifndef __ENETFEC_ETHDEV_H__
   6 #define __ENETFEC_ETHDEV_H__
   7
   8 #include <rte_ethdev.h>
   9
  10 #define BD_LEN                  49152
  11 #define ENETFEC_TX_FR_SIZE      2048
  12 #define ETH_HLEN                RTE_ETHER_HDR_LEN
  13
  14 /* full duplex */
  15 #define FULL_DUPLEX             0x00
  16
  17 #define MAX_TX_BD_RING_SIZE     512     /* It should be power of 2 */
  18 #define MAX_RX_BD_RING_SIZE     512
  19 #define PKT_MAX_BUF_SIZE        1984
  20 #define OPT_FRAME_SIZE          (PKT_MAX_BUF_SIZE << 16)
  21 #define ENETFEC_MAX_RX_PKT_LEN  3000
  22
  23 #define __iomem
  24 #if defined(RTE_ARCH_ARM)
  25 #if defined(RTE_ARCH_64)
  26 #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
  27 #define dcbf_64(p) dcbf(p)
  28
  29 #else /* RTE_ARCH_32 */
  30 #define dcbf(p) RTE_SET_USED(p)
  31 #define dcbf_64(p) dcbf(p)
  32 #endif
  33
  34 #else
  35 #define dcbf(p) RTE_SET_USED(p)
  36 #define dcbf_64(p) dcbf(p)
  37 #endif
  38
  39 /*
  40  * ENETFEC can support 1 rx and tx queue..
  41  */
  42
  43 #define ENETFEC_MAX_Q           1
  44
  45 #define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
  46 #define readl(p) rte_read32(p)
  47
  48 struct bufdesc {
  49         uint16_t                bd_datlen;  /* buffer data length */
  50         uint16_t                bd_sc;      /* buffer control & status */
  51         uint32_t                bd_bufaddr; /* buffer address */
  52 };
  53
  54 struct bufdesc_ex {
  55         struct                  bufdesc desc;
  56         uint32_t                bd_esc;
  57         uint32_t                bd_prot;
  58         uint32_t                bd_bdu;
  59         uint32_t                ts;
  60         uint16_t                res0[4];
  61 };
  62
  63 struct bufdesc_prop {
  64         int                     queue_id;
  65         /* Addresses of Tx and Rx buffers */
  66         struct bufdesc          *base;
  67         struct bufdesc          *last;
  68         struct bufdesc          *cur;
  69         void __iomem            *active_reg_desc;
  70         uint64_t                descr_baseaddr_p;
  71         unsigned short          ring_size;
  72         unsigned char           d_size;
  73         unsigned char           d_size_log2;
  74 };
  75
  76 struct enetfec_priv_tx_q {
  77         struct bufdesc_prop     bd;
  78         struct rte_mbuf         *tx_mbuf[MAX_TX_BD_RING_SIZE];
  79         struct bufdesc          *dirty_tx;
  80         struct rte_mempool      *pool;
  81         struct enetfec_private  *fep;
  82 };
  83
  84 struct enetfec_priv_rx_q {
  85         struct bufdesc_prop     bd;
  86         struct rte_mbuf         *rx_mbuf[MAX_RX_BD_RING_SIZE];
  87         struct rte_mempool      *pool;
  88         struct enetfec_private  *fep;
  89 };
  90
  91 struct enetfec_private {
  92         struct rte_eth_dev      *dev;
  93         struct rte_eth_stats    stats;
  94         int                     full_duplex;
  95         int                     flag_pause;
  96         int                     flag_csum;
  97         uint32_t                quirks;
  98         uint32_t                cbus_size;
  99         uint32_t                enetfec_e_cntl;
 100         uint16_t                max_rx_queues;
 101         uint16_t                max_tx_queues;
 102         unsigned int            total_tx_ring_size;
 103         unsigned int            total_rx_ring_size;
 104         unsigned int            reg_size;
 105         unsigned int            bd_size;
 106         bool                    bufdesc_ex;
 107         bool                    rgmii_txc_delay;
 108         bool                    rgmii_rxc_delay;
 109         void                    *hw_baseaddr_v;
 110         void                    *bd_addr_v;
 111         uint32_t                hw_baseaddr_p;
 112         uint32_t                bd_addr_p;
 113         uint32_t                bd_addr_p_r[ENETFEC_MAX_Q];
 114         uint32_t                bd_addr_p_t[ENETFEC_MAX_Q];
 115         void                    *dma_baseaddr_r[ENETFEC_MAX_Q];
 116         void                    *dma_baseaddr_t[ENETFEC_MAX_Q];
 117         struct enetfec_priv_rx_q *rx_queues[ENETFEC_MAX_Q];
 118         struct enetfec_priv_tx_q *tx_queues[ENETFEC_MAX_Q];
 119 };
 120
 121 static inline struct
 122 bufdesc *enet_get_nextdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
 123 {
 124         return (bdp >= bd->last) ? bd->base
 125                 : (struct bufdesc *)(((uintptr_t)bdp) + bd->d_size);
 126 }
 127
 128 static inline int
 129 fls64(unsigned long word)
 130 {
 131         return (64 - __builtin_clzl(word)) - 1;
 132 }
 133
 134 static inline struct
 135 bufdesc *enet_get_prevdesc(struct bufdesc *bdp, struct bufdesc_prop *bd)
 136 {
 137         return (bdp <= bd->base) ? bd->last
 138                 : (struct bufdesc *)(((uintptr_t)bdp) - bd->d_size);
 139 }
 140
 141 static inline int
 142 enet_get_bd_index(struct bufdesc *bdp, struct bufdesc_prop *bd)
 143 {
 144         return ((const char *)bdp - (const char *)bd->base) >> bd->d_size_log2;
 145 }
 146
 147 uint16_t enetfec_recv_pkts(void *rxq1, struct rte_mbuf **rx_pkts,
 148                 uint16_t nb_pkts);
 149 uint16_t enetfec_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 150                 uint16_t nb_pkts);
 151
 152 #endif /*__ENETFEC_ETHDEV_H__*/