drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30 #include <rte_os_shim.h>
  31
  32 #include "i40e_logs.h"
  33 #include "base/i40e_prototype.h"
  34 #include "base/i40e_adminq_cmd.h"
  35 #include "base/i40e_type.h"
  36 #include "base/i40e_register.h"
  37 #include "base/i40e_dcb.h"
  38 #include "i40e_ethdev.h"
  39 #include "i40e_rxtx.h"
  40 #include "i40e_pf.h"
  41 #include "i40e_regs.h"
  42 #include "rte_pmd_i40e.h"
  43 #include "i40e_hash.h"
  44
  45 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  46 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  47 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  49 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  50
  51 #define I40E_CLEAR_PXE_WAIT_MS     200
  52 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  53 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  54
  55 /* Maximun number of capability elements */
  56 #define I40E_MAX_CAP_ELE_NUM       128
  57
  58 /* Wait count and interval */
  59 #define I40E_CHK_Q_ENA_COUNT       1000
  60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  61
  62 /* Maximun number of VSI */
  63 #define I40E_MAX_NUM_VSIS          (384UL)
  64
  65 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  66
  67 /* Flow control default timer */
  68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  69
  70 /* Flow control enable fwd bit */
  71 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  72
  73 /* Receive Packet Buffer size */
  74 #define I40E_RXPBSIZE (968 * 1024)
  75
  76 /* Kilobytes shift */
  77 #define I40E_KILOSHIFT 10
  78
  79 /* Flow control default high water */
  80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  81
  82 /* Flow control default low water */
  83 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  84
  85 /* Receive Average Packet Size in Byte*/
  86 #define I40E_PACKET_AVERAGE_SIZE 128
  87
  88 /* Mask of PF interrupt causes */
  89 #define I40E_PFINT_ICR0_ENA_MASK ( \
  90                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  92                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  94                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  95                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  98                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  99
 100 #define I40E_FLOW_TYPES ( \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 110         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 111         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 112
 113 /* Additional timesync values. */
 114 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 115 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 116 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 117 #define I40E_PRTTSYN_TSYNENA     0x80000000
 118 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 119 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 120
 121 /**
 122  * Below are values for writing un-exposed registers suggested
 123  * by silicon experts
 124  */
 125 /* Destination MAC address */
 126 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 127 /* Source MAC address */
 128 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 130 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 132 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 133 /* Single VLAN tag in the inner L2 header */
 134 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 135 /* Source IPv4 address */
 136 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 137 /* Destination IPv4 address */
 138 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 139 /* Source IPv4 address for X722 */
 140 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 141 /* Destination IPv4 address for X722 */
 142 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 143 /* IPv4 Protocol for X722 */
 144 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 145 /* IPv4 Time to Live for X722 */
 146 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 147 /* IPv4 Type of Service (TOS) */
 148 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 149 /* IPv4 Protocol */
 150 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 151 /* IPv4 Time to Live */
 152 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 153 /* Source IPv6 address */
 154 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 155 /* Destination IPv6 address */
 156 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 157 /* IPv6 Traffic Class (TC) */
 158 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 159 /* IPv6 Next Header */
 160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 161 /* IPv6 Hop Limit */
 162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 163 /* Source L4 port */
 164 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 165 /* Destination L4 port */
 166 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 167 /* SCTP verification tag */
 168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 171 /* Source port of tunneling UDP */
 172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 173 /* Destination port of tunneling UDP */
 174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 175 /* UDP Tunneling ID, NVGRE/GRE key */
 176 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 177 /* Last ether type */
 178 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 179 /* Tunneling outer destination IPv4 address */
 180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 181 /* Tunneling outer destination IPv6 address */
 182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 183 /* 1st word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 185 /* 2nd word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 187 /* 3rd word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 189 /* 4th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 191 /* 5th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 193 /* 6th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 195 /* 7th word of flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 197 /* 8th word of flex payload */
 198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 199 /* all 8 words flex payload */
 200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 201 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 202
 203 #define I40E_TRANSLATE_INSET 0
 204 #define I40E_TRANSLATE_REG   1
 205
 206 #define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
 207 #define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
 208 #define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
 209 #define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
 210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
 211 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 212
 213 /* PCI offset for querying capability */
 214 #define PCI_DEV_CAP_REG            0xA4
 215 /* PCI offset for enabling/disabling Extended Tag */
 216 #define PCI_DEV_CTRL_REG           0xA8
 217 /* Bit mask of Extended Tag capability */
 218 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 219 /* Bit shift of Extended Tag enable/disable */
 220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 221 /* Bit mask of Extended Tag enable/disable */
 222 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 223
 224 #define I40E_GLQF_PIT_IPV4_START        2
 225 #define I40E_GLQF_PIT_IPV4_COUNT        2
 226 #define I40E_GLQF_PIT_IPV6_START        4
 227 #define I40E_GLQF_PIT_IPV6_COUNT        2
 228
 229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
 230                                 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
 231                                  I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
 232
 233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
 234                                 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
 235                                  I40E_GLQF_PIT_DEST_OFF_SHIFT)
 236
 237 #define I40E_GLQF_PIT_FSIZE_GET(a)      (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
 238                                          I40E_GLQF_PIT_FSIZE_SHIFT)
 239
 240 #define I40E_GLQF_PIT_BUILD(off, mask)  (((off) << 16) | (mask))
 241 #define I40E_FDIR_FIELD_OFFSET(a)       ((a) >> 1)
 242
 243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 245 static int i40e_dev_configure(struct rte_eth_dev *dev);
 246 static int i40e_dev_start(struct rte_eth_dev *dev);
 247 static int i40e_dev_stop(struct rte_eth_dev *dev);
 248 static int i40e_dev_close(struct rte_eth_dev *dev);
 249 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 257                                struct rte_eth_stats *stats);
 258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_xstat *xstats, unsigned n);
 260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 261                                      struct rte_eth_xstat_name *xstats_names,
 262                                      unsigned limit);
 263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 265                                 char *fw_version, size_t fw_size);
 266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 267                              struct rte_eth_dev_info *dev_info);
 268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 269                                 uint16_t vlan_id,
 270                                 int on);
 271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 272                               enum rte_vlan_type vlan_type,
 273                               uint16_t tpid);
 274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 276                                       uint16_t queue,
 277                                       int on);
 278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 282                               struct rte_eth_fc_conf *fc_conf);
 283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 284                               struct rte_eth_fc_conf *fc_conf);
 285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 286                                        struct rte_eth_pfc_conf *pfc_conf);
 287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 288                             struct rte_ether_addr *mac_addr,
 289                             uint32_t index,
 290                             uint32_t pool);
 291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 293                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 294                                     uint16_t reta_size);
 295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 296                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 297                                    uint16_t reta_size);
 298
 299 static int i40e_get_cap(struct i40e_hw *hw);
 300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 301 static int i40e_pf_setup(struct i40e_pf *pf);
 302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 306                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 307 static void i40e_stat_update_48(struct i40e_hw *hw,
 308                                uint32_t hireg,
 309                                uint32_t loreg,
 310                                bool offset_loaded,
 311                                uint64_t *offset,
 312                                uint64_t *stat);
 313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 314 static void i40e_dev_interrupt_handler(void *param);
 315 static void i40e_dev_alarm_handler(void *param);
 316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 317                                 uint32_t base, uint32_t num);
 318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 320                         uint32_t base);
 321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 322                         uint16_t num);
 323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 324 static int i40e_veb_release(struct i40e_veb *veb);
 325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 326                                                 struct i40e_vsi *vsi);
 327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 329                                              struct i40e_macvlan_filter *mv_f,
 330                                              int num,
 331                                              uint16_t vlan);
 332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 334                                     struct rte_eth_rss_conf *rss_conf);
 335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 336                                       struct rte_eth_rss_conf *rss_conf);
 337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 338                                         struct rte_eth_udp_tunnel *udp_tunnel);
 339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 340                                         struct rte_eth_udp_tunnel *udp_tunnel);
 341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
 343                                  const struct rte_flow_ops **ops);
 344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                   struct rte_eth_dcb_info *dcb_info);
 346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 347 static void i40e_configure_registers(struct i40e_hw *hw);
 348 static void i40e_hw_init(struct rte_eth_dev *dev);
 349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 350
 351 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 352 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 353 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                            struct timespec *timestamp,
 355                                            uint32_t flags);
 356 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                            struct timespec *timestamp);
 358 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 359
 360 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 361
 362 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 363                                    struct timespec *timestamp);
 364 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 365                                     const struct timespec *timestamp);
 366
 367 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 368                                          uint16_t queue_id);
 369 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 370                                           uint16_t queue_id);
 371
 372 static int i40e_get_regs(struct rte_eth_dev *dev,
 373                          struct rte_dev_reg_info *regs);
 374
 375 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 376
 377 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 378                            struct rte_dev_eeprom_info *eeprom);
 379
 380 static int i40e_get_module_info(struct rte_eth_dev *dev,
 381                                 struct rte_eth_dev_module_info *modinfo);
 382 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 383                                   struct rte_dev_eeprom_info *info);
 384
 385 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 386                                       struct rte_ether_addr *mac_addr);
 387
 388 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 389
 390 static int i40e_ethertype_filter_convert(
 391         const struct rte_eth_ethertype_filter *input,
 392         struct i40e_ethertype_filter *filter);
 393 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 394                                    struct i40e_ethertype_filter *filter);
 395
 396 static int i40e_tunnel_filter_convert(
 397         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 398         struct i40e_tunnel_filter *tunnel_filter);
 399 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 400                                 struct i40e_tunnel_filter *tunnel_filter);
 401 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 402
 403 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 404 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 405 static void i40e_filter_restore(struct i40e_pf *pf);
 406 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 407
 408 static const char *const valid_keys[] = {
 409         ETH_I40E_FLOATING_VEB_ARG,
 410         ETH_I40E_FLOATING_VEB_LIST_ARG,
 411         ETH_I40E_SUPPORT_MULTI_DRIVER,
 412         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 413         ETH_I40E_VF_MSG_CFG,
 414         NULL};
 415
 416 static const struct rte_pci_id pci_id_i40e_map[] = {
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .dev_reset                    = i40e_dev_reset,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 481         .tx_queue_release             = i40e_dev_tx_queue_release,
 482         .dev_led_on                   = i40e_dev_led_on,
 483         .dev_led_off                  = i40e_dev_led_off,
 484         .flow_ctrl_get                = i40e_flow_ctrl_get,
 485         .flow_ctrl_set                = i40e_flow_ctrl_set,
 486         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 487         .mac_addr_add                 = i40e_macaddr_add,
 488         .mac_addr_remove              = i40e_macaddr_remove,
 489         .reta_update                  = i40e_dev_rss_reta_update,
 490         .reta_query                   = i40e_dev_rss_reta_query,
 491         .rss_hash_update              = i40e_dev_rss_hash_update,
 492         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 493         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 494         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 495         .flow_ops_get                 = i40e_dev_flow_ops_get,
 496         .rxq_info_get                 = i40e_rxq_info_get,
 497         .txq_info_get                 = i40e_txq_info_get,
 498         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 499         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 500         .timesync_enable              = i40e_timesync_enable,
 501         .timesync_disable             = i40e_timesync_disable,
 502         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 503         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 504         .get_dcb_info                 = i40e_dev_get_dcb_info,
 505         .timesync_adjust_time         = i40e_timesync_adjust_time,
 506         .timesync_read_time           = i40e_timesync_read_time,
 507         .timesync_write_time          = i40e_timesync_write_time,
 508         .get_reg                      = i40e_get_regs,
 509         .get_eeprom_length            = i40e_get_eeprom_length,
 510         .get_eeprom                   = i40e_get_eeprom,
 511         .get_module_info              = i40e_get_module_info,
 512         .get_module_eeprom            = i40e_get_module_eeprom,
 513         .mac_addr_set                 = i40e_set_default_mac_addr,
 514         .mtu_set                      = i40e_dev_mtu_set,
 515         .tm_ops_get                   = i40e_tm_ops_get,
 516         .tx_done_cleanup              = i40e_tx_done_cleanup,
 517         .get_monitor_addr             = i40e_get_monitor_addr,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         int offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"rx_size_error_packets", offsetof(struct i40e_pf, rx_err1) -
 534                                   offsetof(struct i40e_pf, stats)},
 535         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 536         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 537         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 538         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 539 };
 540
 541 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 542                 sizeof(rte_i40e_stats_strings[0]))
 543
 544 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 545         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 546                 tx_dropped_link_down)},
 547         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 548         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 549                 illegal_bytes)},
 550         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 551         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_local_faults)},
 553         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 554                 mac_remote_faults)},
 555         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_length_errors)},
 557         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 558         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 559         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 560         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 561         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 562         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_127)},
 564         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_255)},
 566         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_511)},
 568         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1023)},
 570         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_1522)},
 572         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_big)},
 574         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_undersize)},
 576         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 577                 rx_oversize)},
 578         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 579                 mac_short_packet_dropped)},
 580         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 581                 rx_fragments)},
 582         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 583         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 584         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_127)},
 586         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_255)},
 588         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_511)},
 590         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1023)},
 592         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_1522)},
 594         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_big)},
 596         {"rx_flow_director_atr_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 598         {"rx_flow_director_sb_match_packets",
 599                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 600         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 tx_lpi_status)},
 602         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 603                 rx_lpi_status)},
 604         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 tx_lpi_count)},
 606         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 607                 rx_lpi_count)},
 608 };
 609
 610 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 611                 sizeof(rte_i40e_hw_port_strings[0]))
 612
 613 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 614         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xon_rx)},
 616         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 617                 priority_xoff_rx)},
 618 };
 619
 620 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 621                 sizeof(rte_i40e_rxq_prio_strings[0]))
 622
 623 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 624         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_tx)},
 626         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xoff_tx)},
 628         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 629                 priority_xon_2_xoff)},
 630 };
 631
 632 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 633                 sizeof(rte_i40e_txq_prio_strings[0]))
 634
 635 static int
 636 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 637         struct rte_pci_device *pci_dev)
 638 {
 639         char name[RTE_ETH_NAME_MAX_LEN];
 640         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 641         int i, retval;
 642
 643         if (pci_dev->device.devargs) {
 644                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 645                                 &eth_da);
 646                 if (retval)
 647                         return retval;
 648         }
 649
 650         if (eth_da.nb_representor_ports > 0 &&
 651             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
 652                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
 653                             pci_dev->device.devargs->args);
 654                 return -ENOTSUP;
 655         }
 656
 657         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 658                 sizeof(struct i40e_adapter),
 659                 eth_dev_pci_specific_init, pci_dev,
 660                 eth_i40e_dev_init, NULL);
 661
 662         if (retval || eth_da.nb_representor_ports < 1)
 663                 return retval;
 664
 665         /* probe VF representor ports */
 666         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 667                 pci_dev->device.name);
 668
 669         if (pf_ethdev == NULL)
 670                 return -ENODEV;
 671
 672         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 673                 struct i40e_vf_representor representor = {
 674                         .vf_id = eth_da.representor_ports[i],
 675                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 676                                 pf_ethdev->data->dev_private)->switch_domain_id,
 677                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 678                                 pf_ethdev->data->dev_private)
 679                 };
 680
 681                 /* representor port net_bdf_port */
 682                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 683                         pci_dev->device.name, eth_da.representor_ports[i]);
 684
 685                 retval = rte_eth_dev_create(&pci_dev->device, name,
 686                         sizeof(struct i40e_vf_representor), NULL, NULL,
 687                         i40e_vf_representor_init, &representor);
 688
 689                 if (retval)
 690                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 691                                 "representor %s.", name);
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 698 {
 699         struct rte_eth_dev *ethdev;
 700
 701         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 702         if (!ethdev)
 703                 return 0;
 704
 705         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 706                 return rte_eth_dev_pci_generic_remove(pci_dev,
 707                                         i40e_vf_representor_uninit);
 708         else
 709                 return rte_eth_dev_pci_generic_remove(pci_dev,
 710                                                 eth_i40e_dev_uninit);
 711 }
 712
 713 static struct rte_pci_driver rte_i40e_pmd = {
 714         .id_table = pci_id_i40e_map,
 715         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 716         .probe = eth_i40e_pci_probe,
 717         .remove = eth_i40e_pci_remove,
 718 };
 719
 720 static inline void
 721 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 722                          uint32_t reg_val)
 723 {
 724         uint32_t ori_reg_val;
 725         struct rte_eth_dev_data *dev_data =
 726                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
 727         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
 728
 729         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 730         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 731         if (ori_reg_val != reg_val)
 732                 PMD_DRV_LOG(WARNING,
 733                             "i40e device %s changed global register [0x%08x]."
 734                             " original: 0x%08x, new: 0x%08x",
 735                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 736 }
 737
 738 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 739 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 740 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 741
 742 #ifndef I40E_GLQF_ORT
 743 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 744 #endif
 745 #ifndef I40E_GLQF_PIT
 746 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 747 #endif
 748 #ifndef I40E_GLQF_L3_MAP
 749 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 750 #endif
 751
 752 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 753 {
 754         /*
 755          * Initialize registers for parsing packet type of QinQ
 756          * This should be removed from code once proper
 757          * configuration API is added to avoid configuration conflicts
 758          * between ports of the same device.
 759          */
 760         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 761         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 762 }
 763
 764 static inline void i40e_config_automask(struct i40e_pf *pf)
 765 {
 766         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 767         uint32_t val;
 768
 769         /* INTENA flag is not auto-cleared for interrupt */
 770         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 771         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 772                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 773
 774         /* If support multi-driver, PF will use INT0. */
 775         if (!pf->support_multi_driver)
 776                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 777
 778         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 779 }
 780
 781 static inline void i40e_clear_automask(struct i40e_pf *pf)
 782 {
 783         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 784         uint32_t val;
 785
 786         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 787         val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 788                  I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
 789
 790         if (!pf->support_multi_driver)
 791                 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 792
 793         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 794 }
 795
 796 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 797
 798 /*
 799  * Add a ethertype filter to drop all flow control frames transmitted
 800  * from VSIs.
 801 */
 802 static void
 803 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 804 {
 805         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 806         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 807                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 808                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 809         int ret;
 810
 811         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 812                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 813                                 pf->main_vsi_seid, 0,
 814                                 TRUE, NULL, NULL);
 815         if (ret)
 816                 PMD_INIT_LOG(ERR,
 817                         "Failed to add filter to drop flow control frames from VSIs.");
 818 }
 819
 820 static int
 821 floating_veb_list_handler(__rte_unused const char *key,
 822                           const char *floating_veb_value,
 823                           void *opaque)
 824 {
 825         int idx = 0;
 826         unsigned int count = 0;
 827         char *end = NULL;
 828         int min, max;
 829         bool *vf_floating_veb = opaque;
 830
 831         while (isblank(*floating_veb_value))
 832                 floating_veb_value++;
 833
 834         /* Reset floating VEB configuration for VFs */
 835         for (idx = 0; idx < I40E_MAX_VF; idx++)
 836                 vf_floating_veb[idx] = false;
 837
 838         min = I40E_MAX_VF;
 839         do {
 840                 while (isblank(*floating_veb_value))
 841                         floating_veb_value++;
 842                 if (*floating_veb_value == '\0')
 843                         return -1;
 844                 errno = 0;
 845                 idx = strtoul(floating_veb_value, &end, 10);
 846                 if (errno || end == NULL)
 847                         return -1;
 848                 if (idx < 0)
 849                         return -1;
 850                 while (isblank(*end))
 851                         end++;
 852                 if (*end == '-') {
 853                         min = idx;
 854                 } else if ((*end == ';') || (*end == '\0')) {
 855                         max = idx;
 856                         if (min == I40E_MAX_VF)
 857                                 min = idx;
 858                         if (max >= I40E_MAX_VF)
 859                                 max = I40E_MAX_VF - 1;
 860                         for (idx = min; idx <= max; idx++) {
 861                                 vf_floating_veb[idx] = true;
 862                                 count++;
 863                         }
 864                         min = I40E_MAX_VF;
 865                 } else {
 866                         return -1;
 867                 }
 868                 floating_veb_value = end + 1;
 869         } while (*end != '\0');
 870
 871         if (count == 0)
 872                 return -1;
 873
 874         return 0;
 875 }
 876
 877 static void
 878 config_vf_floating_veb(struct rte_devargs *devargs,
 879                        uint16_t floating_veb,
 880                        bool *vf_floating_veb)
 881 {
 882         struct rte_kvargs *kvlist;
 883         int i;
 884         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 885
 886         if (!floating_veb)
 887                 return;
 888         /* All the VFs attach to the floating VEB by default
 889          * when the floating VEB is enabled.
 890          */
 891         for (i = 0; i < I40E_MAX_VF; i++)
 892                 vf_floating_veb[i] = true;
 893
 894         if (devargs == NULL)
 895                 return;
 896
 897         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 898         if (kvlist == NULL)
 899                 return;
 900
 901         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 902                 rte_kvargs_free(kvlist);
 903                 return;
 904         }
 905         /* When the floating_veb_list parameter exists, all the VFs
 906          * will attach to the legacy VEB firstly, then configure VFs
 907          * to the floating VEB according to the floating_veb_list.
 908          */
 909         if (rte_kvargs_process(kvlist, floating_veb_list,
 910                                floating_veb_list_handler,
 911                                vf_floating_veb) < 0) {
 912                 rte_kvargs_free(kvlist);
 913                 return;
 914         }
 915         rte_kvargs_free(kvlist);
 916 }
 917
 918 static int
 919 i40e_check_floating_handler(__rte_unused const char *key,
 920                             const char *value,
 921                             __rte_unused void *opaque)
 922 {
 923         if (strcmp(value, "1"))
 924                 return -1;
 925
 926         return 0;
 927 }
 928
 929 static int
 930 is_floating_veb_supported(struct rte_devargs *devargs)
 931 {
 932         struct rte_kvargs *kvlist;
 933         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 934
 935         if (devargs == NULL)
 936                 return 0;
 937
 938         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 939         if (kvlist == NULL)
 940                 return 0;
 941
 942         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 943                 rte_kvargs_free(kvlist);
 944                 return 0;
 945         }
 946         /* Floating VEB is enabled when there's key-value:
 947          * enable_floating_veb=1
 948          */
 949         if (rte_kvargs_process(kvlist, floating_veb_key,
 950                                i40e_check_floating_handler, NULL) < 0) {
 951                 rte_kvargs_free(kvlist);
 952                 return 0;
 953         }
 954         rte_kvargs_free(kvlist);
 955
 956         return 1;
 957 }
 958
 959 static void
 960 config_floating_veb(struct rte_eth_dev *dev)
 961 {
 962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 963         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 964         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 965
 966         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 967
 968         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 969                 pf->floating_veb =
 970                         is_floating_veb_supported(pci_dev->device.devargs);
 971                 config_vf_floating_veb(pci_dev->device.devargs,
 972                                        pf->floating_veb,
 973                                        pf->floating_veb_list);
 974         } else {
 975                 pf->floating_veb = false;
 976         }
 977 }
 978
 979 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 980 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 981
 982 static int
 983 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 984 {
 985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 986         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 987         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 988         int ret;
 989
 990         struct rte_hash_parameters ethertype_hash_params = {
 991                 .name = ethertype_hash_name,
 992                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 993                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 994                 .hash_func = rte_hash_crc,
 995                 .hash_func_init_val = 0,
 996                 .socket_id = rte_socket_id(),
 997         };
 998
 999         /* Initialize ethertype filter rule list and hash */
1000         TAILQ_INIT(&ethertype_rule->ethertype_list);
1001         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1002                  "ethertype_%s", dev->device->name);
1003         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
1004         if (!ethertype_rule->hash_table) {
1005                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1006                 return -EINVAL;
1007         }
1008         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1009                                        sizeof(struct i40e_ethertype_filter *) *
1010                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
1011                                        0);
1012         if (!ethertype_rule->hash_map) {
1013                 PMD_INIT_LOG(ERR,
1014                              "Failed to allocate memory for ethertype hash map!");
1015                 ret = -ENOMEM;
1016                 goto err_ethertype_hash_map_alloc;
1017         }
1018
1019         return 0;
1020
1021 err_ethertype_hash_map_alloc:
1022         rte_hash_free(ethertype_rule->hash_table);
1023
1024         return ret;
1025 }
1026
1027 static int
1028 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1029 {
1030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1032         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1033         int ret;
1034
1035         struct rte_hash_parameters tunnel_hash_params = {
1036                 .name = tunnel_hash_name,
1037                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1038                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1039                 .hash_func = rte_hash_crc,
1040                 .hash_func_init_val = 0,
1041                 .socket_id = rte_socket_id(),
1042         };
1043
1044         /* Initialize tunnel filter rule list and hash */
1045         TAILQ_INIT(&tunnel_rule->tunnel_list);
1046         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1047                  "tunnel_%s", dev->device->name);
1048         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1049         if (!tunnel_rule->hash_table) {
1050                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1051                 return -EINVAL;
1052         }
1053         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1054                                     sizeof(struct i40e_tunnel_filter *) *
1055                                     I40E_MAX_TUNNEL_FILTER_NUM,
1056                                     0);
1057         if (!tunnel_rule->hash_map) {
1058                 PMD_INIT_LOG(ERR,
1059                              "Failed to allocate memory for tunnel hash map!");
1060                 ret = -ENOMEM;
1061                 goto err_tunnel_hash_map_alloc;
1062         }
1063
1064         return 0;
1065
1066 err_tunnel_hash_map_alloc:
1067         rte_hash_free(tunnel_rule->hash_table);
1068
1069         return ret;
1070 }
1071
1072 static int
1073 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1074 {
1075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1077         struct i40e_fdir_info *fdir_info = &pf->fdir;
1078         char fdir_hash_name[RTE_HASH_NAMESIZE];
1079         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1080         uint32_t best = hw->func_caps.fd_filters_best_effort;
1081         enum i40e_filter_pctype pctype;
1082         struct rte_bitmap *bmp = NULL;
1083         uint32_t bmp_size;
1084         void *mem = NULL;
1085         uint32_t i = 0;
1086         int ret;
1087
1088         struct rte_hash_parameters fdir_hash_params = {
1089                 .name = fdir_hash_name,
1090                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1091                 .key_len = sizeof(struct i40e_fdir_input),
1092                 .hash_func = rte_hash_crc,
1093                 .hash_func_init_val = 0,
1094                 .socket_id = rte_socket_id(),
1095         };
1096
1097         /* Initialize flow director filter rule list and hash */
1098         TAILQ_INIT(&fdir_info->fdir_list);
1099         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1100                  "fdir_%s", dev->device->name);
1101         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1102         if (!fdir_info->hash_table) {
1103                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1104                 return -EINVAL;
1105         }
1106
1107         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1108                                           sizeof(struct i40e_fdir_filter *) *
1109                                           I40E_MAX_FDIR_FILTER_NUM,
1110                                           0);
1111         if (!fdir_info->hash_map) {
1112                 PMD_INIT_LOG(ERR,
1113                              "Failed to allocate memory for fdir hash map!");
1114                 ret = -ENOMEM;
1115                 goto err_fdir_hash_map_alloc;
1116         }
1117
1118         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1119                         sizeof(struct i40e_fdir_filter) *
1120                         I40E_MAX_FDIR_FILTER_NUM,
1121                         0);
1122
1123         if (!fdir_info->fdir_filter_array) {
1124                 PMD_INIT_LOG(ERR,
1125                              "Failed to allocate memory for fdir filter array!");
1126                 ret = -ENOMEM;
1127                 goto err_fdir_filter_array_alloc;
1128         }
1129
1130         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1131              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
1132                 pf->fdir.flow_count[pctype] = 0;
1133
1134         fdir_info->fdir_space_size = alloc + best;
1135         fdir_info->fdir_actual_cnt = 0;
1136         fdir_info->fdir_guarantee_total_space = alloc;
1137         fdir_info->fdir_guarantee_free_space =
1138                 fdir_info->fdir_guarantee_total_space;
1139
1140         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1141
1142         fdir_info->fdir_flow_pool.pool =
1143                         rte_zmalloc("i40e_fdir_entry",
1144                                 sizeof(struct i40e_fdir_entry) *
1145                                 fdir_info->fdir_space_size,
1146                                 0);
1147
1148         if (!fdir_info->fdir_flow_pool.pool) {
1149                 PMD_INIT_LOG(ERR,
1150                              "Failed to allocate memory for bitmap flow!");
1151                 ret = -ENOMEM;
1152                 goto err_fdir_bitmap_flow_alloc;
1153         }
1154
1155         for (i = 0; i < fdir_info->fdir_space_size; i++)
1156                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1157
1158         bmp_size =
1159                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1160         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1161         if (mem == NULL) {
1162                 PMD_INIT_LOG(ERR,
1163                              "Failed to allocate memory for fdir bitmap!");
1164                 ret = -ENOMEM;
1165                 goto err_fdir_mem_alloc;
1166         }
1167         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1168         if (bmp == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                              "Failed to initialization fdir bitmap!");
1171                 ret = -ENOMEM;
1172                 goto err_fdir_bmp_alloc;
1173         }
1174         for (i = 0; i < fdir_info->fdir_space_size; i++)
1175                 rte_bitmap_set(bmp, i);
1176
1177         fdir_info->fdir_flow_pool.bitmap = bmp;
1178
1179         return 0;
1180
1181 err_fdir_bmp_alloc:
1182         rte_free(mem);
1183 err_fdir_mem_alloc:
1184         rte_free(fdir_info->fdir_flow_pool.pool);
1185 err_fdir_bitmap_flow_alloc:
1186         rte_free(fdir_info->fdir_filter_array);
1187 err_fdir_filter_array_alloc:
1188         rte_free(fdir_info->hash_map);
1189 err_fdir_hash_map_alloc:
1190         rte_hash_free(fdir_info->hash_table);
1191
1192         return ret;
1193 }
1194
1195 static void
1196 i40e_init_customized_info(struct i40e_pf *pf)
1197 {
1198         int i;
1199
1200         /* Initialize customized pctype */
1201         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1202                 pf->customized_pctype[i].index = i;
1203                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1204                 pf->customized_pctype[i].valid = false;
1205         }
1206
1207         pf->gtp_support = false;
1208         pf->esp_support = false;
1209 }
1210
1211 static void
1212 i40e_init_filter_invalidation(struct i40e_pf *pf)
1213 {
1214         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1215         struct i40e_fdir_info *fdir_info = &pf->fdir;
1216         uint32_t glqf_ctl_reg = 0;
1217
1218         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1219         if (!pf->support_multi_driver) {
1220                 fdir_info->fdir_invalprio = 1;
1221                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1222                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1223                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1224         } else {
1225                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1226                         fdir_info->fdir_invalprio = 1;
1227                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1228                 } else {
1229                         fdir_info->fdir_invalprio = 0;
1230                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1231                 }
1232         }
1233 }
1234
1235 void
1236 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1237 {
1238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240         struct i40e_queue_regions *info = &pf->queue_region;
1241         uint16_t i;
1242
1243         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1244                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1245
1246         memset(info, 0, sizeof(struct i40e_queue_regions));
1247 }
1248
1249 static int
1250 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1251                                const char *value,
1252                                void *opaque)
1253 {
1254         struct i40e_pf *pf;
1255         unsigned long support_multi_driver;
1256         char *end;
1257
1258         pf = (struct i40e_pf *)opaque;
1259
1260         errno = 0;
1261         support_multi_driver = strtoul(value, &end, 10);
1262         if (errno != 0 || end == value || *end != 0) {
1263                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1264                 return -(EINVAL);
1265         }
1266
1267         if (support_multi_driver == 1 || support_multi_driver == 0)
1268                 pf->support_multi_driver = (bool)support_multi_driver;
1269         else
1270                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1271                             "enable global configuration by default."
1272                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1273         return 0;
1274 }
1275
1276 static int
1277 i40e_support_multi_driver(struct rte_eth_dev *dev)
1278 {
1279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1280         struct rte_kvargs *kvlist;
1281         int kvargs_count;
1282
1283         /* Enable global configuration by default */
1284         pf->support_multi_driver = false;
1285
1286         if (!dev->device->devargs)
1287                 return 0;
1288
1289         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1290         if (!kvlist)
1291                 return -EINVAL;
1292
1293         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1294         if (!kvargs_count) {
1295                 rte_kvargs_free(kvlist);
1296                 return 0;
1297         }
1298
1299         if (kvargs_count > 1)
1300                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1301                             "the first invalid or last valid one is used !",
1302                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1303
1304         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1305                                i40e_parse_multi_drv_handler, pf) < 0) {
1306                 rte_kvargs_free(kvlist);
1307                 return -EINVAL;
1308         }
1309
1310         rte_kvargs_free(kvlist);
1311         return 0;
1312 }
1313
1314 static int
1315 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1316                                     uint32_t reg_addr, uint64_t reg_val,
1317                                     struct i40e_asq_cmd_details *cmd_details)
1318 {
1319         uint64_t ori_reg_val;
1320         struct rte_eth_dev_data *dev_data =
1321                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
1322         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
1323         int ret;
1324
1325         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1326         if (ret != I40E_SUCCESS) {
1327                 PMD_DRV_LOG(ERR,
1328                             "Fail to debug read from 0x%08x",
1329                             reg_addr);
1330                 return -EIO;
1331         }
1332
1333         if (ori_reg_val != reg_val)
1334                 PMD_DRV_LOG(WARNING,
1335                             "i40e device %s changed global register [0x%08x]."
1336                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1337                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1338
1339         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1340 }
1341
1342 static int
1343 read_vf_msg_config(__rte_unused const char *key,
1344                                const char *value,
1345                                void *opaque)
1346 {
1347         struct i40e_vf_msg_cfg *cfg = opaque;
1348
1349         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1350                         &cfg->ignore_second) != 3) {
1351                 memset(cfg, 0, sizeof(*cfg));
1352                 PMD_DRV_LOG(ERR, "format error! example: "
1353                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1354                 return -EINVAL;
1355         }
1356
1357         /*
1358          * If the message validation function been enabled, the 'period'
1359          * and 'ignore_second' must greater than 0.
1360          */
1361         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1362                 memset(cfg, 0, sizeof(*cfg));
1363                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1364                                 " number must be greater than 0!",
1365                                 ETH_I40E_VF_MSG_CFG);
1366                 return -EINVAL;
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int
1373 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1374                 struct i40e_vf_msg_cfg *msg_cfg)
1375 {
1376         struct rte_kvargs *kvlist;
1377         int kvargs_count;
1378         int ret = 0;
1379
1380         memset(msg_cfg, 0, sizeof(*msg_cfg));
1381
1382         if (!dev->device->devargs)
1383                 return ret;
1384
1385         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1386         if (!kvlist)
1387                 return -EINVAL;
1388
1389         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1390         if (!kvargs_count)
1391                 goto free_end;
1392
1393         if (kvargs_count > 1) {
1394                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1395                                 ETH_I40E_VF_MSG_CFG);
1396                 ret = -EINVAL;
1397                 goto free_end;
1398         }
1399
1400         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1401                         read_vf_msg_config, msg_cfg) < 0)
1402                 ret = -EINVAL;
1403
1404 free_end:
1405         rte_kvargs_free(kvlist);
1406         return ret;
1407 }
1408
1409 #define I40E_ALARM_INTERVAL 50000 /* us */
1410
1411 static int
1412 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1413 {
1414         struct rte_pci_device *pci_dev;
1415         struct rte_intr_handle *intr_handle;
1416         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1417         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418         struct i40e_vsi *vsi;
1419         int ret;
1420         uint32_t len, val;
1421         uint8_t aq_fail = 0;
1422
1423         PMD_INIT_FUNC_TRACE();
1424
1425         dev->dev_ops = &i40e_eth_dev_ops;
1426         dev->rx_queue_count = i40e_dev_rx_queue_count;
1427         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1428         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1429         dev->rx_pkt_burst = i40e_recv_pkts;
1430         dev->tx_pkt_burst = i40e_xmit_pkts;
1431         dev->tx_pkt_prepare = i40e_prep_pkts;
1432
1433         /* for secondary processes, we don't initialise any further as primary
1434          * has already done this work. Only check we don't need a different
1435          * RX function */
1436         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1437                 i40e_set_rx_function(dev);
1438                 i40e_set_tx_function(dev);
1439                 return 0;
1440         }
1441         i40e_set_default_ptype_table(dev);
1442         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1443         intr_handle = pci_dev->intr_handle;
1444
1445         rte_eth_copy_pci_info(dev, pci_dev);
1446
1447         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1448         pf->dev_data = dev->data;
1449
1450         hw->back = I40E_PF_TO_ADAPTER(pf);
1451         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1452         if (!hw->hw_addr) {
1453                 PMD_INIT_LOG(ERR,
1454                         "Hardware is not available, as address is NULL");
1455                 return -ENODEV;
1456         }
1457
1458         hw->vendor_id = pci_dev->id.vendor_id;
1459         hw->device_id = pci_dev->id.device_id;
1460         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1461         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1462         hw->bus.device = pci_dev->addr.devid;
1463         hw->bus.func = pci_dev->addr.function;
1464         hw->adapter_stopped = 0;
1465         hw->adapter_closed = 0;
1466
1467         /* Init switch device pointer */
1468         hw->switch_dev = NULL;
1469
1470         /*
1471          * Switch Tag value should not be identical to either the First Tag
1472          * or Second Tag values. So set something other than common Ethertype
1473          * for internal switching.
1474          */
1475         hw->switch_tag = 0xffff;
1476
1477         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1478         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1479                 PMD_INIT_LOG(ERR, "\nERROR: "
1480                         "Firmware recovery mode detected. Limiting functionality.\n"
1481                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1482                         "User Guide for details on firmware recovery mode.");
1483                 return -EIO;
1484         }
1485
1486         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1487         /* Check if need to support multi-driver */
1488         i40e_support_multi_driver(dev);
1489
1490         /* Make sure all is clean before doing PF reset */
1491         i40e_clear_hw(hw);
1492
1493         /* Reset here to make sure all is clean for each PF */
1494         ret = i40e_pf_reset(hw);
1495         if (ret) {
1496                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1497                 return ret;
1498         }
1499
1500         /* Initialize the shared code (base driver) */
1501         ret = i40e_init_shared_code(hw);
1502         if (ret) {
1503                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1504                 return ret;
1505         }
1506
1507         /* Initialize the parameters for adminq */
1508         i40e_init_adminq_parameter(hw);
1509         ret = i40e_init_adminq(hw);
1510         if (ret != I40E_SUCCESS) {
1511                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1512                 return -EIO;
1513         }
1514         /* Firmware of SFP x722 does not support 802.1ad frames ability */
1515         if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1516                 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1517                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1518
1519         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1520                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1521                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1522                      ((hw->nvm.version >> 12) & 0xf),
1523                      ((hw->nvm.version >> 4) & 0xff),
1524                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1525
1526         /* Initialize the hardware */
1527         i40e_hw_init(dev);
1528
1529         i40e_config_automask(pf);
1530
1531         i40e_set_default_pctype_table(dev);
1532
1533         /*
1534          * To work around the NVM issue, initialize registers
1535          * for packet type of QinQ by software.
1536          * It should be removed once issues are fixed in NVM.
1537          */
1538         if (!pf->support_multi_driver)
1539                 i40e_GLQF_reg_init(hw);
1540
1541         /* Initialize the input set for filters (hash and fd) to default value */
1542         i40e_filter_input_set_init(pf);
1543
1544         /* initialise the L3_MAP register */
1545         if (!pf->support_multi_driver) {
1546                 ret = i40e_aq_debug_write_global_register(hw,
1547                                                    I40E_GLQF_L3_MAP(40),
1548                                                    0x00000028,  NULL);
1549                 if (ret)
1550                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1551                                      ret);
1552                 PMD_INIT_LOG(DEBUG,
1553                              "Global register 0x%08x is changed with 0x28",
1554                              I40E_GLQF_L3_MAP(40));
1555         }
1556
1557         /* Need the special FW version to support floating VEB */
1558         config_floating_veb(dev);
1559         /* Clear PXE mode */
1560         i40e_clear_pxe_mode(hw);
1561         i40e_dev_sync_phy_type(hw);
1562
1563         /*
1564          * On X710, performance number is far from the expectation on recent
1565          * firmware versions. The fix for this issue may not be integrated in
1566          * the following firmware version. So the workaround in software driver
1567          * is needed. It needs to modify the initial values of 3 internal only
1568          * registers. Note that the workaround can be removed when it is fixed
1569          * in firmware in the future.
1570          */
1571         i40e_configure_registers(hw);
1572
1573         /* Get hw capabilities */
1574         ret = i40e_get_cap(hw);
1575         if (ret != I40E_SUCCESS) {
1576                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1577                 goto err_get_capabilities;
1578         }
1579
1580         /* Initialize parameters for PF */
1581         ret = i40e_pf_parameter_init(dev);
1582         if (ret != 0) {
1583                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1584                 goto err_parameter_init;
1585         }
1586
1587         /* Initialize the queue management */
1588         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1589         if (ret < 0) {
1590                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1591                 goto err_qp_pool_init;
1592         }
1593         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1594                                 hw->func_caps.num_msix_vectors - 1);
1595         if (ret < 0) {
1596                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1597                 goto err_msix_pool_init;
1598         }
1599
1600         /* Initialize lan hmc */
1601         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1602                                 hw->func_caps.num_rx_qp, 0, 0);
1603         if (ret != I40E_SUCCESS) {
1604                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1605                 goto err_init_lan_hmc;
1606         }
1607
1608         /* Configure lan hmc */
1609         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1610         if (ret != I40E_SUCCESS) {
1611                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1612                 goto err_configure_lan_hmc;
1613         }
1614
1615         /* Get and check the mac address */
1616         i40e_get_mac_addr(hw, hw->mac.addr);
1617         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1618                 PMD_INIT_LOG(ERR, "mac address is not valid");
1619                 ret = -EIO;
1620                 goto err_get_mac_addr;
1621         }
1622         /* Copy the permanent MAC address */
1623         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1624                         (struct rte_ether_addr *)hw->mac.perm_addr);
1625
1626         /* Disable flow control */
1627         hw->fc.requested_mode = I40E_FC_NONE;
1628         i40e_set_fc(hw, &aq_fail, TRUE);
1629
1630         /* Set the global registers with default ether type value */
1631         if (!pf->support_multi_driver) {
1632                 ret = i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
1633                                          RTE_ETHER_TYPE_VLAN);
1634                 if (ret != I40E_SUCCESS) {
1635                         PMD_INIT_LOG(ERR,
1636                                      "Failed to set the default outer "
1637                                      "VLAN ether type");
1638                         goto err_setup_pf_switch;
1639                 }
1640         }
1641
1642         /* PF setup, which includes VSI setup */
1643         ret = i40e_pf_setup(pf);
1644         if (ret) {
1645                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1646                 goto err_setup_pf_switch;
1647         }
1648
1649         vsi = pf->main_vsi;
1650
1651         /* Disable double vlan by default */
1652         i40e_vsi_config_double_vlan(vsi, FALSE);
1653
1654         /* Disable S-TAG identification when floating_veb is disabled */
1655         if (!pf->floating_veb) {
1656                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1657                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1658                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1659                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1660                 }
1661         }
1662
1663         if (!vsi->max_macaddrs)
1664                 len = RTE_ETHER_ADDR_LEN;
1665         else
1666                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1667
1668         /* Should be after VSI initialized */
1669         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1670         if (!dev->data->mac_addrs) {
1671                 PMD_INIT_LOG(ERR,
1672                         "Failed to allocated memory for storing mac address");
1673                 goto err_mac_alloc;
1674         }
1675         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1676                                         &dev->data->mac_addrs[0]);
1677
1678         /* Init dcb to sw mode by default */
1679         ret = i40e_dcb_init_configure(dev, TRUE);
1680         if (ret != I40E_SUCCESS) {
1681                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1682                 pf->flags &= ~I40E_FLAG_DCB;
1683         }
1684         /* Update HW struct after DCB configuration */
1685         i40e_get_cap(hw);
1686
1687         /* initialize pf host driver to setup SRIOV resource if applicable */
1688         i40e_pf_host_init(dev);
1689
1690         /* register callback func to eal lib */
1691         rte_intr_callback_register(intr_handle,
1692                                    i40e_dev_interrupt_handler, dev);
1693
1694         /* configure and enable device interrupt */
1695         i40e_pf_config_irq0(hw, TRUE);
1696         i40e_pf_enable_irq0(hw);
1697
1698         /* enable uio intr after callback register */
1699         rte_intr_enable(intr_handle);
1700
1701         /* By default disable flexible payload in global configuration */
1702         if (!pf->support_multi_driver)
1703                 i40e_flex_payload_reg_set_default(hw);
1704
1705         /*
1706          * Add an ethertype filter to drop all flow control frames transmitted
1707          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1708          * frames to wire.
1709          */
1710         i40e_add_tx_flow_control_drop_filter(pf);
1711
1712         /* Set the max frame size to 0x2600 by default,
1713          * in case other drivers changed the default value.
1714          */
1715         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1716
1717         /* initialize RSS rule list */
1718         TAILQ_INIT(&pf->rss_config_list);
1719
1720         /* initialize Traffic Manager configuration */
1721         i40e_tm_conf_init(dev);
1722
1723         /* Initialize customized information */
1724         i40e_init_customized_info(pf);
1725
1726         /* Initialize the filter invalidation configuration */
1727         i40e_init_filter_invalidation(pf);
1728
1729         ret = i40e_init_ethtype_filter_list(dev);
1730         if (ret < 0)
1731                 goto err_init_ethtype_filter_list;
1732         ret = i40e_init_tunnel_filter_list(dev);
1733         if (ret < 0)
1734                 goto err_init_tunnel_filter_list;
1735         ret = i40e_init_fdir_filter_list(dev);
1736         if (ret < 0)
1737                 goto err_init_fdir_filter_list;
1738
1739         /* initialize queue region configuration */
1740         i40e_init_queue_region_conf(dev);
1741
1742         /* reset all stats of the device, including pf and main vsi */
1743         i40e_dev_stats_reset(dev);
1744
1745         return 0;
1746
1747 err_init_fdir_filter_list:
1748         rte_hash_free(pf->tunnel.hash_table);
1749         rte_free(pf->tunnel.hash_map);
1750 err_init_tunnel_filter_list:
1751         rte_hash_free(pf->ethertype.hash_table);
1752         rte_free(pf->ethertype.hash_map);
1753 err_init_ethtype_filter_list:
1754         rte_intr_callback_unregister(intr_handle,
1755                 i40e_dev_interrupt_handler, dev);
1756         rte_free(dev->data->mac_addrs);
1757         dev->data->mac_addrs = NULL;
1758 err_mac_alloc:
1759         i40e_vsi_release(pf->main_vsi);
1760 err_setup_pf_switch:
1761 err_get_mac_addr:
1762 err_configure_lan_hmc:
1763         (void)i40e_shutdown_lan_hmc(hw);
1764 err_init_lan_hmc:
1765         i40e_res_pool_destroy(&pf->msix_pool);
1766 err_msix_pool_init:
1767         i40e_res_pool_destroy(&pf->qp_pool);
1768 err_qp_pool_init:
1769 err_parameter_init:
1770 err_get_capabilities:
1771         (void)i40e_shutdown_adminq(hw);
1772
1773         return ret;
1774 }
1775
1776 static void
1777 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1778 {
1779         struct i40e_ethertype_filter *p_ethertype;
1780         struct i40e_ethertype_rule *ethertype_rule;
1781
1782         ethertype_rule = &pf->ethertype;
1783         /* Remove all ethertype filter rules and hash */
1784         if (ethertype_rule->hash_map)
1785                 rte_free(ethertype_rule->hash_map);
1786         if (ethertype_rule->hash_table)
1787                 rte_hash_free(ethertype_rule->hash_table);
1788
1789         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1790                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1791                              p_ethertype, rules);
1792                 rte_free(p_ethertype);
1793         }
1794 }
1795
1796 static void
1797 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1798 {
1799         struct i40e_tunnel_filter *p_tunnel;
1800         struct i40e_tunnel_rule *tunnel_rule;
1801
1802         tunnel_rule = &pf->tunnel;
1803         /* Remove all tunnel director rules and hash */
1804         if (tunnel_rule->hash_map)
1805                 rte_free(tunnel_rule->hash_map);
1806         if (tunnel_rule->hash_table)
1807                 rte_hash_free(tunnel_rule->hash_table);
1808
1809         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1810                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1811                 rte_free(p_tunnel);
1812         }
1813 }
1814
1815 static void
1816 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1817 {
1818         struct i40e_fdir_filter *p_fdir;
1819         struct i40e_fdir_info *fdir_info;
1820
1821         fdir_info = &pf->fdir;
1822
1823         /* Remove all flow director rules */
1824         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1825                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1826 }
1827
1828 static void
1829 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1830 {
1831         struct i40e_fdir_info *fdir_info;
1832
1833         fdir_info = &pf->fdir;
1834
1835         /* flow director memory cleanup */
1836         if (fdir_info->hash_map)
1837                 rte_free(fdir_info->hash_map);
1838         if (fdir_info->hash_table)
1839                 rte_hash_free(fdir_info->hash_table);
1840         if (fdir_info->fdir_flow_pool.bitmap)
1841                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1842         if (fdir_info->fdir_flow_pool.pool)
1843                 rte_free(fdir_info->fdir_flow_pool.pool);
1844         if (fdir_info->fdir_filter_array)
1845                 rte_free(fdir_info->fdir_filter_array);
1846 }
1847
1848 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1849 {
1850         /*
1851          * Disable by default flexible payload
1852          * for corresponding L2/L3/L4 layers.
1853          */
1854         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1855         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1856         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1857 }
1858
1859 static int
1860 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1861 {
1862         struct i40e_hw *hw;
1863
1864         PMD_INIT_FUNC_TRACE();
1865
1866         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1867                 return 0;
1868
1869         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870
1871         if (hw->adapter_closed == 0)
1872                 i40e_dev_close(dev);
1873
1874         return 0;
1875 }
1876
1877 static int
1878 i40e_dev_configure(struct rte_eth_dev *dev)
1879 {
1880         struct i40e_adapter *ad =
1881                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1885         int i, ret;
1886
1887         ret = i40e_dev_sync_phy_type(hw);
1888         if (ret)
1889                 return ret;
1890
1891         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1892          * bulk allocation or vector Rx preconditions we will reset it.
1893          */
1894         ad->rx_bulk_alloc_allowed = true;
1895         ad->rx_vec_allowed = true;
1896         ad->tx_simple_allowed = true;
1897         ad->tx_vec_allowed = true;
1898
1899         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1900                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1901
1902         /* Only legacy filter API needs the following fdir config. So when the
1903          * legacy filter API is deprecated, the following codes should also be
1904          * removed.
1905          */
1906         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1907                 ret = i40e_fdir_setup(pf);
1908                 if (ret != I40E_SUCCESS) {
1909                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1910                         return -ENOTSUP;
1911                 }
1912                 ret = i40e_fdir_configure(dev);
1913                 if (ret < 0) {
1914                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1915                         goto err;
1916                 }
1917         } else
1918                 i40e_fdir_teardown(pf);
1919
1920         ret = i40e_dev_init_vlan(dev);
1921         if (ret < 0)
1922                 goto err;
1923
1924         /* VMDQ setup.
1925          *  General PMD driver call sequence are NIC init, configure,
1926          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1927          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1928          *  applicable. So, VMDQ setting has to be done before
1929          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1930          *  For RSS setting, it will try to calculate actual configured RX queue
1931          *  number, which will be available after rx_queue_setup(). dev_start()
1932          *  function is good to place RSS setup.
1933          */
1934         if (mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) {
1935                 ret = i40e_vmdq_setup(dev);
1936                 if (ret)
1937                         goto err;
1938         }
1939
1940         if (mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
1941                 ret = i40e_dcb_setup(dev);
1942                 if (ret) {
1943                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1944                         goto err_dcb;
1945                 }
1946         }
1947
1948         TAILQ_INIT(&pf->flow_list);
1949
1950         return 0;
1951
1952 err_dcb:
1953         /* need to release vmdq resource if exists */
1954         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955                 i40e_vsi_release(pf->vmdq[i].vsi);
1956                 pf->vmdq[i].vsi = NULL;
1957         }
1958         rte_free(pf->vmdq);
1959         pf->vmdq = NULL;
1960 err:
1961         /* Need to release fdir resource if exists.
1962          * Only legacy filter API needs the following fdir config. So when the
1963          * legacy filter API is deprecated, the following code should also be
1964          * removed.
1965          */
1966         i40e_fdir_teardown(pf);
1967         return ret;
1968 }
1969
1970 void
1971 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1972 {
1973         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
1974         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1975         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1976         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1977         uint16_t msix_vect = vsi->msix_intr;
1978         uint16_t i;
1979
1980         for (i = 0; i < vsi->nb_qps; i++) {
1981                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1982                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1983                 rte_wmb();
1984         }
1985
1986         if (vsi->type != I40E_VSI_SRIOV) {
1987                 if (!rte_intr_allow_others(intr_handle)) {
1988                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1989                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1990                         I40E_WRITE_REG(hw,
1991                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1992                                        0);
1993                 } else {
1994                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1995                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1996                         I40E_WRITE_REG(hw,
1997                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1998                                                        msix_vect - 1), 0);
1999                 }
2000         } else {
2001                 uint32_t reg;
2002                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2003                         vsi->user_param + (msix_vect - 1);
2004
2005                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2006                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2007         }
2008         I40E_WRITE_FLUSH(hw);
2009 }
2010
2011 static void
2012 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2013                        int base_queue, int nb_queue,
2014                        uint16_t itr_idx)
2015 {
2016         int i;
2017         uint32_t val;
2018         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2019         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2020
2021         /* Bind all RX queues to allocated MSIX interrupt */
2022         for (i = 0; i < nb_queue; i++) {
2023                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2024                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2025                         ((base_queue + i + 1) <<
2026                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2027                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2028                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2029
2030                 if (i == nb_queue - 1)
2031                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2032                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2033         }
2034
2035         /* Write first RX queue to Link list register as the head element */
2036         if (vsi->type != I40E_VSI_SRIOV) {
2037                 uint16_t interval =
2038                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2039
2040                 if (msix_vect == I40E_MISC_VEC_ID) {
2041                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2042                                        (base_queue <<
2043                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2044                                        (0x0 <<
2045                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2046                         I40E_WRITE_REG(hw,
2047                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2048                                        interval);
2049                 } else {
2050                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2051                                        (base_queue <<
2052                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2053                                        (0x0 <<
2054                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2055                         I40E_WRITE_REG(hw,
2056                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2057                                                        msix_vect - 1),
2058                                        interval);
2059                 }
2060         } else {
2061                 uint32_t reg;
2062
2063                 if (msix_vect == I40E_MISC_VEC_ID) {
2064                         I40E_WRITE_REG(hw,
2065                                        I40E_VPINT_LNKLST0(vsi->user_param),
2066                                        (base_queue <<
2067                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2068                                        (0x0 <<
2069                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2070                 } else {
2071                         /* num_msix_vectors_vf needs to minus irq0 */
2072                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2073                                 vsi->user_param + (msix_vect - 1);
2074
2075                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2076                                        (base_queue <<
2077                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2078                                        (0x0 <<
2079                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2080                 }
2081         }
2082
2083         I40E_WRITE_FLUSH(hw);
2084 }
2085
2086 int
2087 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2088 {
2089         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2090         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2091         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2092         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2093         uint16_t msix_vect = vsi->msix_intr;
2094         uint16_t nb_msix = RTE_MIN(vsi->nb_msix,
2095                                    rte_intr_nb_efd_get(intr_handle));
2096         uint16_t queue_idx = 0;
2097         int record = 0;
2098         int i;
2099
2100         for (i = 0; i < vsi->nb_qps; i++) {
2101                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2102                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2103         }
2104
2105         /* VF bind interrupt */
2106         if (vsi->type == I40E_VSI_SRIOV) {
2107                 if (vsi->nb_msix == 0) {
2108                         PMD_DRV_LOG(ERR, "No msix resource");
2109                         return -EINVAL;
2110                 }
2111                 __vsi_queues_bind_intr(vsi, msix_vect,
2112                                        vsi->base_queue, vsi->nb_qps,
2113                                        itr_idx);
2114                 return 0;
2115         }
2116
2117         /* PF & VMDq bind interrupt */
2118         if (rte_intr_dp_is_en(intr_handle)) {
2119                 if (vsi->type == I40E_VSI_MAIN) {
2120                         queue_idx = 0;
2121                         record = 1;
2122                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2123                         struct i40e_vsi *main_vsi =
2124                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2125                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2126                         record = 1;
2127                 }
2128         }
2129
2130         for (i = 0; i < vsi->nb_used_qps; i++) {
2131                 if (vsi->nb_msix == 0) {
2132                         PMD_DRV_LOG(ERR, "No msix resource");
2133                         return -EINVAL;
2134                 } else if (nb_msix <= 1) {
2135                         if (!rte_intr_allow_others(intr_handle))
2136                                 /* allow to share MISC_VEC_ID */
2137                                 msix_vect = I40E_MISC_VEC_ID;
2138
2139                         /* no enough msix_vect, map all to one */
2140                         __vsi_queues_bind_intr(vsi, msix_vect,
2141                                                vsi->base_queue + i,
2142                                                vsi->nb_used_qps - i,
2143                                                itr_idx);
2144                         for (; !!record && i < vsi->nb_used_qps; i++)
2145                                 rte_intr_vec_list_index_set(intr_handle,
2146                                                 queue_idx + i, msix_vect);
2147                         break;
2148                 }
2149                 /* 1:1 queue/msix_vect mapping */
2150                 __vsi_queues_bind_intr(vsi, msix_vect,
2151                                        vsi->base_queue + i, 1,
2152                                        itr_idx);
2153                 if (!!record)
2154                         if (rte_intr_vec_list_index_set(intr_handle,
2155                                                 queue_idx + i, msix_vect))
2156                                 return -rte_errno;
2157
2158                 msix_vect++;
2159                 nb_msix--;
2160         }
2161
2162         return 0;
2163 }
2164
2165 void
2166 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2167 {
2168         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2169         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2170         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2171         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2172         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2173         uint16_t msix_intr, i;
2174
2175         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2176                 for (i = 0; i < vsi->nb_msix; i++) {
2177                         msix_intr = vsi->msix_intr + i;
2178                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2179                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2180                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2181                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2182                 }
2183         else
2184                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2185                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2186                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2187                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2188
2189         I40E_WRITE_FLUSH(hw);
2190 }
2191
2192 void
2193 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2194 {
2195         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2196         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2197         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2198         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2199         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2200         uint16_t msix_intr, i;
2201
2202         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2203                 for (i = 0; i < vsi->nb_msix; i++) {
2204                         msix_intr = vsi->msix_intr + i;
2205                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2206                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2207                 }
2208         else
2209                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2210                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2211
2212         I40E_WRITE_FLUSH(hw);
2213 }
2214
2215 static inline uint8_t
2216 i40e_parse_link_speeds(uint16_t link_speeds)
2217 {
2218         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2219
2220         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
2221                 link_speed |= I40E_LINK_SPEED_40GB;
2222         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
2223                 link_speed |= I40E_LINK_SPEED_25GB;
2224         if (link_speeds & RTE_ETH_LINK_SPEED_20G)
2225                 link_speed |= I40E_LINK_SPEED_20GB;
2226         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
2227                 link_speed |= I40E_LINK_SPEED_10GB;
2228         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
2229                 link_speed |= I40E_LINK_SPEED_1GB;
2230         if (link_speeds & RTE_ETH_LINK_SPEED_100M)
2231                 link_speed |= I40E_LINK_SPEED_100MB;
2232
2233         return link_speed;
2234 }
2235
2236 static int
2237 i40e_phy_conf_link(struct i40e_hw *hw,
2238                    uint8_t abilities,
2239                    uint8_t force_speed,
2240                    bool is_up)
2241 {
2242         enum i40e_status_code status;
2243         struct i40e_aq_get_phy_abilities_resp phy_ab;
2244         struct i40e_aq_set_phy_config phy_conf;
2245         enum i40e_aq_phy_type cnt;
2246         uint8_t avail_speed;
2247         uint32_t phy_type_mask = 0;
2248
2249         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2250                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2251                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2252                         I40E_AQ_PHY_FLAG_LOW_POWER;
2253         int ret = -ENOTSUP;
2254
2255         /* To get phy capabilities of available speeds. */
2256         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2257                                               NULL);
2258         if (status) {
2259                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2260                                 status);
2261                 return ret;
2262         }
2263         avail_speed = phy_ab.link_speed;
2264
2265         /* To get the current phy config. */
2266         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2267                                               NULL);
2268         if (status) {
2269                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2270                                 status);
2271                 return ret;
2272         }
2273
2274         /* If link needs to go up and it is in autoneg mode the speed is OK,
2275          * no need to set up again.
2276          */
2277         if (is_up && phy_ab.phy_type != 0 &&
2278                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2279                      phy_ab.link_speed != 0)
2280                 return I40E_SUCCESS;
2281
2282         memset(&phy_conf, 0, sizeof(phy_conf));
2283
2284         /* bits 0-2 use the values from get_phy_abilities_resp */
2285         abilities &= ~mask;
2286         abilities |= phy_ab.abilities & mask;
2287
2288         phy_conf.abilities = abilities;
2289
2290         /* If link needs to go up, but the force speed is not supported,
2291          * Warn users and config the default available speeds.
2292          */
2293         if (is_up && !(force_speed & avail_speed)) {
2294                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2295                 phy_conf.link_speed = avail_speed;
2296         } else {
2297                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2298         }
2299
2300         /* PHY type mask needs to include each type except PHY type extension */
2301         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2302                 phy_type_mask |= 1 << cnt;
2303
2304         /* use get_phy_abilities_resp value for the rest */
2305         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2306         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2307                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2308                 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2309                 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2310         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2311         phy_conf.eee_capability = phy_ab.eee_capability;
2312         phy_conf.eeer = phy_ab.eeer_val;
2313         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2314
2315         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2316                     phy_ab.abilities, phy_ab.link_speed);
2317         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2318                     phy_conf.abilities, phy_conf.link_speed);
2319
2320         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2321         if (status)
2322                 return ret;
2323
2324         return I40E_SUCCESS;
2325 }
2326
2327 static int
2328 i40e_apply_link_speed(struct rte_eth_dev *dev)
2329 {
2330         uint8_t speed;
2331         uint8_t abilities = 0;
2332         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333         struct rte_eth_conf *conf = &dev->data->dev_conf;
2334
2335         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2336                      I40E_AQ_PHY_LINK_ENABLED;
2337
2338         if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
2339                 conf->link_speeds = RTE_ETH_LINK_SPEED_40G |
2340                                     RTE_ETH_LINK_SPEED_25G |
2341                                     RTE_ETH_LINK_SPEED_20G |
2342                                     RTE_ETH_LINK_SPEED_10G |
2343                                     RTE_ETH_LINK_SPEED_1G |
2344                                     RTE_ETH_LINK_SPEED_100M;
2345
2346                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2347         } else {
2348                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2349         }
2350         speed = i40e_parse_link_speeds(conf->link_speeds);
2351
2352         return i40e_phy_conf_link(hw, abilities, speed, true);
2353 }
2354
2355 static int
2356 i40e_dev_start(struct rte_eth_dev *dev)
2357 {
2358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360         struct i40e_vsi *main_vsi = pf->main_vsi;
2361         int ret, i;
2362         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2363         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2364         uint32_t intr_vector = 0;
2365         struct i40e_vsi *vsi;
2366         uint16_t nb_rxq, nb_txq;
2367
2368         hw->adapter_stopped = 0;
2369
2370         rte_intr_disable(intr_handle);
2371
2372         if ((rte_intr_cap_multiple(intr_handle) ||
2373              !RTE_ETH_DEV_SRIOV(dev).active) &&
2374             dev->data->dev_conf.intr_conf.rxq != 0) {
2375                 intr_vector = dev->data->nb_rx_queues;
2376                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2377                 if (ret)
2378                         return ret;
2379         }
2380
2381         if (rte_intr_dp_is_en(intr_handle)) {
2382                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2383                                                    dev->data->nb_rx_queues)) {
2384                         PMD_INIT_LOG(ERR,
2385                                 "Failed to allocate %d rx_queues intr_vec",
2386                                 dev->data->nb_rx_queues);
2387                         return -ENOMEM;
2388                 }
2389         }
2390
2391         /* Initialize VSI */
2392         ret = i40e_dev_rxtx_init(pf);
2393         if (ret != I40E_SUCCESS) {
2394                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2395                 return ret;
2396         }
2397
2398         /* Map queues with MSIX interrupt */
2399         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2400                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2401         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2402         if (ret < 0)
2403                 return ret;
2404         i40e_vsi_enable_queues_intr(main_vsi);
2405
2406         /* Map VMDQ VSI queues with MSIX interrupt */
2407         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2408                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2409                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2410                                                 I40E_ITR_INDEX_DEFAULT);
2411                 if (ret < 0)
2412                         return ret;
2413                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2414         }
2415
2416         /* Enable all queues which have been configured */
2417         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2418                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2419                 if (ret)
2420                         goto rx_err;
2421         }
2422
2423         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2424                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2425                 if (ret)
2426                         goto tx_err;
2427         }
2428
2429         /* Enable receiving broadcast packets */
2430         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2431         if (ret != I40E_SUCCESS)
2432                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2433
2434         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2435                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2436                                                 true, NULL);
2437                 if (ret != I40E_SUCCESS)
2438                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2439         }
2440
2441         /* Enable the VLAN promiscuous mode. */
2442         if (pf->vfs) {
2443                 for (i = 0; i < pf->vf_num; i++) {
2444                         vsi = pf->vfs[i].vsi;
2445                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2446                                                      true, NULL);
2447                 }
2448         }
2449
2450         /* Enable mac loopback mode */
2451         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2452             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2453                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2454                 if (ret != I40E_SUCCESS) {
2455                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2456                         goto tx_err;
2457                 }
2458         }
2459
2460         /* Apply link configure */
2461         ret = i40e_apply_link_speed(dev);
2462         if (I40E_SUCCESS != ret) {
2463                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2464                 goto tx_err;
2465         }
2466
2467         if (!rte_intr_allow_others(intr_handle)) {
2468                 rte_intr_callback_unregister(intr_handle,
2469                                              i40e_dev_interrupt_handler,
2470                                              (void *)dev);
2471                 /* configure and enable device interrupt */
2472                 i40e_pf_config_irq0(hw, FALSE);
2473                 i40e_pf_enable_irq0(hw);
2474
2475                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2476                         PMD_INIT_LOG(INFO,
2477                                 "lsc won't enable because of no intr multiplex");
2478         } else {
2479                 ret = i40e_aq_set_phy_int_mask(hw,
2480                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2481                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2482                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2483                 if (ret != I40E_SUCCESS)
2484                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2485
2486                 /* Call get_link_info aq commond to enable/disable LSE */
2487                 i40e_dev_link_update(dev, 0);
2488         }
2489
2490         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2491                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2492                                   i40e_dev_alarm_handler, dev);
2493         } else {
2494                 /* enable uio intr after callback register */
2495                 rte_intr_enable(intr_handle);
2496         }
2497
2498         i40e_filter_restore(pf);
2499
2500         if (pf->tm_conf.root && !pf->tm_conf.committed)
2501                 PMD_DRV_LOG(WARNING,
2502                             "please call hierarchy_commit() "
2503                             "before starting the port");
2504
2505         return I40E_SUCCESS;
2506
2507 tx_err:
2508         for (i = 0; i < nb_txq; i++)
2509                 i40e_dev_tx_queue_stop(dev, i);
2510 rx_err:
2511         for (i = 0; i < nb_rxq; i++)
2512                 i40e_dev_rx_queue_stop(dev, i);
2513
2514         return ret;
2515 }
2516
2517 static int
2518 i40e_dev_stop(struct rte_eth_dev *dev)
2519 {
2520         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522         struct i40e_vsi *main_vsi = pf->main_vsi;
2523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2524         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2525         int i;
2526
2527         if (hw->adapter_stopped == 1)
2528                 return 0;
2529
2530         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2531                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2532                 rte_intr_enable(intr_handle);
2533         }
2534
2535         /* Disable all queues */
2536         for (i = 0; i < dev->data->nb_tx_queues; i++)
2537                 i40e_dev_tx_queue_stop(dev, i);
2538
2539         for (i = 0; i < dev->data->nb_rx_queues; i++)
2540                 i40e_dev_rx_queue_stop(dev, i);
2541
2542         /* un-map queues with interrupt registers */
2543         i40e_vsi_disable_queues_intr(main_vsi);
2544         i40e_vsi_queues_unbind_intr(main_vsi);
2545
2546         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2547                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2548                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2549         }
2550
2551         /* Clear all queues and release memory */
2552         i40e_dev_clear_queues(dev);
2553
2554         /* Set link down */
2555         i40e_dev_set_link_down(dev);
2556
2557         if (!rte_intr_allow_others(intr_handle))
2558                 /* resume to the default handler */
2559                 rte_intr_callback_register(intr_handle,
2560                                            i40e_dev_interrupt_handler,
2561                                            (void *)dev);
2562
2563         /* Clean datapath event and queue/vec mapping */
2564         rte_intr_efd_disable(intr_handle);
2565
2566         /* Cleanup vector list */
2567         rte_intr_vec_list_free(intr_handle);
2568
2569         /* reset hierarchy commit */
2570         pf->tm_conf.committed = false;
2571
2572         hw->adapter_stopped = 1;
2573         dev->data->dev_started = 0;
2574
2575         pf->adapter->rss_reta_updated = 0;
2576
2577         return 0;
2578 }
2579
2580 static int
2581 i40e_dev_close(struct rte_eth_dev *dev)
2582 {
2583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2586         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2587         struct i40e_filter_control_settings settings;
2588         struct rte_flow *p_flow;
2589         uint32_t reg;
2590         int i;
2591         int ret;
2592         uint8_t aq_fail = 0;
2593         int retries = 0;
2594
2595         PMD_INIT_FUNC_TRACE();
2596         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2597                 return 0;
2598
2599         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2600         if (ret)
2601                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2602
2603
2604         ret = i40e_dev_stop(dev);
2605
2606         i40e_dev_free_queues(dev);
2607
2608         /* Disable interrupt */
2609         i40e_pf_disable_irq0(hw);
2610         rte_intr_disable(intr_handle);
2611
2612         /*
2613          * Only legacy filter API needs the following fdir config. So when the
2614          * legacy filter API is deprecated, the following code should also be
2615          * removed.
2616          */
2617         i40e_fdir_teardown(pf);
2618
2619         /* shutdown and destroy the HMC */
2620         i40e_shutdown_lan_hmc(hw);
2621
2622         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2623                 i40e_vsi_release(pf->vmdq[i].vsi);
2624                 pf->vmdq[i].vsi = NULL;
2625         }
2626         rte_free(pf->vmdq);
2627         pf->vmdq = NULL;
2628
2629         /* release all the existing VSIs and VEBs */
2630         i40e_vsi_release(pf->main_vsi);
2631
2632         /* shutdown the adminq */
2633         i40e_aq_queue_shutdown(hw, true);
2634         i40e_shutdown_adminq(hw);
2635
2636         i40e_res_pool_destroy(&pf->qp_pool);
2637         i40e_res_pool_destroy(&pf->msix_pool);
2638
2639         /* Disable flexible payload in global configuration */
2640         if (!pf->support_multi_driver)
2641                 i40e_flex_payload_reg_set_default(hw);
2642
2643         /* force a PF reset to clean anything leftover */
2644         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2645         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2646                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2647         I40E_WRITE_FLUSH(hw);
2648
2649         /* Clear PXE mode */
2650         i40e_clear_pxe_mode(hw);
2651
2652         /* Unconfigure filter control */
2653         memset(&settings, 0, sizeof(settings));
2654         ret = i40e_set_filter_control(hw, &settings);
2655         if (ret)
2656                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2657                                         ret);
2658
2659         /* Disable flow control */
2660         hw->fc.requested_mode = I40E_FC_NONE;
2661         i40e_set_fc(hw, &aq_fail, TRUE);
2662
2663         /* uninitialize pf host driver */
2664         i40e_pf_host_uninit(dev);
2665
2666         do {
2667                 ret = rte_intr_callback_unregister(intr_handle,
2668                                 i40e_dev_interrupt_handler, dev);
2669                 if (ret >= 0 || ret == -ENOENT) {
2670                         break;
2671                 } else if (ret != -EAGAIN) {
2672                         PMD_INIT_LOG(ERR,
2673                                  "intr callback unregister failed: %d",
2674                                  ret);
2675                 }
2676                 i40e_msec_delay(500);
2677         } while (retries++ < 5);
2678
2679         i40e_rm_ethtype_filter_list(pf);
2680         i40e_rm_tunnel_filter_list(pf);
2681         i40e_rm_fdir_filter_list(pf);
2682
2683         /* Remove all flows */
2684         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2685                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2686                 /* Do not free FDIR flows since they are static allocated */
2687                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2688                         rte_free(p_flow);
2689         }
2690
2691         /* release the fdir static allocated memory */
2692         i40e_fdir_memory_cleanup(pf);
2693
2694         /* Remove all Traffic Manager configuration */
2695         i40e_tm_conf_uninit(dev);
2696
2697         i40e_clear_automask(pf);
2698
2699         hw->adapter_closed = 1;
2700         return ret;
2701 }
2702
2703 /*
2704  * Reset PF device only to re-initialize resources in PMD layer
2705  */
2706 static int
2707 i40e_dev_reset(struct rte_eth_dev *dev)
2708 {
2709         int ret;
2710
2711         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2712          * its VF to make them align with it. The detailed notification
2713          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2714          * To avoid unexpected behavior in VF, currently reset of PF with
2715          * SR-IOV activation is not supported. It might be supported later.
2716          */
2717         if (dev->data->sriov.active)
2718                 return -ENOTSUP;
2719
2720         ret = eth_i40e_dev_uninit(dev);
2721         if (ret)
2722                 return ret;
2723
2724         ret = eth_i40e_dev_init(dev, NULL);
2725
2726         return ret;
2727 }
2728
2729 static int
2730 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2731 {
2732         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734         struct i40e_vsi *vsi = pf->main_vsi;
2735         int status;
2736
2737         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2738                                                      true, NULL, true);
2739         if (status != I40E_SUCCESS) {
2740                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2741                 return -EAGAIN;
2742         }
2743
2744         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2745                                                         TRUE, NULL);
2746         if (status != I40E_SUCCESS) {
2747                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2748                 /* Rollback unicast promiscuous mode */
2749                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2750                                                     false, NULL, true);
2751                 return -EAGAIN;
2752         }
2753
2754         return 0;
2755 }
2756
2757 static int
2758 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2759 {
2760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762         struct i40e_vsi *vsi = pf->main_vsi;
2763         int status;
2764
2765         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2766                                                      false, NULL, true);
2767         if (status != I40E_SUCCESS) {
2768                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2769                 return -EAGAIN;
2770         }
2771
2772         /* must remain in all_multicast mode */
2773         if (dev->data->all_multicast == 1)
2774                 return 0;
2775
2776         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2777                                                         false, NULL);
2778         if (status != I40E_SUCCESS) {
2779                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2780                 /* Rollback unicast promiscuous mode */
2781                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2782                                                     true, NULL, true);
2783                 return -EAGAIN;
2784         }
2785
2786         return 0;
2787 }
2788
2789 static int
2790 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2791 {
2792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         struct i40e_vsi *vsi = pf->main_vsi;
2795         int ret;
2796
2797         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2798         if (ret != I40E_SUCCESS) {
2799                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2800                 return -EAGAIN;
2801         }
2802
2803         return 0;
2804 }
2805
2806 static int
2807 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2808 {
2809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         struct i40e_vsi *vsi = pf->main_vsi;
2812         int ret;
2813
2814         if (dev->data->promiscuous == 1)
2815                 return 0; /* must remain in all_multicast mode */
2816
2817         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2818                                 vsi->seid, FALSE, NULL);
2819         if (ret != I40E_SUCCESS) {
2820                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2821                 return -EAGAIN;
2822         }
2823
2824         return 0;
2825 }
2826
2827 /*
2828  * Set device link up.
2829  */
2830 static int
2831 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2832 {
2833         /* re-apply link speed setting */
2834         return i40e_apply_link_speed(dev);
2835 }
2836
2837 /*
2838  * Set device link down.
2839  */
2840 static int
2841 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2842 {
2843         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2844         uint8_t abilities = 0;
2845         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846
2847         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2848         return i40e_phy_conf_link(hw, abilities, speed, false);
2849 }
2850
2851 static __rte_always_inline void
2852 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2853 {
2854 /* Link status registers and values*/
2855 #define I40E_REG_LINK_UP                0x40000080
2856 #define I40E_PRTMAC_MACC                0x001E24E0
2857 #define I40E_REG_MACC_25GB              0x00020000
2858 #define I40E_REG_SPEED_MASK             0x38000000
2859 #define I40E_REG_SPEED_0                0x00000000
2860 #define I40E_REG_SPEED_1                0x08000000
2861 #define I40E_REG_SPEED_2                0x10000000
2862 #define I40E_REG_SPEED_3                0x18000000
2863 #define I40E_REG_SPEED_4                0x20000000
2864         uint32_t link_speed;
2865         uint32_t reg_val;
2866
2867         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA(0));
2868         link_speed = reg_val & I40E_REG_SPEED_MASK;
2869         reg_val &= I40E_REG_LINK_UP;
2870         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2871
2872         if (unlikely(link->link_status == 0))
2873                 return;
2874
2875         /* Parse the link status */
2876         switch (link_speed) {
2877         case I40E_REG_SPEED_0:
2878                 link->link_speed = RTE_ETH_SPEED_NUM_100M;
2879                 break;
2880         case I40E_REG_SPEED_1:
2881                 link->link_speed = RTE_ETH_SPEED_NUM_1G;
2882                 break;
2883         case I40E_REG_SPEED_2:
2884                 if (hw->mac.type == I40E_MAC_X722)
2885                         link->link_speed = RTE_ETH_SPEED_NUM_2_5G;
2886                 else
2887                         link->link_speed = RTE_ETH_SPEED_NUM_10G;
2888                 break;
2889         case I40E_REG_SPEED_3:
2890                 if (hw->mac.type == I40E_MAC_X722) {
2891                         link->link_speed = RTE_ETH_SPEED_NUM_5G;
2892                 } else {
2893                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2894
2895                         if (reg_val & I40E_REG_MACC_25GB)
2896                                 link->link_speed = RTE_ETH_SPEED_NUM_25G;
2897                         else
2898                                 link->link_speed = RTE_ETH_SPEED_NUM_40G;
2899                 }
2900                 break;
2901         case I40E_REG_SPEED_4:
2902                 if (hw->mac.type == I40E_MAC_X722)
2903                         link->link_speed = RTE_ETH_SPEED_NUM_10G;
2904                 else
2905                         link->link_speed = RTE_ETH_SPEED_NUM_20G;
2906                 break;
2907         default:
2908                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2909                 break;
2910         }
2911 }
2912
2913 static __rte_always_inline void
2914 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2915         bool enable_lse, int wait_to_complete)
2916 {
2917 #define CHECK_INTERVAL             100  /* 100ms */
2918 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2919         uint32_t rep_cnt = MAX_REPEAT_TIME;
2920         struct i40e_link_status link_status;
2921         int status;
2922
2923         memset(&link_status, 0, sizeof(link_status));
2924
2925         do {
2926                 memset(&link_status, 0, sizeof(link_status));
2927
2928                 /* Get link status information from hardware */
2929                 status = i40e_aq_get_link_info(hw, enable_lse,
2930                                                 &link_status, NULL);
2931                 if (unlikely(status != I40E_SUCCESS)) {
2932                         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2933                         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
2934                         PMD_DRV_LOG(ERR, "Failed to get link info");
2935                         return;
2936                 }
2937
2938                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2939                 if (!wait_to_complete || link->link_status)
2940                         break;
2941
2942                 rte_delay_ms(CHECK_INTERVAL);
2943         } while (--rep_cnt);
2944
2945         /* Parse the link status */
2946         switch (link_status.link_speed) {
2947         case I40E_LINK_SPEED_100MB:
2948                 link->link_speed = RTE_ETH_SPEED_NUM_100M;
2949                 break;
2950         case I40E_LINK_SPEED_1GB:
2951                 link->link_speed = RTE_ETH_SPEED_NUM_1G;
2952                 break;
2953         case I40E_LINK_SPEED_10GB:
2954                 link->link_speed = RTE_ETH_SPEED_NUM_10G;
2955                 break;
2956         case I40E_LINK_SPEED_20GB:
2957                 link->link_speed = RTE_ETH_SPEED_NUM_20G;
2958                 break;
2959         case I40E_LINK_SPEED_25GB:
2960                 link->link_speed = RTE_ETH_SPEED_NUM_25G;
2961                 break;
2962         case I40E_LINK_SPEED_40GB:
2963                 link->link_speed = RTE_ETH_SPEED_NUM_40G;
2964                 break;
2965         default:
2966                 if (link->link_status)
2967                         link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2968                 else
2969                         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2970                 break;
2971         }
2972 }
2973
2974 int
2975 i40e_dev_link_update(struct rte_eth_dev *dev,
2976                      int wait_to_complete)
2977 {
2978         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2979         struct rte_eth_link link;
2980         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2981         int ret;
2982
2983         memset(&link, 0, sizeof(link));
2984
2985         /* i40e uses full duplex only */
2986         link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
2987         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2988                         RTE_ETH_LINK_SPEED_FIXED);
2989
2990         if (!wait_to_complete && !enable_lse)
2991                 update_link_reg(hw, &link);
2992         else
2993                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2994
2995         if (hw->switch_dev)
2996                 rte_eth_linkstatus_get(hw->switch_dev, &link);
2997
2998         ret = rte_eth_linkstatus_set(dev, &link);
2999         i40e_notify_all_vfs_link_status(dev);
3000
3001         return ret;
3002 }
3003
3004 static void
3005 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3006                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3007                           uint64_t *stat, uint64_t *prev_stat)
3008 {
3009         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3010         /* enlarge the limitation when statistics counters overflowed */
3011         if (offset_loaded) {
3012                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3013                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3014                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3015         }
3016         *prev_stat = *stat;
3017 }
3018
3019 /* Get all the statistics of a VSI */
3020 void
3021 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3022 {
3023         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3024         struct i40e_eth_stats *nes = &vsi->eth_stats;
3025         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3026         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3027
3028         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3029                                   vsi->offset_loaded, &oes->rx_bytes,
3030                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3031         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3032                             vsi->offset_loaded, &oes->rx_unicast,
3033                             &nes->rx_unicast);
3034         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3035                             vsi->offset_loaded, &oes->rx_multicast,
3036                             &nes->rx_multicast);
3037         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3038                             vsi->offset_loaded, &oes->rx_broadcast,
3039                             &nes->rx_broadcast);
3040         /* exclude CRC bytes */
3041         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3042                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3043
3044         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3045                             &oes->rx_discards, &nes->rx_discards);
3046         /* GLV_REPC not supported */
3047         /* GLV_RMPC not supported */
3048         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3049                             &oes->rx_unknown_protocol,
3050                             &nes->rx_unknown_protocol);
3051         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3052                                   vsi->offset_loaded, &oes->tx_bytes,
3053                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3054         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3055                             vsi->offset_loaded, &oes->tx_unicast,
3056                             &nes->tx_unicast);
3057         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3058                             vsi->offset_loaded, &oes->tx_multicast,
3059                             &nes->tx_multicast);
3060         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3061                             vsi->offset_loaded,  &oes->tx_broadcast,
3062                             &nes->tx_broadcast);
3063         /* GLV_TDPC not supported */
3064         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3065                             &oes->tx_errors, &nes->tx_errors);
3066         vsi->offset_loaded = true;
3067
3068         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3069                     vsi->vsi_id);
3070         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3071         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3072         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3073         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3074         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3075         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3076                     nes->rx_unknown_protocol);
3077         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3078         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3079         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3080         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3081         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3082         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3083         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3084                     vsi->vsi_id);
3085 }
3086
3087 static void
3088 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3089 {
3090         unsigned int i;
3091         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3092         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3093
3094         /* Get rx/tx bytes of internal transfer packets */
3095         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3096                                   I40E_GLV_GORCL(hw->port),
3097                                   pf->offset_loaded,
3098                                   &pf->internal_stats_offset.rx_bytes,
3099                                   &pf->internal_stats.rx_bytes,
3100                                   &pf->internal_prev_rx_bytes);
3101         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3102                                   I40E_GLV_GOTCL(hw->port),
3103                                   pf->offset_loaded,
3104                                   &pf->internal_stats_offset.tx_bytes,
3105                                   &pf->internal_stats.tx_bytes,
3106                                   &pf->internal_prev_tx_bytes);
3107         /* Get total internal rx packet count */
3108         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3109                             I40E_GLV_UPRCL(hw->port),
3110                             pf->offset_loaded,
3111                             &pf->internal_stats_offset.rx_unicast,
3112                             &pf->internal_stats.rx_unicast);
3113         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3114                             I40E_GLV_MPRCL(hw->port),
3115                             pf->offset_loaded,
3116                             &pf->internal_stats_offset.rx_multicast,
3117                             &pf->internal_stats.rx_multicast);
3118         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3119                             I40E_GLV_BPRCL(hw->port),
3120                             pf->offset_loaded,
3121                             &pf->internal_stats_offset.rx_broadcast,
3122                             &pf->internal_stats.rx_broadcast);
3123         /* Get total internal tx packet count */
3124         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3125                             I40E_GLV_UPTCL(hw->port),
3126                             pf->offset_loaded,
3127                             &pf->internal_stats_offset.tx_unicast,
3128                             &pf->internal_stats.tx_unicast);
3129         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3130                             I40E_GLV_MPTCL(hw->port),
3131                             pf->offset_loaded,
3132                             &pf->internal_stats_offset.tx_multicast,
3133                             &pf->internal_stats.tx_multicast);
3134         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3135                             I40E_GLV_BPTCL(hw->port),
3136                             pf->offset_loaded,
3137                             &pf->internal_stats_offset.tx_broadcast,
3138                             &pf->internal_stats.tx_broadcast);
3139
3140         /* exclude CRC size */
3141         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3142                 pf->internal_stats.rx_multicast +
3143                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3144
3145         /* Get statistics of struct i40e_eth_stats */
3146         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3147                                   I40E_GLPRT_GORCL(hw->port),
3148                                   pf->offset_loaded, &os->eth.rx_bytes,
3149                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3150         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3151                             I40E_GLPRT_UPRCL(hw->port),
3152                             pf->offset_loaded, &os->eth.rx_unicast,
3153                             &ns->eth.rx_unicast);
3154         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3155                             I40E_GLPRT_MPRCL(hw->port),
3156                             pf->offset_loaded, &os->eth.rx_multicast,
3157                             &ns->eth.rx_multicast);
3158         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3159                             I40E_GLPRT_BPRCL(hw->port),
3160                             pf->offset_loaded, &os->eth.rx_broadcast,
3161                             &ns->eth.rx_broadcast);
3162         /* Workaround: CRC size should not be included in byte statistics,
3163          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3164          * packet.
3165          */
3166         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3167                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3168
3169         /* exclude internal rx bytes
3170          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3171          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3172          * value.
3173          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3174          */
3175         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3176                 ns->eth.rx_bytes = 0;
3177         else
3178                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3179
3180         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3181                 ns->eth.rx_unicast = 0;
3182         else
3183                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3184
3185         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3186                 ns->eth.rx_multicast = 0;
3187         else
3188                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3189
3190         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3191                 ns->eth.rx_broadcast = 0;
3192         else
3193                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3194
3195         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3196                             pf->offset_loaded, &os->eth.rx_discards,
3197                             &ns->eth.rx_discards);
3198         /* GLPRT_REPC not supported */
3199         /* GLPRT_RMPC not supported */
3200         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3201                             pf->offset_loaded,
3202                             &os->eth.rx_unknown_protocol,
3203                             &ns->eth.rx_unknown_protocol);
3204         i40e_stat_update_48(hw, I40E_GL_RXERR1_H(hw->pf_id + I40E_MAX_VF),
3205                             I40E_GL_RXERR1_L(hw->pf_id + I40E_MAX_VF),
3206                             pf->offset_loaded, &pf->rx_err1_offset,
3207                             &pf->rx_err1);
3208         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3209                                   I40E_GLPRT_GOTCL(hw->port),
3210                                   pf->offset_loaded, &os->eth.tx_bytes,
3211                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3212         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3213                             I40E_GLPRT_UPTCL(hw->port),
3214                             pf->offset_loaded, &os->eth.tx_unicast,
3215                             &ns->eth.tx_unicast);
3216         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3217                             I40E_GLPRT_MPTCL(hw->port),
3218                             pf->offset_loaded, &os->eth.tx_multicast,
3219                             &ns->eth.tx_multicast);
3220         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3221                             I40E_GLPRT_BPTCL(hw->port),
3222                             pf->offset_loaded, &os->eth.tx_broadcast,
3223                             &ns->eth.tx_broadcast);
3224         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3225                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3226
3227         /* exclude internal tx bytes
3228          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3229          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3230          * value.
3231          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3232          */
3233         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3234                 ns->eth.tx_bytes = 0;
3235         else
3236                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3237
3238         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3239                 ns->eth.tx_unicast = 0;
3240         else
3241                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3242
3243         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3244                 ns->eth.tx_multicast = 0;
3245         else
3246                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3247
3248         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3249                 ns->eth.tx_broadcast = 0;
3250         else
3251                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3252
3253         /* GLPRT_TEPC not supported */
3254
3255         /* additional port specific stats */
3256         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3257                             pf->offset_loaded, &os->tx_dropped_link_down,
3258                             &ns->tx_dropped_link_down);
3259         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3260                             pf->offset_loaded, &os->crc_errors,
3261                             &ns->crc_errors);
3262         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3263                             pf->offset_loaded, &os->illegal_bytes,
3264                             &ns->illegal_bytes);
3265         /* GLPRT_ERRBC not supported */
3266         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3267                             pf->offset_loaded, &os->mac_local_faults,
3268                             &ns->mac_local_faults);
3269         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3270                             pf->offset_loaded, &os->mac_remote_faults,
3271                             &ns->mac_remote_faults);
3272         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3273                             pf->offset_loaded, &os->rx_length_errors,
3274                             &ns->rx_length_errors);
3275         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3276                             pf->offset_loaded, &os->link_xon_rx,
3277                             &ns->link_xon_rx);
3278         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3279                             pf->offset_loaded, &os->link_xoff_rx,
3280                             &ns->link_xoff_rx);
3281         for (i = 0; i < 8; i++) {
3282                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3283                                     pf->offset_loaded,
3284                                     &os->priority_xon_rx[i],
3285                                     &ns->priority_xon_rx[i]);
3286                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3287                                     pf->offset_loaded,
3288                                     &os->priority_xoff_rx[i],
3289                                     &ns->priority_xoff_rx[i]);
3290         }
3291         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3292                             pf->offset_loaded, &os->link_xon_tx,
3293                             &ns->link_xon_tx);
3294         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3295                             pf->offset_loaded, &os->link_xoff_tx,
3296                             &ns->link_xoff_tx);
3297         for (i = 0; i < 8; i++) {
3298                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3299                                     pf->offset_loaded,
3300                                     &os->priority_xon_tx[i],
3301                                     &ns->priority_xon_tx[i]);
3302                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3303                                     pf->offset_loaded,
3304                                     &os->priority_xoff_tx[i],
3305                                     &ns->priority_xoff_tx[i]);
3306                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3307                                     pf->offset_loaded,
3308                                     &os->priority_xon_2_xoff[i],
3309                                     &ns->priority_xon_2_xoff[i]);
3310         }
3311         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3312                             I40E_GLPRT_PRC64L(hw->port),
3313                             pf->offset_loaded, &os->rx_size_64,
3314                             &ns->rx_size_64);
3315         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3316                             I40E_GLPRT_PRC127L(hw->port),
3317                             pf->offset_loaded, &os->rx_size_127,
3318                             &ns->rx_size_127);
3319         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3320                             I40E_GLPRT_PRC255L(hw->port),
3321                             pf->offset_loaded, &os->rx_size_255,
3322                             &ns->rx_size_255);
3323         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3324                             I40E_GLPRT_PRC511L(hw->port),
3325                             pf->offset_loaded, &os->rx_size_511,
3326                             &ns->rx_size_511);
3327         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3328                             I40E_GLPRT_PRC1023L(hw->port),
3329                             pf->offset_loaded, &os->rx_size_1023,
3330                             &ns->rx_size_1023);
3331         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3332                             I40E_GLPRT_PRC1522L(hw->port),
3333                             pf->offset_loaded, &os->rx_size_1522,
3334                             &ns->rx_size_1522);
3335         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3336                             I40E_GLPRT_PRC9522L(hw->port),
3337                             pf->offset_loaded, &os->rx_size_big,
3338                             &ns->rx_size_big);
3339         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3340                             pf->offset_loaded, &os->rx_undersize,
3341                             &ns->rx_undersize);
3342         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3343                             pf->offset_loaded, &os->rx_fragments,
3344                             &ns->rx_fragments);
3345         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3346                             pf->offset_loaded, &os->rx_oversize,
3347                             &ns->rx_oversize);
3348         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3349                             pf->offset_loaded, &os->rx_jabber,
3350                             &ns->rx_jabber);
3351         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3352                             I40E_GLPRT_PTC64L(hw->port),
3353                             pf->offset_loaded, &os->tx_size_64,
3354                             &ns->tx_size_64);
3355         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3356                             I40E_GLPRT_PTC127L(hw->port),
3357                             pf->offset_loaded, &os->tx_size_127,
3358                             &ns->tx_size_127);
3359         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3360                             I40E_GLPRT_PTC255L(hw->port),
3361                             pf->offset_loaded, &os->tx_size_255,
3362                             &ns->tx_size_255);
3363         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3364                             I40E_GLPRT_PTC511L(hw->port),
3365                             pf->offset_loaded, &os->tx_size_511,
3366                             &ns->tx_size_511);
3367         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3368                             I40E_GLPRT_PTC1023L(hw->port),
3369                             pf->offset_loaded, &os->tx_size_1023,
3370                             &ns->tx_size_1023);
3371         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3372                             I40E_GLPRT_PTC1522L(hw->port),
3373                             pf->offset_loaded, &os->tx_size_1522,
3374                             &ns->tx_size_1522);
3375         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3376                             I40E_GLPRT_PTC9522L(hw->port),
3377                             pf->offset_loaded, &os->tx_size_big,
3378                             &ns->tx_size_big);
3379         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3380                            pf->offset_loaded,
3381                            &os->fd_sb_match, &ns->fd_sb_match);
3382         /* GLPRT_MSPDC not supported */
3383         /* GLPRT_XEC not supported */
3384
3385         pf->offset_loaded = true;
3386
3387         if (pf->main_vsi)
3388                 i40e_update_vsi_stats(pf->main_vsi);
3389 }
3390
3391 /* Get all statistics of a port */
3392 static int
3393 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3394 {
3395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3398         struct i40e_vsi *vsi;
3399         unsigned i;
3400
3401         /* call read registers - updates values, now write them to struct */
3402         i40e_read_stats_registers(pf, hw);
3403
3404         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3405                         pf->main_vsi->eth_stats.rx_multicast +
3406                         pf->main_vsi->eth_stats.rx_broadcast -
3407                         pf->main_vsi->eth_stats.rx_discards -
3408                         pf->rx_err1;
3409         stats->opackets = ns->eth.tx_unicast +
3410                         ns->eth.tx_multicast +
3411                         ns->eth.tx_broadcast;
3412         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3413         stats->obytes   = ns->eth.tx_bytes;
3414         stats->oerrors  = ns->eth.tx_errors +
3415                         pf->main_vsi->eth_stats.tx_errors;
3416
3417         /* Rx Errors */
3418         stats->imissed  = ns->eth.rx_discards +
3419                         pf->main_vsi->eth_stats.rx_discards;
3420         stats->ierrors  = ns->crc_errors +
3421                         ns->rx_length_errors + ns->rx_undersize +
3422                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
3423                         pf->rx_err1;
3424
3425         if (pf->vfs) {
3426                 for (i = 0; i < pf->vf_num; i++) {
3427                         vsi = pf->vfs[i].vsi;
3428                         i40e_update_vsi_stats(vsi);
3429
3430                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3431                                         vsi->eth_stats.rx_multicast +
3432                                         vsi->eth_stats.rx_broadcast -
3433                                         vsi->eth_stats.rx_discards);
3434                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3435                         stats->oerrors  += vsi->eth_stats.tx_errors;
3436                         stats->imissed  += vsi->eth_stats.rx_discards;
3437                 }
3438         }
3439
3440         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3441         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3442         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3443         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3444         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3445         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3446         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3447                     ns->eth.rx_unknown_protocol);
3448         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3449         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3450         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3451         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3452         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3453         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3454
3455         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3456                     ns->tx_dropped_link_down);
3457         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3458         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3459                     ns->illegal_bytes);
3460         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3461         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3462                     ns->mac_local_faults);
3463         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3464                     ns->mac_remote_faults);
3465         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3466                     ns->rx_length_errors);
3467         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3468         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3469         for (i = 0; i < 8; i++) {
3470                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3471                                 i, ns->priority_xon_rx[i]);
3472                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3473                                 i, ns->priority_xoff_rx[i]);
3474         }
3475         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3476         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3477         for (i = 0; i < 8; i++) {
3478                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3479                                 i, ns->priority_xon_tx[i]);
3480                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3481                                 i, ns->priority_xoff_tx[i]);
3482                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3483                                 i, ns->priority_xon_2_xoff[i]);
3484         }
3485         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3486         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3487         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3488         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3489         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3490         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3491         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3492         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3493         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3494         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3495         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3496         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3497         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3498         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3499         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3500         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3501         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3502         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3503         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3504                         ns->mac_short_packet_dropped);
3505         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3506                     ns->checksum_error);
3507         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3508         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3509         return 0;
3510 }
3511
3512 /* Reset the statistics */
3513 static int
3514 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3515 {
3516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3517         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518
3519         /* Mark PF and VSI stats to update the offset, aka "reset" */
3520         pf->offset_loaded = false;
3521         if (pf->main_vsi)
3522                 pf->main_vsi->offset_loaded = false;
3523
3524         /* read the stats, reading current register values into offset */
3525         i40e_read_stats_registers(pf, hw);
3526
3527         return 0;
3528 }
3529
3530 static uint32_t
3531 i40e_xstats_calc_num(void)
3532 {
3533         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3534                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3535                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3536 }
3537
3538 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3539                                      struct rte_eth_xstat_name *xstats_names,
3540                                      __rte_unused unsigned limit)
3541 {
3542         unsigned count = 0;
3543         unsigned i, prio;
3544
3545         if (xstats_names == NULL)
3546                 return i40e_xstats_calc_num();
3547
3548         /* Note: limit checked in rte_eth_xstats_names() */
3549
3550         /* Get stats from i40e_eth_stats struct */
3551         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3552                 strlcpy(xstats_names[count].name,
3553                         rte_i40e_stats_strings[i].name,
3554                         sizeof(xstats_names[count].name));
3555                 count++;
3556         }
3557
3558         /* Get individiual stats from i40e_hw_port struct */
3559         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3560                 strlcpy(xstats_names[count].name,
3561                         rte_i40e_hw_port_strings[i].name,
3562                         sizeof(xstats_names[count].name));
3563                 count++;
3564         }
3565
3566         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3567                 for (prio = 0; prio < 8; prio++) {
3568                         snprintf(xstats_names[count].name,
3569                                  sizeof(xstats_names[count].name),
3570                                  "rx_priority%u_%s", prio,
3571                                  rte_i40e_rxq_prio_strings[i].name);
3572                         count++;
3573                 }
3574         }
3575
3576         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3577                 for (prio = 0; prio < 8; prio++) {
3578                         snprintf(xstats_names[count].name,
3579                                  sizeof(xstats_names[count].name),
3580                                  "tx_priority%u_%s", prio,
3581                                  rte_i40e_txq_prio_strings[i].name);
3582                         count++;
3583                 }
3584         }
3585         return count;
3586 }
3587
3588 static int
3589 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3590                     unsigned n)
3591 {
3592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3593         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         unsigned i, count, prio;
3595         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3596
3597         count = i40e_xstats_calc_num();
3598         if (n < count)
3599                 return count;
3600
3601         i40e_read_stats_registers(pf, hw);
3602
3603         if (xstats == NULL)
3604                 return 0;
3605
3606         count = 0;
3607
3608         /* Get stats from i40e_eth_stats struct */
3609         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3610                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3611                         rte_i40e_stats_strings[i].offset);
3612                 xstats[count].id = count;
3613                 count++;
3614         }
3615
3616         /* Get individiual stats from i40e_hw_port struct */
3617         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3618                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3619                         rte_i40e_hw_port_strings[i].offset);
3620                 xstats[count].id = count;
3621                 count++;
3622         }
3623
3624         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3625                 for (prio = 0; prio < 8; prio++) {
3626                         xstats[count].value =
3627                                 *(uint64_t *)(((char *)hw_stats) +
3628                                 rte_i40e_rxq_prio_strings[i].offset +
3629                                 (sizeof(uint64_t) * prio));
3630                         xstats[count].id = count;
3631                         count++;
3632                 }
3633         }
3634
3635         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3636                 for (prio = 0; prio < 8; prio++) {
3637                         xstats[count].value =
3638                                 *(uint64_t *)(((char *)hw_stats) +
3639                                 rte_i40e_txq_prio_strings[i].offset +
3640                                 (sizeof(uint64_t) * prio));
3641                         xstats[count].id = count;
3642                         count++;
3643                 }
3644         }
3645
3646         return count;
3647 }
3648
3649 static int
3650 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3651 {
3652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         u32 full_ver;
3654         u8 ver, patch;
3655         u16 build;
3656         int ret;
3657
3658         full_ver = hw->nvm.oem_ver;
3659         ver = (u8)(full_ver >> 24);
3660         build = (u16)((full_ver >> 8) & 0xffff);
3661         patch = (u8)(full_ver & 0xff);
3662
3663         ret = snprintf(fw_version, fw_size,
3664                  "%d.%d%d 0x%08x %d.%d.%d",
3665                  ((hw->nvm.version >> 12) & 0xf),
3666                  ((hw->nvm.version >> 4) & 0xff),
3667                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3668                  ver, build, patch);
3669         if (ret < 0)
3670                 return -EINVAL;
3671
3672         ret += 1; /* add the size of '\0' */
3673         if (fw_size < (size_t)ret)
3674                 return ret;
3675         else
3676                 return 0;
3677 }
3678
3679 /*
3680  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3681  * the Rx data path does not hang if the FW LLDP is stopped.
3682  * return true if lldp need to stop
3683  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3684  */
3685 static bool
3686 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3687 {
3688         double nvm_ver;
3689         char ver_str[64] = {0};
3690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3691
3692         i40e_fw_version_get(dev, ver_str, 64);
3693         nvm_ver = atof(ver_str);
3694         if ((hw->mac.type == I40E_MAC_X722 ||
3695              hw->mac.type == I40E_MAC_X722_VF) &&
3696              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3697                 return true;
3698         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3699                 return true;
3700
3701         return false;
3702 }
3703
3704 static int
3705 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3706 {
3707         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709         struct i40e_vsi *vsi = pf->main_vsi;
3710         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3711
3712         dev_info->max_rx_queues = vsi->nb_qps;
3713         dev_info->max_tx_queues = vsi->nb_qps;
3714         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3715         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3716         dev_info->max_mac_addrs = vsi->max_macaddrs;
3717         dev_info->max_vfs = pci_dev->max_vfs;
3718         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3719         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3720         dev_info->rx_queue_offload_capa = 0;
3721         dev_info->rx_offload_capa =
3722                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
3723                 RTE_ETH_RX_OFFLOAD_QINQ_STRIP |
3724                 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
3725                 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
3726                 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
3727                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3728                 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
3729                 RTE_ETH_RX_OFFLOAD_SCATTER |
3730                 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |
3731                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
3732                 RTE_ETH_RX_OFFLOAD_RSS_HASH;
3733
3734         dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
3735         dev_info->tx_offload_capa =
3736                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
3737                 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
3738                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
3739                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
3740                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
3741                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
3742                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3743                 RTE_ETH_TX_OFFLOAD_TCP_TSO |
3744                 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
3745                 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
3746                 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO |
3747                 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
3748                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
3749                 dev_info->tx_queue_offload_capa;
3750         dev_info->dev_capa =
3751                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3752                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3753
3754         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3755                                                 sizeof(uint32_t);
3756         dev_info->reta_size = pf->hash_lut_size;
3757         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3758
3759         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3760                 .rx_thresh = {
3761                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3762                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3763                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3764                 },
3765                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3766                 .rx_drop_en = 0,
3767                 .offloads = 0,
3768         };
3769
3770         dev_info->default_txconf = (struct rte_eth_txconf) {
3771                 .tx_thresh = {
3772                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3773                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3774                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3775                 },
3776                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3777                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3778                 .offloads = 0,
3779         };
3780
3781         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3782                 .nb_max = I40E_MAX_RING_DESC,
3783                 .nb_min = I40E_MIN_RING_DESC,
3784                 .nb_align = I40E_ALIGN_RING_DESC,
3785         };
3786
3787         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3788                 .nb_max = I40E_MAX_RING_DESC,
3789                 .nb_min = I40E_MIN_RING_DESC,
3790                 .nb_align = I40E_ALIGN_RING_DESC,
3791                 .nb_seg_max = I40E_TX_MAX_SEG,
3792                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3793         };
3794
3795         if (pf->flags & I40E_FLAG_VMDQ) {
3796                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3797                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3798                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3799                                                 pf->max_nb_vmdq_vsi;
3800                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3801                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3802                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3803         }
3804
3805         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3806                 /* For XL710 */
3807                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_40G;
3808                 dev_info->default_rxportconf.nb_queues = 2;
3809                 dev_info->default_txportconf.nb_queues = 2;
3810                 if (dev->data->nb_rx_queues == 1)
3811                         dev_info->default_rxportconf.ring_size = 2048;
3812                 else
3813                         dev_info->default_rxportconf.ring_size = 1024;
3814                 if (dev->data->nb_tx_queues == 1)
3815                         dev_info->default_txportconf.ring_size = 1024;
3816                 else
3817                         dev_info->default_txportconf.ring_size = 512;
3818
3819         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3820                 /* For XXV710 */
3821                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_25G;
3822                 dev_info->default_rxportconf.nb_queues = 1;
3823                 dev_info->default_txportconf.nb_queues = 1;
3824                 dev_info->default_rxportconf.ring_size = 256;
3825                 dev_info->default_txportconf.ring_size = 256;
3826         } else {
3827                 /* For X710 */
3828                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G;
3829                 dev_info->default_rxportconf.nb_queues = 1;
3830                 dev_info->default_txportconf.nb_queues = 1;
3831                 if (dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_10G) {
3832                         dev_info->default_rxportconf.ring_size = 512;
3833                         dev_info->default_txportconf.ring_size = 256;
3834                 } else {
3835                         dev_info->default_rxportconf.ring_size = 256;
3836                         dev_info->default_txportconf.ring_size = 256;
3837                 }
3838         }
3839         dev_info->default_rxportconf.burst_size = 32;
3840         dev_info->default_txportconf.burst_size = 32;
3841
3842         return 0;
3843 }
3844
3845 static int
3846 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3847 {
3848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3849         struct i40e_vsi *vsi = pf->main_vsi;
3850         PMD_INIT_FUNC_TRACE();
3851
3852         if (on)
3853                 return i40e_vsi_add_vlan(vsi, vlan_id);
3854         else
3855                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3856 }
3857
3858 static int
3859 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3860                                 enum rte_vlan_type vlan_type,
3861                                 uint16_t tpid, int qinq)
3862 {
3863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3864         uint64_t reg_r = 0;
3865         uint64_t reg_w = 0;
3866         uint16_t reg_id = 3;
3867         int ret;
3868
3869         if (qinq) {
3870                 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER)
3871                         reg_id = 2;
3872         }
3873
3874         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3875                                           &reg_r, NULL);
3876         if (ret != I40E_SUCCESS) {
3877                 PMD_DRV_LOG(ERR,
3878                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3879                            reg_id);
3880                 return -EIO;
3881         }
3882         PMD_DRV_LOG(DEBUG,
3883                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3884                     reg_id, reg_r);
3885
3886         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3887         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3888         if (reg_r == reg_w) {
3889                 PMD_DRV_LOG(DEBUG, "No need to write");
3890                 return 0;
3891         }
3892
3893         ret = i40e_aq_debug_write_global_register(hw,
3894                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3895                                            reg_w, NULL);
3896         if (ret != I40E_SUCCESS) {
3897                 PMD_DRV_LOG(ERR,
3898                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3899                             reg_id);
3900                 return -EIO;
3901         }
3902         PMD_DRV_LOG(DEBUG,
3903                     "Global register 0x%08x is changed with value 0x%08x",
3904                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3905
3906         return 0;
3907 }
3908
3909 static int
3910 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3911                    enum rte_vlan_type vlan_type,
3912                    uint16_t tpid)
3913 {
3914         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3916         int qinq = dev->data->dev_conf.rxmode.offloads &
3917                    RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
3918         int ret = 0;
3919
3920         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
3921              vlan_type != RTE_ETH_VLAN_TYPE_OUTER) ||
3922             (!qinq && vlan_type == RTE_ETH_VLAN_TYPE_INNER)) {
3923                 PMD_DRV_LOG(ERR,
3924                             "Unsupported vlan type.");
3925                 return -EINVAL;
3926         }
3927
3928         if (pf->support_multi_driver) {
3929                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3930                 return -ENOTSUP;
3931         }
3932
3933         /* 802.1ad frames ability is added in NVM API 1.7*/
3934         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3935                 if (qinq) {
3936                         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER)
3937                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3938                         else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER)
3939                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3940                 } else {
3941                         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER)
3942                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3943                 }
3944                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3945                 if (ret != I40E_SUCCESS) {
3946                         PMD_DRV_LOG(ERR,
3947                                     "Set switch config failed aq_err: %d",
3948                                     hw->aq.asq_last_status);
3949                         ret = -EIO;
3950                 }
3951         } else
3952                 /* If NVM API < 1.7, keep the register setting */
3953                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3954                                                       tpid, qinq);
3955
3956         return ret;
3957 }
3958
3959 /* Configure outer vlan stripping on or off in QinQ mode */
3960 static int
3961 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3962 {
3963         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3964         int ret = I40E_SUCCESS;
3965         uint32_t reg;
3966
3967         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3968                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3969                 return -EINVAL;
3970         }
3971
3972         /* Configure for outer VLAN RX stripping */
3973         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
3974
3975         if (on)
3976                 reg |= I40E_VSI_TSR_QINQ_STRIP;
3977         else
3978                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
3979
3980         ret = i40e_aq_debug_write_register(hw,
3981                                                    I40E_VSI_TSR(vsi->vsi_id),
3982                                                    reg, NULL);
3983         if (ret < 0) {
3984                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
3985                                     vsi->vsi_id);
3986                 return I40E_ERR_CONFIG;
3987         }
3988
3989         return ret;
3990 }
3991
3992 static int
3993 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3994 {
3995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3996         struct i40e_vsi *vsi = pf->main_vsi;
3997         struct rte_eth_rxmode *rxmode;
3998
3999         rxmode = &dev->data->dev_conf.rxmode;
4000         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
4001                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
4002                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4003                 else
4004                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4005         }
4006
4007         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
4008                 /* Enable or disable VLAN stripping */
4009                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
4010                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4011                 else
4012                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4013         }
4014
4015         if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
4016                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) {
4017                         i40e_vsi_config_double_vlan(vsi, TRUE);
4018                         /* Set global registers with default ethertype. */
4019                         i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
4020                                            RTE_ETHER_TYPE_VLAN);
4021                         i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER,
4022                                            RTE_ETHER_TYPE_VLAN);
4023                 }
4024                 else
4025                         i40e_vsi_config_double_vlan(vsi, FALSE);
4026         }
4027
4028         if (mask & RTE_ETH_QINQ_STRIP_MASK) {
4029                 /* Enable or disable outer VLAN stripping */
4030                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP)
4031                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4032                 else
4033                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4034         }
4035
4036         return 0;
4037 }
4038
4039 static void
4040 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4041                           __rte_unused uint16_t queue,
4042                           __rte_unused int on)
4043 {
4044         PMD_INIT_FUNC_TRACE();
4045 }
4046
4047 static int
4048 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4049 {
4050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4051         struct i40e_vsi *vsi = pf->main_vsi;
4052         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4053         struct i40e_vsi_vlan_pvid_info info;
4054
4055         memset(&info, 0, sizeof(info));
4056         info.on = on;
4057         if (info.on)
4058                 info.config.pvid = pvid;
4059         else {
4060                 info.config.reject.tagged =
4061                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4062                 info.config.reject.untagged =
4063                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4064         }
4065
4066         return i40e_vsi_vlan_pvid_set(vsi, &info);
4067 }
4068
4069 static int
4070 i40e_dev_led_on(struct rte_eth_dev *dev)
4071 {
4072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4073         uint32_t mode = i40e_led_get(hw);
4074
4075         if (mode == 0)
4076                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4077
4078         return 0;
4079 }
4080
4081 static int
4082 i40e_dev_led_off(struct rte_eth_dev *dev)
4083 {
4084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         uint32_t mode = i40e_led_get(hw);
4086
4087         if (mode != 0)
4088                 i40e_led_set(hw, 0, false);
4089
4090         return 0;
4091 }
4092
4093 static int
4094 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4095 {
4096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4098
4099         fc_conf->pause_time = pf->fc_conf.pause_time;
4100
4101         /* read out from register, in case they are modified by other port */
4102         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4103                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4104         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4105                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4106
4107         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4108         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4109
4110          /* Return current mode according to actual setting*/
4111         switch (hw->fc.current_mode) {
4112         case I40E_FC_FULL:
4113                 fc_conf->mode = RTE_ETH_FC_FULL;
4114                 break;
4115         case I40E_FC_TX_PAUSE:
4116                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
4117                 break;
4118         case I40E_FC_RX_PAUSE:
4119                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
4120                 break;
4121         case I40E_FC_NONE:
4122         default:
4123                 fc_conf->mode = RTE_ETH_FC_NONE;
4124         };
4125
4126         return 0;
4127 }
4128
4129 static int
4130 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4131 {
4132         uint32_t mflcn_reg, fctrl_reg, reg;
4133         uint32_t max_high_water;
4134         uint8_t i, aq_failure;
4135         int err;
4136         struct i40e_hw *hw;
4137         struct i40e_pf *pf;
4138         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4139                 [RTE_ETH_FC_NONE] = I40E_FC_NONE,
4140                 [RTE_ETH_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4141                 [RTE_ETH_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4142                 [RTE_ETH_FC_FULL] = I40E_FC_FULL
4143         };
4144
4145         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4146
4147         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4148         if ((fc_conf->high_water > max_high_water) ||
4149                         (fc_conf->high_water < fc_conf->low_water)) {
4150                 PMD_INIT_LOG(ERR,
4151                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4152                         max_high_water);
4153                 return -EINVAL;
4154         }
4155
4156         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4157         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4158         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4159
4160         pf->fc_conf.pause_time = fc_conf->pause_time;
4161         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4162         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4163
4164         PMD_INIT_FUNC_TRACE();
4165
4166         /* All the link flow control related enable/disable register
4167          * configuration is handle by the F/W
4168          */
4169         err = i40e_set_fc(hw, &aq_failure, true);
4170         if (err < 0)
4171                 return -ENOSYS;
4172
4173         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4174                 /* Configure flow control refresh threshold,
4175                  * the value for stat_tx_pause_refresh_timer[8]
4176                  * is used for global pause operation.
4177                  */
4178
4179                 I40E_WRITE_REG(hw,
4180                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4181                                pf->fc_conf.pause_time);
4182
4183                 /* configure the timer value included in transmitted pause
4184                  * frame,
4185                  * the value for stat_tx_pause_quanta[8] is used for global
4186                  * pause operation
4187                  */
4188                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4189                                pf->fc_conf.pause_time);
4190
4191                 fctrl_reg = I40E_READ_REG(hw,
4192                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4193
4194                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4195                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4196                 else
4197                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4198
4199                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4200                                fctrl_reg);
4201         } else {
4202                 /* Configure pause time (2 TCs per register) */
4203                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4204                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4205                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4206
4207                 /* Configure flow control refresh threshold value */
4208                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4209                                pf->fc_conf.pause_time / 2);
4210
4211                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4212
4213                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4214                  *depending on configuration
4215                  */
4216                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4217                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4218                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4219                 } else {
4220                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4221                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4222                 }
4223
4224                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4225         }
4226
4227         if (!pf->support_multi_driver) {
4228                 /* config water marker both based on the packets and bytes */
4229                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4230                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4231                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4232                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4233                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4234                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4235                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4236                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4237                                   << I40E_KILOSHIFT);
4238                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4239                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4240                                    << I40E_KILOSHIFT);
4241         } else {
4242                 PMD_DRV_LOG(ERR,
4243                             "Water marker configuration is not supported.");
4244         }
4245
4246         I40E_WRITE_FLUSH(hw);
4247
4248         return 0;
4249 }
4250
4251 static int
4252 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4253                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4254 {
4255         PMD_INIT_FUNC_TRACE();
4256
4257         return -ENOSYS;
4258 }
4259
4260 /* Add a MAC address, and update filters */
4261 static int
4262 i40e_macaddr_add(struct rte_eth_dev *dev,
4263                  struct rte_ether_addr *mac_addr,
4264                  __rte_unused uint32_t index,
4265                  uint32_t pool)
4266 {
4267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4268         struct i40e_mac_filter_info mac_filter;
4269         struct i40e_vsi *vsi;
4270         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4271         int ret;
4272
4273         /* If VMDQ not enabled or configured, return */
4274         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4275                           !pf->nb_cfg_vmdq_vsi)) {
4276                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4277                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4278                         pool);
4279                 return -ENOTSUP;
4280         }
4281
4282         if (pool > pf->nb_cfg_vmdq_vsi) {
4283                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4284                                 pool, pf->nb_cfg_vmdq_vsi);
4285                 return -EINVAL;
4286         }
4287
4288         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4289         if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
4290                 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4291         else
4292                 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4293
4294         if (pool == 0)
4295                 vsi = pf->main_vsi;
4296         else
4297                 vsi = pf->vmdq[pool - 1].vsi;
4298
4299         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4300         if (ret != I40E_SUCCESS) {
4301                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4302                 return -ENODEV;
4303         }
4304         return 0;
4305 }
4306
4307 /* Remove a MAC address, and update filters */
4308 static void
4309 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4310 {
4311         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4312         struct i40e_vsi *vsi;
4313         struct rte_eth_dev_data *data = dev->data;
4314         struct rte_ether_addr *macaddr;
4315         int ret;
4316         uint32_t i;
4317         uint64_t pool_sel;
4318
4319         macaddr = &(data->mac_addrs[index]);
4320
4321         pool_sel = dev->data->mac_pool_sel[index];
4322
4323         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4324                 if (pool_sel & (1ULL << i)) {
4325                         if (i == 0)
4326                                 vsi = pf->main_vsi;
4327                         else {
4328                                 /* No VMDQ pool enabled or configured */
4329                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4330                                         (i > pf->nb_cfg_vmdq_vsi)) {
4331                                         PMD_DRV_LOG(ERR,
4332                                                 "No VMDQ pool enabled/configured");
4333                                         return;
4334                                 }
4335                                 vsi = pf->vmdq[i - 1].vsi;
4336                         }
4337                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4338
4339                         if (ret) {
4340                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4341                                 return;
4342                         }
4343                 }
4344         }
4345 }
4346
4347 static int
4348 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4349 {
4350         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4351         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4352         uint32_t reg;
4353         int ret;
4354
4355         if (!lut)
4356                 return -EINVAL;
4357
4358         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4359                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4360                                           vsi->type != I40E_VSI_SRIOV,
4361                                           lut, lut_size);
4362                 if (ret) {
4363                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4364                         return ret;
4365                 }
4366         } else {
4367                 uint32_t *lut_dw = (uint32_t *)lut;
4368                 uint16_t i, lut_size_dw = lut_size / 4;
4369
4370                 if (vsi->type == I40E_VSI_SRIOV) {
4371                         for (i = 0; i <= lut_size_dw; i++) {
4372                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4373                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4374                         }
4375                 } else {
4376                         for (i = 0; i < lut_size_dw; i++)
4377                                 lut_dw[i] = I40E_READ_REG(hw,
4378                                                           I40E_PFQF_HLUT(i));
4379                 }
4380         }
4381
4382         return 0;
4383 }
4384
4385 int
4386 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4387 {
4388         struct i40e_pf *pf;
4389         struct i40e_hw *hw;
4390
4391         if (!vsi || !lut)
4392                 return -EINVAL;
4393
4394         pf = I40E_VSI_TO_PF(vsi);
4395         hw = I40E_VSI_TO_HW(vsi);
4396
4397         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4398                 enum i40e_status_code status;
4399
4400                 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4401                                              vsi->type != I40E_VSI_SRIOV,
4402                                              lut, lut_size);
4403                 if (status) {
4404                         PMD_DRV_LOG(ERR,
4405                                     "Failed to update RSS lookup table, error status: %d",
4406                                     status);
4407                         return -EIO;
4408                 }
4409         } else {
4410                 uint32_t *lut_dw = (uint32_t *)lut;
4411                 uint16_t i, lut_size_dw = lut_size / 4;
4412
4413                 if (vsi->type == I40E_VSI_SRIOV) {
4414                         for (i = 0; i < lut_size_dw; i++)
4415                                 I40E_WRITE_REG(
4416                                         hw,
4417                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4418                                         lut_dw[i]);
4419                 } else {
4420                         for (i = 0; i < lut_size_dw; i++)
4421                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4422                                                lut_dw[i]);
4423                 }
4424                 I40E_WRITE_FLUSH(hw);
4425         }
4426
4427         return 0;
4428 }
4429
4430 static int
4431 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4432                          struct rte_eth_rss_reta_entry64 *reta_conf,
4433                          uint16_t reta_size)
4434 {
4435         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4436         uint16_t i, lut_size = pf->hash_lut_size;
4437         uint16_t idx, shift;
4438         uint8_t *lut;
4439         int ret;
4440
4441         if (reta_size != lut_size ||
4442                 reta_size > RTE_ETH_RSS_RETA_SIZE_512) {
4443                 PMD_DRV_LOG(ERR,
4444                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4445                         reta_size, lut_size);
4446                 return -EINVAL;
4447         }
4448
4449         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4450         if (!lut) {
4451                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4452                 return -ENOMEM;
4453         }
4454         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4455         if (ret)
4456                 goto out;
4457         for (i = 0; i < reta_size; i++) {
4458                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
4459                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
4460                 if (reta_conf[idx].mask & (1ULL << shift))
4461                         lut[i] = reta_conf[idx].reta[shift];
4462         }
4463         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4464
4465         pf->adapter->rss_reta_updated = 1;
4466
4467 out:
4468         rte_free(lut);
4469
4470         return ret;
4471 }
4472
4473 static int
4474 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4475                         struct rte_eth_rss_reta_entry64 *reta_conf,
4476                         uint16_t reta_size)
4477 {
4478         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4479         uint16_t i, lut_size = pf->hash_lut_size;
4480         uint16_t idx, shift;
4481         uint8_t *lut;
4482         int ret;
4483
4484         if (reta_size != lut_size ||
4485                 reta_size > RTE_ETH_RSS_RETA_SIZE_512) {
4486                 PMD_DRV_LOG(ERR,
4487                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4488                         reta_size, lut_size);
4489                 return -EINVAL;
4490         }
4491
4492         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4493         if (!lut) {
4494                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4495                 return -ENOMEM;
4496         }
4497
4498         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4499         if (ret)
4500                 goto out;
4501         for (i = 0; i < reta_size; i++) {
4502                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
4503                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
4504                 if (reta_conf[idx].mask & (1ULL << shift))
4505                         reta_conf[idx].reta[shift] = lut[i];
4506         }
4507
4508 out:
4509         rte_free(lut);
4510
4511         return ret;
4512 }
4513
4514 /**
4515  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4516  * @hw:   pointer to the HW structure
4517  * @mem:  pointer to mem struct to fill out
4518  * @size: size of memory requested
4519  * @alignment: what to align the allocation to
4520  **/
4521 enum i40e_status_code
4522 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4523                         struct i40e_dma_mem *mem,
4524                         u64 size,
4525                         u32 alignment)
4526 {
4527         static uint64_t i40e_dma_memzone_id;
4528         const struct rte_memzone *mz = NULL;
4529         char z_name[RTE_MEMZONE_NAMESIZE];
4530
4531         if (!mem)
4532                 return I40E_ERR_PARAM;
4533
4534         snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
4535                 __atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
4536         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4537                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4538         if (!mz)
4539                 return I40E_ERR_NO_MEMORY;
4540
4541         mem->size = size;
4542         mem->va = mz->addr;
4543         mem->pa = mz->iova;
4544         mem->zone = (const void *)mz;
4545         PMD_DRV_LOG(DEBUG,
4546                 "memzone %s allocated with physical address: %"PRIu64,
4547                 mz->name, mem->pa);
4548
4549         return I40E_SUCCESS;
4550 }
4551
4552 /**
4553  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4554  * @hw:   pointer to the HW structure
4555  * @mem:  ptr to mem struct to free
4556  **/
4557 enum i40e_status_code
4558 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4559                     struct i40e_dma_mem *mem)
4560 {
4561         if (!mem)
4562                 return I40E_ERR_PARAM;
4563
4564         PMD_DRV_LOG(DEBUG,
4565                 "memzone %s to be freed with physical address: %"PRIu64,
4566                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4567         rte_memzone_free((const struct rte_memzone *)mem->zone);
4568         mem->zone = NULL;
4569         mem->va = NULL;
4570         mem->pa = (u64)0;
4571
4572         return I40E_SUCCESS;
4573 }
4574
4575 /**
4576  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4577  * @hw:   pointer to the HW structure
4578  * @mem:  pointer to mem struct to fill out
4579  * @size: size of memory requested
4580  **/
4581 enum i40e_status_code
4582 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4583                          struct i40e_virt_mem *mem,
4584                          u32 size)
4585 {
4586         if (!mem)
4587                 return I40E_ERR_PARAM;
4588
4589         mem->size = size;
4590         mem->va = rte_zmalloc("i40e", size, 0);
4591
4592         if (mem->va)
4593                 return I40E_SUCCESS;
4594         else
4595                 return I40E_ERR_NO_MEMORY;
4596 }
4597
4598 /**
4599  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4600  * @hw:   pointer to the HW structure
4601  * @mem:  pointer to mem struct to free
4602  **/
4603 enum i40e_status_code
4604 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4605                      struct i40e_virt_mem *mem)
4606 {
4607         if (!mem)
4608                 return I40E_ERR_PARAM;
4609
4610         rte_free(mem->va);
4611         mem->va = NULL;
4612
4613         return I40E_SUCCESS;
4614 }
4615
4616 void
4617 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4618 {
4619         rte_spinlock_init(&sp->spinlock);
4620 }
4621
4622 void
4623 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4624 {
4625         rte_spinlock_lock(&sp->spinlock);
4626 }
4627
4628 void
4629 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4630 {
4631         rte_spinlock_unlock(&sp->spinlock);
4632 }
4633
4634 void
4635 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4636 {
4637         return;
4638 }
4639
4640 /**
4641  * Get the hardware capabilities, which will be parsed
4642  * and saved into struct i40e_hw.
4643  */
4644 static int
4645 i40e_get_cap(struct i40e_hw *hw)
4646 {
4647         struct i40e_aqc_list_capabilities_element_resp *buf;
4648         uint16_t len, size = 0;
4649         int ret;
4650
4651         /* Calculate a huge enough buff for saving response data temporarily */
4652         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4653                                                 I40E_MAX_CAP_ELE_NUM;
4654         buf = rte_zmalloc("i40e", len, 0);
4655         if (!buf) {
4656                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4657                 return I40E_ERR_NO_MEMORY;
4658         }
4659
4660         /* Get, parse the capabilities and save it to hw */
4661         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4662                         i40e_aqc_opc_list_func_capabilities, NULL);
4663         if (ret != I40E_SUCCESS)
4664                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4665
4666         /* Free the temporary buffer after being used */
4667         rte_free(buf);
4668
4669         return ret;
4670 }
4671
4672 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4673
4674 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4675                 const char *value,
4676                 void *opaque)
4677 {
4678         struct i40e_pf *pf;
4679         unsigned long num;
4680         char *end;
4681
4682         pf = (struct i40e_pf *)opaque;
4683         RTE_SET_USED(key);
4684
4685         errno = 0;
4686         num = strtoul(value, &end, 0);
4687         if (errno != 0 || end == value || *end != 0) {
4688                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4689                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4690                 return -(EINVAL);
4691         }
4692
4693         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4694                 pf->vf_nb_qp_max = (uint16_t)num;
4695         else
4696                 /* here return 0 to make next valid same argument work */
4697                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4698                             "power of 2 and equal or less than 16 !, Now it is "
4699                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4700
4701         return 0;
4702 }
4703
4704 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4705 {
4706         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4707         struct rte_kvargs *kvlist;
4708         int kvargs_count;
4709
4710         /* set default queue number per VF as 4 */
4711         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4712
4713         if (dev->device->devargs == NULL)
4714                 return 0;
4715
4716         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4717         if (kvlist == NULL)
4718                 return -(EINVAL);
4719
4720         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4721         if (!kvargs_count) {
4722                 rte_kvargs_free(kvlist);
4723                 return 0;
4724         }
4725
4726         if (kvargs_count > 1)
4727                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4728                             "the first invalid or last valid one is used !",
4729                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4730
4731         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4732                            i40e_pf_parse_vf_queue_number_handler, pf);
4733
4734         rte_kvargs_free(kvlist);
4735
4736         return 0;
4737 }
4738
4739 static int
4740 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4741 {
4742         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4743         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4745         uint16_t qp_count = 0, vsi_count = 0;
4746
4747         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4748                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4749                 return -EINVAL;
4750         }
4751
4752         i40e_pf_config_vf_rxq_number(dev);
4753
4754         /* Add the parameter init for LFC */
4755         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4756         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4757         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4758
4759         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4760         pf->max_num_vsi = hw->func_caps.num_vsis;
4761         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4762         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4763
4764         /* FDir queue/VSI allocation */
4765         pf->fdir_qp_offset = 0;
4766         if (hw->func_caps.fd) {
4767                 pf->flags |= I40E_FLAG_FDIR;
4768                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4769         } else {
4770                 pf->fdir_nb_qps = 0;
4771         }
4772         qp_count += pf->fdir_nb_qps;
4773         vsi_count += 1;
4774
4775         /* LAN queue/VSI allocation */
4776         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4777         if (!hw->func_caps.rss) {
4778                 pf->lan_nb_qps = 1;
4779         } else {
4780                 pf->flags |= I40E_FLAG_RSS;
4781                 if (hw->mac.type == I40E_MAC_X722)
4782                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4783                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4784         }
4785         qp_count += pf->lan_nb_qps;
4786         vsi_count += 1;
4787
4788         /* VF queue/VSI allocation */
4789         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4790         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4791                 pf->flags |= I40E_FLAG_SRIOV;
4792                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4793                 pf->vf_num = pci_dev->max_vfs;
4794                 PMD_DRV_LOG(DEBUG,
4795                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4796                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4797         } else {
4798                 pf->vf_nb_qps = 0;
4799                 pf->vf_num = 0;
4800         }
4801         qp_count += pf->vf_nb_qps * pf->vf_num;
4802         vsi_count += pf->vf_num;
4803
4804         /* VMDq queue/VSI allocation */
4805         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4806         pf->vmdq_nb_qps = 0;
4807         pf->max_nb_vmdq_vsi = 0;
4808         if (hw->func_caps.vmdq) {
4809                 if (qp_count < hw->func_caps.num_tx_qp &&
4810                         vsi_count < hw->func_caps.num_vsis) {
4811                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4812                                 qp_count) / pf->vmdq_nb_qp_max;
4813
4814                         /* Limit the maximum number of VMDq vsi to the maximum
4815                          * ethdev can support
4816                          */
4817                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4818                                 hw->func_caps.num_vsis - vsi_count);
4819                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4820                                 RTE_ETH_64_POOLS);
4821                         if (pf->max_nb_vmdq_vsi) {
4822                                 pf->flags |= I40E_FLAG_VMDQ;
4823                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4824                                 PMD_DRV_LOG(DEBUG,
4825                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4826                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4827                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4828                         } else {
4829                                 PMD_DRV_LOG(INFO,
4830                                         "No enough queues left for VMDq");
4831                         }
4832                 } else {
4833                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4834                 }
4835         }
4836         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4837         vsi_count += pf->max_nb_vmdq_vsi;
4838
4839         if (hw->func_caps.dcb)
4840                 pf->flags |= I40E_FLAG_DCB;
4841
4842         if (qp_count > hw->func_caps.num_tx_qp) {
4843                 PMD_DRV_LOG(ERR,
4844                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4845                         qp_count, hw->func_caps.num_tx_qp);
4846                 return -EINVAL;
4847         }
4848         if (vsi_count > hw->func_caps.num_vsis) {
4849                 PMD_DRV_LOG(ERR,
4850                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4851                         vsi_count, hw->func_caps.num_vsis);
4852                 return -EINVAL;
4853         }
4854
4855         return 0;
4856 }
4857
4858 static int
4859 i40e_pf_get_switch_config(struct i40e_pf *pf)
4860 {
4861         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4862         struct i40e_aqc_get_switch_config_resp *switch_config;
4863         struct i40e_aqc_switch_config_element_resp *element;
4864         uint16_t start_seid = 0, num_reported;
4865         int ret;
4866
4867         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4868                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4869         if (!switch_config) {
4870                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4871                 return -ENOMEM;
4872         }
4873
4874         /* Get the switch configurations */
4875         ret = i40e_aq_get_switch_config(hw, switch_config,
4876                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4877         if (ret != I40E_SUCCESS) {
4878                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4879                 goto fail;
4880         }
4881         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4882         if (num_reported != 1) { /* The number should be 1 */
4883                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4884                 goto fail;
4885         }
4886
4887         /* Parse the switch configuration elements */
4888         element = &(switch_config->element[0]);
4889         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4890                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4891                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4892         } else
4893                 PMD_DRV_LOG(INFO, "Unknown element type");
4894
4895 fail:
4896         rte_free(switch_config);
4897
4898         return ret;
4899 }
4900
4901 static int
4902 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4903                         uint32_t num)
4904 {
4905         struct pool_entry *entry;
4906
4907         if (pool == NULL || num == 0)
4908                 return -EINVAL;
4909
4910         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4911         if (entry == NULL) {
4912                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4913                 return -ENOMEM;
4914         }
4915
4916         /* queue heap initialize */
4917         pool->num_free = num;
4918         pool->num_alloc = 0;
4919         pool->base = base;
4920         LIST_INIT(&pool->alloc_list);
4921         LIST_INIT(&pool->free_list);
4922
4923         /* Initialize element  */
4924         entry->base = 0;
4925         entry->len = num;
4926
4927         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4928         return 0;
4929 }
4930
4931 static void
4932 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4933 {
4934         struct pool_entry *entry, *next_entry;
4935
4936         if (pool == NULL)
4937                 return;
4938
4939         for (entry = LIST_FIRST(&pool->alloc_list);
4940                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4941                         entry = next_entry) {
4942                 LIST_REMOVE(entry, next);
4943                 rte_free(entry);
4944         }
4945
4946         for (entry = LIST_FIRST(&pool->free_list);
4947                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4948                         entry = next_entry) {
4949                 LIST_REMOVE(entry, next);
4950                 rte_free(entry);
4951         }
4952
4953         pool->num_free = 0;
4954         pool->num_alloc = 0;
4955         pool->base = 0;
4956         LIST_INIT(&pool->alloc_list);
4957         LIST_INIT(&pool->free_list);
4958 }
4959
4960 static int
4961 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4962                        uint32_t base)
4963 {
4964         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4965         uint32_t pool_offset;
4966         uint16_t len;
4967         int insert;
4968
4969         if (pool == NULL) {
4970                 PMD_DRV_LOG(ERR, "Invalid parameter");
4971                 return -EINVAL;
4972         }
4973
4974         pool_offset = base - pool->base;
4975         /* Lookup in alloc list */
4976         LIST_FOREACH(entry, &pool->alloc_list, next) {
4977                 if (entry->base == pool_offset) {
4978                         valid_entry = entry;
4979                         LIST_REMOVE(entry, next);
4980                         break;
4981                 }
4982         }
4983
4984         /* Not find, return */
4985         if (valid_entry == NULL) {
4986                 PMD_DRV_LOG(ERR, "Failed to find entry");
4987                 return -EINVAL;
4988         }
4989
4990         /**
4991          * Found it, move it to free list  and try to merge.
4992          * In order to make merge easier, always sort it by qbase.
4993          * Find adjacent prev and last entries.
4994          */
4995         prev = next = NULL;
4996         LIST_FOREACH(entry, &pool->free_list, next) {
4997                 if (entry->base > valid_entry->base) {
4998                         next = entry;
4999                         break;
5000                 }
5001                 prev = entry;
5002         }
5003
5004         insert = 0;
5005         len = valid_entry->len;
5006         /* Try to merge with next one*/
5007         if (next != NULL) {
5008                 /* Merge with next one */
5009                 if (valid_entry->base + len == next->base) {
5010                         next->base = valid_entry->base;
5011                         next->len += len;
5012                         rte_free(valid_entry);
5013                         valid_entry = next;
5014                         insert = 1;
5015                 }
5016         }
5017
5018         if (prev != NULL) {
5019                 /* Merge with previous one */
5020                 if (prev->base + prev->len == valid_entry->base) {
5021                         prev->len += len;
5022                         /* If it merge with next one, remove next node */
5023                         if (insert == 1) {
5024                                 LIST_REMOVE(valid_entry, next);
5025                                 rte_free(valid_entry);
5026                                 valid_entry = NULL;
5027                         } else {
5028                                 rte_free(valid_entry);
5029                                 valid_entry = NULL;
5030                                 insert = 1;
5031                         }
5032                 }
5033         }
5034
5035         /* Not find any entry to merge, insert */
5036         if (insert == 0) {
5037                 if (prev != NULL)
5038                         LIST_INSERT_AFTER(prev, valid_entry, next);
5039                 else if (next != NULL)
5040                         LIST_INSERT_BEFORE(next, valid_entry, next);
5041                 else /* It's empty list, insert to head */
5042                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5043         }
5044
5045         pool->num_free += len;
5046         pool->num_alloc -= len;
5047
5048         return 0;
5049 }
5050
5051 static int
5052 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5053                        uint16_t num)
5054 {
5055         struct pool_entry *entry, *valid_entry;
5056
5057         if (pool == NULL || num == 0) {
5058                 PMD_DRV_LOG(ERR, "Invalid parameter");
5059                 return -EINVAL;
5060         }
5061
5062         if (pool->num_free < num) {
5063                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5064                             num, pool->num_free);
5065                 return -ENOMEM;
5066         }
5067
5068         valid_entry = NULL;
5069         /* Lookup  in free list and find most fit one */
5070         LIST_FOREACH(entry, &pool->free_list, next) {
5071                 if (entry->len >= num) {
5072                         /* Find best one */
5073                         if (entry->len == num) {
5074                                 valid_entry = entry;
5075                                 break;
5076                         }
5077                         if (valid_entry == NULL || valid_entry->len > entry->len)
5078                                 valid_entry = entry;
5079                 }
5080         }
5081
5082         /* Not find one to satisfy the request, return */
5083         if (valid_entry == NULL) {
5084                 PMD_DRV_LOG(ERR, "No valid entry found");
5085                 return -ENOMEM;
5086         }
5087         /**
5088          * The entry have equal queue number as requested,
5089          * remove it from alloc_list.
5090          */
5091         if (valid_entry->len == num) {
5092                 LIST_REMOVE(valid_entry, next);
5093         } else {
5094                 /**
5095                  * The entry have more numbers than requested,
5096                  * create a new entry for alloc_list and minus its
5097                  * queue base and number in free_list.
5098                  */
5099                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5100                 if (entry == NULL) {
5101                         PMD_DRV_LOG(ERR,
5102                                 "Failed to allocate memory for resource pool");
5103                         return -ENOMEM;
5104                 }
5105                 entry->base = valid_entry->base;
5106                 entry->len = num;
5107                 valid_entry->base += num;
5108                 valid_entry->len -= num;
5109                 valid_entry = entry;
5110         }
5111
5112         /* Insert it into alloc list, not sorted */
5113         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5114
5115         pool->num_free -= valid_entry->len;
5116         pool->num_alloc += valid_entry->len;
5117
5118         return valid_entry->base + pool->base;
5119 }
5120
5121 /**
5122  * bitmap_is_subset - Check whether src2 is subset of src1
5123  **/
5124 static inline int
5125 bitmap_is_subset(uint8_t src1, uint8_t src2)
5126 {
5127         return !((src1 ^ src2) & src2);
5128 }
5129
5130 static enum i40e_status_code
5131 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5132 {
5133         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5134
5135         /* If DCB is not supported, only default TC is supported */
5136         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5137                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5138                 return I40E_NOT_SUPPORTED;
5139         }
5140
5141         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5142                 PMD_DRV_LOG(ERR,
5143                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5144                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5145                 return I40E_NOT_SUPPORTED;
5146         }
5147         return I40E_SUCCESS;
5148 }
5149
5150 int
5151 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5152                                 struct i40e_vsi_vlan_pvid_info *info)
5153 {
5154         struct i40e_hw *hw;
5155         struct i40e_vsi_context ctxt;
5156         uint8_t vlan_flags = 0;
5157         int ret;
5158
5159         if (vsi == NULL || info == NULL) {
5160                 PMD_DRV_LOG(ERR, "invalid parameters");
5161                 return I40E_ERR_PARAM;
5162         }
5163
5164         if (info->on) {
5165                 vsi->info.pvid = info->config.pvid;
5166                 /**
5167                  * If insert pvid is enabled, only tagged pkts are
5168                  * allowed to be sent out.
5169                  */
5170                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5171                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5172         } else {
5173                 vsi->info.pvid = 0;
5174                 if (info->config.reject.tagged == 0)
5175                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5176
5177                 if (info->config.reject.untagged == 0)
5178                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5179         }
5180         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5181                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5182         vsi->info.port_vlan_flags |= vlan_flags;
5183         vsi->info.valid_sections =
5184                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5185         memset(&ctxt, 0, sizeof(ctxt));
5186         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5187         ctxt.seid = vsi->seid;
5188
5189         hw = I40E_VSI_TO_HW(vsi);
5190         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5191         if (ret != I40E_SUCCESS)
5192                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5193
5194         return ret;
5195 }
5196
5197 static int
5198 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5199 {
5200         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5201         int i, ret;
5202         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5203
5204         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5205         if (ret != I40E_SUCCESS)
5206                 return ret;
5207
5208         if (!vsi->seid) {
5209                 PMD_DRV_LOG(ERR, "seid not valid");
5210                 return -EINVAL;
5211         }
5212
5213         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5214         tc_bw_data.tc_valid_bits = enabled_tcmap;
5215         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5216                 tc_bw_data.tc_bw_credits[i] =
5217                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5218
5219         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5220         if (ret != I40E_SUCCESS) {
5221                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5222                 return ret;
5223         }
5224
5225         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5226                                         sizeof(vsi->info.qs_handle));
5227         return I40E_SUCCESS;
5228 }
5229
5230 static enum i40e_status_code
5231 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5232                                  struct i40e_aqc_vsi_properties_data *info,
5233                                  uint8_t enabled_tcmap)
5234 {
5235         enum i40e_status_code ret;
5236         int i, total_tc = 0;
5237         uint16_t qpnum_per_tc, bsf, qp_idx;
5238
5239         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5240         if (ret != I40E_SUCCESS)
5241                 return ret;
5242
5243         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5244                 if (enabled_tcmap & (1 << i))
5245                         total_tc++;
5246         if (total_tc == 0)
5247                 total_tc = 1;
5248         vsi->enabled_tc = enabled_tcmap;
5249
5250         /* Number of queues per enabled TC */
5251         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5252         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5253         bsf = rte_bsf32(qpnum_per_tc);
5254
5255         /* Adjust the queue number to actual queues that can be applied */
5256         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5257                 vsi->nb_qps = qpnum_per_tc * total_tc;
5258
5259         /**
5260          * Configure TC and queue mapping parameters, for enabled TC,
5261          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5262          * default queue will serve it.
5263          */
5264         qp_idx = 0;
5265         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5266                 if (vsi->enabled_tc & (1 << i)) {
5267                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5268                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5269                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5270                         qp_idx += qpnum_per_tc;
5271                 } else
5272                         info->tc_mapping[i] = 0;
5273         }
5274
5275         /* Associate queue number with VSI */
5276         if (vsi->type == I40E_VSI_SRIOV) {
5277                 info->mapping_flags |=
5278                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5279                 for (i = 0; i < vsi->nb_qps; i++)
5280                         info->queue_mapping[i] =
5281                                 rte_cpu_to_le_16(vsi->base_queue + i);
5282         } else {
5283                 info->mapping_flags |=
5284                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5285                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5286         }
5287         info->valid_sections |=
5288                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5289
5290         return I40E_SUCCESS;
5291 }
5292
5293 static int
5294 i40e_veb_release(struct i40e_veb *veb)
5295 {
5296         struct i40e_vsi *vsi;
5297         struct i40e_hw *hw;
5298
5299         if (veb == NULL)
5300                 return -EINVAL;
5301
5302         if (!TAILQ_EMPTY(&veb->head)) {
5303                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5304                 return -EACCES;
5305         }
5306         /* associate_vsi field is NULL for floating VEB */
5307         if (veb->associate_vsi != NULL) {
5308                 vsi = veb->associate_vsi;
5309                 hw = I40E_VSI_TO_HW(vsi);
5310
5311                 vsi->uplink_seid = veb->uplink_seid;
5312                 vsi->veb = NULL;
5313         } else {
5314                 veb->associate_pf->main_vsi->floating_veb = NULL;
5315                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5316         }
5317
5318         i40e_aq_delete_element(hw, veb->seid, NULL);
5319         rte_free(veb);
5320         return I40E_SUCCESS;
5321 }
5322
5323 /* Setup a veb */
5324 static struct i40e_veb *
5325 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5326 {
5327         struct i40e_veb *veb;
5328         int ret;
5329         struct i40e_hw *hw;
5330
5331         if (pf == NULL) {
5332                 PMD_DRV_LOG(ERR,
5333                             "veb setup failed, associated PF shouldn't null");
5334                 return NULL;
5335         }
5336         hw = I40E_PF_TO_HW(pf);
5337
5338         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5339         if (!veb) {
5340                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5341                 goto fail;
5342         }
5343
5344         veb->associate_vsi = vsi;
5345         veb->associate_pf = pf;
5346         TAILQ_INIT(&veb->head);
5347         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5348
5349         /* create floating veb if vsi is NULL */
5350         if (vsi != NULL) {
5351                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5352                                       I40E_DEFAULT_TCMAP, false,
5353                                       &veb->seid, false, NULL);
5354         } else {
5355                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5356                                       true, &veb->seid, false, NULL);
5357         }
5358
5359         if (ret != I40E_SUCCESS) {
5360                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5361                             hw->aq.asq_last_status);
5362                 goto fail;
5363         }
5364         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5365
5366         /* get statistics index */
5367         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5368                                 &veb->stats_idx, NULL, NULL, NULL);
5369         if (ret != I40E_SUCCESS) {
5370                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5371                             hw->aq.asq_last_status);
5372                 goto fail;
5373         }
5374         /* Get VEB bandwidth, to be implemented */
5375         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5376         if (vsi)
5377                 vsi->uplink_seid = veb->seid;
5378
5379         return veb;
5380 fail:
5381         rte_free(veb);
5382         return NULL;
5383 }
5384
5385 int
5386 i40e_vsi_release(struct i40e_vsi *vsi)
5387 {
5388         struct i40e_pf *pf;
5389         struct i40e_hw *hw;
5390         struct i40e_vsi_list *vsi_list;
5391         void *temp;
5392         int ret;
5393         struct i40e_mac_filter *f;
5394         uint16_t user_param;
5395
5396         if (!vsi)
5397                 return I40E_SUCCESS;
5398
5399         if (!vsi->adapter)
5400                 return -EFAULT;
5401
5402         user_param = vsi->user_param;
5403
5404         pf = I40E_VSI_TO_PF(vsi);
5405         hw = I40E_VSI_TO_HW(vsi);
5406
5407         /* VSI has child to attach, release child first */
5408         if (vsi->veb) {
5409                 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5410                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5411                                 return -1;
5412                 }
5413                 i40e_veb_release(vsi->veb);
5414         }
5415
5416         if (vsi->floating_veb) {
5417                 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head,
5418                         list, temp) {
5419                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5420                                 return -1;
5421                 }
5422         }
5423
5424         /* Remove all macvlan filters of the VSI */
5425         i40e_vsi_remove_all_macvlan_filter(vsi);
5426         RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5427                 rte_free(f);
5428
5429         if (vsi->type != I40E_VSI_MAIN &&
5430             ((vsi->type != I40E_VSI_SRIOV) ||
5431             !pf->floating_veb_list[user_param])) {
5432                 /* Remove vsi from parent's sibling list */
5433                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5434                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5435                         return I40E_ERR_PARAM;
5436                 }
5437                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5438                                 &vsi->sib_vsi_list, list);
5439
5440                 /* Remove all switch element of the VSI */
5441                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5442                 if (ret != I40E_SUCCESS)
5443                         PMD_DRV_LOG(ERR, "Failed to delete element");
5444         }
5445
5446         if ((vsi->type == I40E_VSI_SRIOV) &&
5447             pf->floating_veb_list[user_param]) {
5448                 /* Remove vsi from parent's sibling list */
5449                 if (vsi->parent_vsi == NULL ||
5450                     vsi->parent_vsi->floating_veb == NULL) {
5451                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5452                         return I40E_ERR_PARAM;
5453                 }
5454                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5455                              &vsi->sib_vsi_list, list);
5456
5457                 /* Remove all switch element of the VSI */
5458                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5459                 if (ret != I40E_SUCCESS)
5460                         PMD_DRV_LOG(ERR, "Failed to delete element");
5461         }
5462
5463         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5464
5465         if (vsi->type != I40E_VSI_SRIOV)
5466                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5467         rte_free(vsi);
5468
5469         return I40E_SUCCESS;
5470 }
5471
5472 static int
5473 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5474 {
5475         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5476         struct i40e_aqc_remove_macvlan_element_data def_filter;
5477         struct i40e_mac_filter_info filter;
5478         int ret;
5479
5480         if (vsi->type != I40E_VSI_MAIN)
5481                 return I40E_ERR_CONFIG;
5482         memset(&def_filter, 0, sizeof(def_filter));
5483         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5484                                         ETH_ADDR_LEN);
5485         def_filter.vlan_tag = 0;
5486         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5487                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5488         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5489         if (ret != I40E_SUCCESS) {
5490                 struct i40e_mac_filter *f;
5491                 struct rte_ether_addr *mac;
5492
5493                 PMD_DRV_LOG(DEBUG,
5494                             "Cannot remove the default macvlan filter");
5495                 /* It needs to add the permanent mac into mac list */
5496                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5497                 if (f == NULL) {
5498                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5499                         return I40E_ERR_NO_MEMORY;
5500                 }
5501                 mac = &f->mac_info.mac_addr;
5502                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5503                                 ETH_ADDR_LEN);
5504                 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5505                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5506                 vsi->mac_num++;
5507
5508                 return ret;
5509         }
5510         rte_memcpy(&filter.mac_addr,
5511                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5512         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5513         return i40e_vsi_add_mac(vsi, &filter);
5514 }
5515
5516 /*
5517  * i40e_vsi_get_bw_config - Query VSI BW Information
5518  * @vsi: the VSI to be queried
5519  *
5520  * Returns 0 on success, negative value on failure
5521  */
5522 static enum i40e_status_code
5523 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5524 {
5525         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5526         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5527         struct i40e_hw *hw = &vsi->adapter->hw;
5528         i40e_status ret;
5529         int i;
5530         uint32_t bw_max;
5531
5532         memset(&bw_config, 0, sizeof(bw_config));
5533         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5534         if (ret != I40E_SUCCESS) {
5535                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5536                             hw->aq.asq_last_status);
5537                 return ret;
5538         }
5539
5540         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5541         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5542                                         &ets_sla_config, NULL);
5543         if (ret != I40E_SUCCESS) {
5544                 PMD_DRV_LOG(ERR,
5545                         "VSI failed to get TC bandwdith configuration %u",
5546                         hw->aq.asq_last_status);
5547                 return ret;
5548         }
5549
5550         /* store and print out BW info */
5551         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5552         vsi->bw_info.bw_max = bw_config.max_bw;
5553         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5554         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5555         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5556                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5557                      I40E_16_BIT_WIDTH);
5558         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5559                 vsi->bw_info.bw_ets_share_credits[i] =
5560                                 ets_sla_config.share_credits[i];
5561                 vsi->bw_info.bw_ets_credits[i] =
5562                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5563                 /* 4 bits per TC, 4th bit is reserved */
5564                 vsi->bw_info.bw_ets_max[i] =
5565                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5566                                   RTE_LEN2MASK(3, uint8_t));
5567                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5568                             vsi->bw_info.bw_ets_share_credits[i]);
5569                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5570                             vsi->bw_info.bw_ets_credits[i]);
5571                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5572                             vsi->bw_info.bw_ets_max[i]);
5573         }
5574
5575         return I40E_SUCCESS;
5576 }
5577
5578 /* i40e_enable_pf_lb
5579  * @pf: pointer to the pf structure
5580  *
5581  * allow loopback on pf
5582  */
5583 static inline void
5584 i40e_enable_pf_lb(struct i40e_pf *pf)
5585 {
5586         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5587         struct i40e_vsi_context ctxt;
5588         int ret;
5589
5590         /* Use the FW API if FW >= v5.0 */
5591         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5592                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5593                 return;
5594         }
5595
5596         memset(&ctxt, 0, sizeof(ctxt));
5597         ctxt.seid = pf->main_vsi_seid;
5598         ctxt.pf_num = hw->pf_id;
5599         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5600         if (ret) {
5601                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5602                             ret, hw->aq.asq_last_status);
5603                 return;
5604         }
5605         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5606         ctxt.info.valid_sections =
5607                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5608         ctxt.info.switch_id |=
5609                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5610
5611         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5612         if (ret)
5613                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5614                             hw->aq.asq_last_status);
5615 }
5616
5617 /* Setup a VSI */
5618 struct i40e_vsi *
5619 i40e_vsi_setup(struct i40e_pf *pf,
5620                enum i40e_vsi_type type,
5621                struct i40e_vsi *uplink_vsi,
5622                uint16_t user_param)
5623 {
5624         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5625         struct i40e_vsi *vsi;
5626         struct i40e_mac_filter_info filter;
5627         int ret;
5628         struct i40e_vsi_context ctxt;
5629         struct rte_ether_addr broadcast =
5630                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5631
5632         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5633             uplink_vsi == NULL) {
5634                 PMD_DRV_LOG(ERR,
5635                         "VSI setup failed, VSI link shouldn't be NULL");
5636                 return NULL;
5637         }
5638
5639         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5640                 PMD_DRV_LOG(ERR,
5641                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5642                 return NULL;
5643         }
5644
5645         /* two situations
5646          * 1.type is not MAIN and uplink vsi is not NULL
5647          * If uplink vsi didn't setup VEB, create one first under veb field
5648          * 2.type is SRIOV and the uplink is NULL
5649          * If floating VEB is NULL, create one veb under floating veb field
5650          */
5651
5652         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5653             uplink_vsi->veb == NULL) {
5654                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5655
5656                 if (uplink_vsi->veb == NULL) {
5657                         PMD_DRV_LOG(ERR, "VEB setup failed");
5658                         return NULL;
5659                 }
5660                 /* set ALLOWLOOPBACk on pf, when veb is created */
5661                 i40e_enable_pf_lb(pf);
5662         }
5663
5664         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5665             pf->main_vsi->floating_veb == NULL) {
5666                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5667
5668                 if (pf->main_vsi->floating_veb == NULL) {
5669                         PMD_DRV_LOG(ERR, "VEB setup failed");
5670                         return NULL;
5671                 }
5672         }
5673
5674         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5675         if (!vsi) {
5676                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5677                 return NULL;
5678         }
5679         TAILQ_INIT(&vsi->mac_list);
5680         vsi->type = type;
5681         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5682         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5683         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5684         vsi->user_param = user_param;
5685         vsi->vlan_anti_spoof_on = 0;
5686         vsi->vlan_filter_on = 0;
5687         /* Allocate queues */
5688         switch (vsi->type) {
5689         case I40E_VSI_MAIN  :
5690                 vsi->nb_qps = pf->lan_nb_qps;
5691                 break;
5692         case I40E_VSI_SRIOV :
5693                 vsi->nb_qps = pf->vf_nb_qps;
5694                 break;
5695         case I40E_VSI_VMDQ2:
5696                 vsi->nb_qps = pf->vmdq_nb_qps;
5697                 break;
5698         case I40E_VSI_FDIR:
5699                 vsi->nb_qps = pf->fdir_nb_qps;
5700                 break;
5701         default:
5702                 goto fail_mem;
5703         }
5704         /*
5705          * The filter status descriptor is reported in rx queue 0,
5706          * while the tx queue for fdir filter programming has no
5707          * such constraints, can be non-zero queues.
5708          * To simplify it, choose FDIR vsi use queue 0 pair.
5709          * To make sure it will use queue 0 pair, queue allocation
5710          * need be done before this function is called
5711          */
5712         if (type != I40E_VSI_FDIR) {
5713                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5714                         if (ret < 0) {
5715                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5716                                                 vsi->seid, ret);
5717                                 goto fail_mem;
5718                         }
5719                         vsi->base_queue = ret;
5720         } else
5721                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5722
5723         /* VF has MSIX interrupt in VF range, don't allocate here */
5724         if (type == I40E_VSI_MAIN) {
5725                 if (pf->support_multi_driver) {
5726                         /* If support multi-driver, need to use INT0 instead of
5727                          * allocating from msix pool. The Msix pool is init from
5728                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5729                          * to 1 without calling i40e_res_pool_alloc.
5730                          */
5731                         vsi->msix_intr = 0;
5732                         vsi->nb_msix = 1;
5733                 } else {
5734                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5735                                                   RTE_MIN(vsi->nb_qps,
5736                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5737                         if (ret < 0) {
5738                                 PMD_DRV_LOG(ERR,
5739                                             "VSI MAIN %d get heap failed %d",
5740                                             vsi->seid, ret);
5741                                 goto fail_queue_alloc;
5742                         }
5743                         vsi->msix_intr = ret;
5744                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5745                                                RTE_MAX_RXTX_INTR_VEC_ID);
5746                 }
5747         } else if (type != I40E_VSI_SRIOV) {
5748                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5749                 if (ret < 0) {
5750                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5751                         if (type != I40E_VSI_FDIR)
5752                                 goto fail_queue_alloc;
5753                         vsi->msix_intr = 0;
5754                         vsi->nb_msix = 0;
5755                 } else {
5756                         vsi->msix_intr = ret;
5757                         vsi->nb_msix = 1;
5758                 }
5759         } else {
5760                 vsi->msix_intr = 0;
5761                 vsi->nb_msix = 0;
5762         }
5763
5764         /* Add VSI */
5765         if (type == I40E_VSI_MAIN) {
5766                 /* For main VSI, no need to add since it's default one */
5767                 vsi->uplink_seid = pf->mac_seid;
5768                 vsi->seid = pf->main_vsi_seid;
5769                 /* Bind queues with specific MSIX interrupt */
5770                 /**
5771                  * Needs 2 interrupt at least, one for misc cause which will
5772                  * enabled from OS side, Another for queues binding the
5773                  * interrupt from device side only.
5774                  */
5775
5776                 /* Get default VSI parameters from hardware */
5777                 memset(&ctxt, 0, sizeof(ctxt));
5778                 ctxt.seid = vsi->seid;
5779                 ctxt.pf_num = hw->pf_id;
5780                 ctxt.uplink_seid = vsi->uplink_seid;
5781                 ctxt.vf_num = 0;
5782                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5783                 if (ret != I40E_SUCCESS) {
5784                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5785                         goto fail_msix_alloc;
5786                 }
5787                 rte_memcpy(&vsi->info, &ctxt.info,
5788                         sizeof(struct i40e_aqc_vsi_properties_data));
5789                 vsi->vsi_id = ctxt.vsi_number;
5790                 vsi->info.valid_sections = 0;
5791
5792                 /* Configure tc, enabled TC0 only */
5793                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5794                         I40E_SUCCESS) {
5795                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5796                         goto fail_msix_alloc;
5797                 }
5798
5799                 /* TC, queue mapping */
5800                 memset(&ctxt, 0, sizeof(ctxt));
5801                 vsi->info.valid_sections |=
5802                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5803                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5804                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5805                 rte_memcpy(&ctxt.info, &vsi->info,
5806                         sizeof(struct i40e_aqc_vsi_properties_data));
5807                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5808                                                 I40E_DEFAULT_TCMAP);
5809                 if (ret != I40E_SUCCESS) {
5810                         PMD_DRV_LOG(ERR,
5811                                 "Failed to configure TC queue mapping");
5812                         goto fail_msix_alloc;
5813                 }
5814                 ctxt.seid = vsi->seid;
5815                 ctxt.pf_num = hw->pf_id;
5816                 ctxt.uplink_seid = vsi->uplink_seid;
5817                 ctxt.vf_num = 0;
5818
5819                 /* Update VSI parameters */
5820                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5821                 if (ret != I40E_SUCCESS) {
5822                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5823                         goto fail_msix_alloc;
5824                 }
5825
5826                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5827                                                 sizeof(vsi->info.tc_mapping));
5828                 rte_memcpy(&vsi->info.queue_mapping,
5829                                 &ctxt.info.queue_mapping,
5830                         sizeof(vsi->info.queue_mapping));
5831                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5832                 vsi->info.valid_sections = 0;
5833
5834                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5835                                 ETH_ADDR_LEN);
5836
5837                 /**
5838                  * Updating default filter settings are necessary to prevent
5839                  * reception of tagged packets.
5840                  * Some old firmware configurations load a default macvlan
5841                  * filter which accepts both tagged and untagged packets.
5842                  * The updating is to use a normal filter instead if needed.
5843                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5844                  * The firmware with correct configurations load the default
5845                  * macvlan filter which is expected and cannot be removed.
5846                  */
5847                 i40e_update_default_filter_setting(vsi);
5848                 i40e_config_qinq(hw, vsi);
5849         } else if (type == I40E_VSI_SRIOV) {
5850                 memset(&ctxt, 0, sizeof(ctxt));
5851                 /**
5852                  * For other VSI, the uplink_seid equals to uplink VSI's
5853                  * uplink_seid since they share same VEB
5854                  */
5855                 if (uplink_vsi == NULL)
5856                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5857                 else
5858                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5859                 ctxt.pf_num = hw->pf_id;
5860                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5861                 ctxt.uplink_seid = vsi->uplink_seid;
5862                 ctxt.connection_type = 0x1;
5863                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5864
5865                 /* Use the VEB configuration if FW >= v5.0 */
5866                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5867                         /* Configure switch ID */
5868                         ctxt.info.valid_sections |=
5869                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5870                         ctxt.info.switch_id =
5871                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5872                 }
5873
5874                 /* Configure port/vlan */
5875                 ctxt.info.valid_sections |=
5876                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5877                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5878                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5879                                                 hw->func_caps.enabled_tcmap);
5880                 if (ret != I40E_SUCCESS) {
5881                         PMD_DRV_LOG(ERR,
5882                                 "Failed to configure TC queue mapping");
5883                         goto fail_msix_alloc;
5884                 }
5885
5886                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5887                 ctxt.info.valid_sections |=
5888                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5889                 /**
5890                  * Since VSI is not created yet, only configure parameter,
5891                  * will add vsi below.
5892                  */
5893
5894                 i40e_config_qinq(hw, vsi);
5895         } else if (type == I40E_VSI_VMDQ2) {
5896                 memset(&ctxt, 0, sizeof(ctxt));
5897                 /*
5898                  * For other VSI, the uplink_seid equals to uplink VSI's
5899                  * uplink_seid since they share same VEB
5900                  */
5901                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5902                 ctxt.pf_num = hw->pf_id;
5903                 ctxt.vf_num = 0;
5904                 ctxt.uplink_seid = vsi->uplink_seid;
5905                 ctxt.connection_type = 0x1;
5906                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5907
5908                 ctxt.info.valid_sections |=
5909                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5910                 /* user_param carries flag to enable loop back */
5911                 if (user_param) {
5912                         ctxt.info.switch_id =
5913                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5914                         ctxt.info.switch_id |=
5915                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5916                 }
5917
5918                 /* Configure port/vlan */
5919                 ctxt.info.valid_sections |=
5920                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5921                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5922                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5923                                                 I40E_DEFAULT_TCMAP);
5924                 if (ret != I40E_SUCCESS) {
5925                         PMD_DRV_LOG(ERR,
5926                                 "Failed to configure TC queue mapping");
5927                         goto fail_msix_alloc;
5928                 }
5929                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5930                 ctxt.info.valid_sections |=
5931                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5932         } else if (type == I40E_VSI_FDIR) {
5933                 memset(&ctxt, 0, sizeof(ctxt));
5934                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5935                 ctxt.pf_num = hw->pf_id;
5936                 ctxt.vf_num = 0;
5937                 ctxt.uplink_seid = vsi->uplink_seid;
5938                 ctxt.connection_type = 0x1;     /* regular data port */
5939                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5940                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5941                                                 I40E_DEFAULT_TCMAP);
5942                 if (ret != I40E_SUCCESS) {
5943                         PMD_DRV_LOG(ERR,
5944                                 "Failed to configure TC queue mapping.");
5945                         goto fail_msix_alloc;
5946                 }
5947                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5948                 ctxt.info.valid_sections |=
5949                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5950         } else {
5951                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5952                 goto fail_msix_alloc;
5953         }
5954
5955         if (vsi->type != I40E_VSI_MAIN) {
5956                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5957                 if (ret != I40E_SUCCESS) {
5958                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5959                                     hw->aq.asq_last_status);
5960                         goto fail_msix_alloc;
5961                 }
5962                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5963                 vsi->info.valid_sections = 0;
5964                 vsi->seid = ctxt.seid;
5965                 vsi->vsi_id = ctxt.vsi_number;
5966                 vsi->sib_vsi_list.vsi = vsi;
5967                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5968                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5969                                           &vsi->sib_vsi_list, list);
5970                 } else {
5971                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5972                                           &vsi->sib_vsi_list, list);
5973                 }
5974         }
5975
5976         /* MAC/VLAN configuration */
5977         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5978         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5979
5980         ret = i40e_vsi_add_mac(vsi, &filter);
5981         if (ret != I40E_SUCCESS) {
5982                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5983                 goto fail_msix_alloc;
5984         }
5985
5986         /* Get VSI BW information */
5987         i40e_vsi_get_bw_config(vsi);
5988         return vsi;
5989 fail_msix_alloc:
5990         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5991 fail_queue_alloc:
5992         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5993 fail_mem:
5994         rte_free(vsi);
5995         return NULL;
5996 }
5997
5998 /* Configure vlan filter on or off */
5999 int
6000 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6001 {
6002         int i, num;
6003         struct i40e_mac_filter *f;
6004         void *temp;
6005         struct i40e_mac_filter_info *mac_filter;
6006         enum i40e_mac_filter_type desired_filter;
6007         int ret = I40E_SUCCESS;
6008
6009         if (on) {
6010                 /* Filter to match MAC and VLAN */
6011                 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6012         } else {
6013                 /* Filter to match only MAC */
6014                 desired_filter = I40E_MAC_PERFECT_MATCH;
6015         }
6016
6017         num = vsi->mac_num;
6018
6019         mac_filter = rte_zmalloc("mac_filter_info_data",
6020                                  num * sizeof(*mac_filter), 0);
6021         if (mac_filter == NULL) {
6022                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6023                 return I40E_ERR_NO_MEMORY;
6024         }
6025
6026         i = 0;
6027
6028         /* Remove all existing mac */
6029         RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6030                 mac_filter[i] = f->mac_info;
6031                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6032                 if (ret) {
6033                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6034                                     on ? "enable" : "disable");
6035                         goto DONE;
6036                 }
6037                 i++;
6038         }
6039
6040         /* Override with new filter */
6041         for (i = 0; i < num; i++) {
6042                 mac_filter[i].filter_type = desired_filter;
6043                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6044                 if (ret) {
6045                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6046                                     on ? "enable" : "disable");
6047                         goto DONE;
6048                 }
6049         }
6050
6051 DONE:
6052         rte_free(mac_filter);
6053         return ret;
6054 }
6055
6056 /* Configure vlan stripping on or off */
6057 int
6058 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6059 {
6060         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6061         struct i40e_vsi_context ctxt;
6062         uint8_t vlan_flags;
6063         int ret = I40E_SUCCESS;
6064
6065         /* Check if it has been already on or off */
6066         if (vsi->info.valid_sections &
6067                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6068                 if (on) {
6069                         if ((vsi->info.port_vlan_flags &
6070                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6071                                 return 0; /* already on */
6072                 } else {
6073                         if ((vsi->info.port_vlan_flags &
6074                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6075                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6076                                 return 0; /* already off */
6077                 }
6078         }
6079
6080         if (on)
6081                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6082         else
6083                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6084         vsi->info.valid_sections =
6085                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6086         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6087         vsi->info.port_vlan_flags |= vlan_flags;
6088         ctxt.seid = vsi->seid;
6089         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6090         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6091         if (ret)
6092                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6093                             on ? "enable" : "disable");
6094
6095         return ret;
6096 }
6097
6098 static int
6099 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6100 {
6101         struct rte_eth_dev_data *data = dev->data;
6102         int ret;
6103         int mask = 0;
6104
6105         /* Apply vlan offload setting */
6106         mask = RTE_ETH_VLAN_STRIP_MASK |
6107                RTE_ETH_QINQ_STRIP_MASK |
6108                RTE_ETH_VLAN_FILTER_MASK |
6109                RTE_ETH_VLAN_EXTEND_MASK;
6110         ret = i40e_vlan_offload_set(dev, mask);
6111         if (ret) {
6112                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6113                 return ret;
6114         }
6115
6116         /* Apply pvid setting */
6117         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6118                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6119         if (ret)
6120                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6121
6122         return ret;
6123 }
6124
6125 static int
6126 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6127 {
6128         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6129
6130         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6131 }
6132
6133 static int
6134 i40e_update_flow_control(struct i40e_hw *hw)
6135 {
6136 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6137         struct i40e_link_status link_status;
6138         uint32_t rxfc = 0, txfc = 0, reg;
6139         uint8_t an_info;
6140         int ret;
6141
6142         memset(&link_status, 0, sizeof(link_status));
6143         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6144         if (ret != I40E_SUCCESS) {
6145                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6146                 goto write_reg; /* Disable flow control */
6147         }
6148
6149         an_info = hw->phy.link_info.an_info;
6150         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6151                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6152                 ret = I40E_ERR_NOT_READY;
6153                 goto write_reg; /* Disable flow control */
6154         }
6155         /**
6156          * If link auto negotiation is enabled, flow control needs to
6157          * be configured according to it
6158          */
6159         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6160         case I40E_LINK_PAUSE_RXTX:
6161                 rxfc = 1;
6162                 txfc = 1;
6163                 hw->fc.current_mode = I40E_FC_FULL;
6164                 break;
6165         case I40E_AQ_LINK_PAUSE_RX:
6166                 rxfc = 1;
6167                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6168                 break;
6169         case I40E_AQ_LINK_PAUSE_TX:
6170                 txfc = 1;
6171                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6172                 break;
6173         default:
6174                 hw->fc.current_mode = I40E_FC_NONE;
6175                 break;
6176         }
6177
6178 write_reg:
6179         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6180                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6181         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6182         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6183         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6184         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6185
6186         return ret;
6187 }
6188
6189 /* PF setup */
6190 static int
6191 i40e_pf_setup(struct i40e_pf *pf)
6192 {
6193         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6194         struct i40e_filter_control_settings settings;
6195         struct i40e_vsi *vsi;
6196         int ret;
6197
6198         /* Clear all stats counters */
6199         pf->offset_loaded = FALSE;
6200         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6201         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6202         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6203         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6204         pf->rx_err1 = 0;
6205         pf->rx_err1_offset = 0;
6206
6207         ret = i40e_pf_get_switch_config(pf);
6208         if (ret != I40E_SUCCESS) {
6209                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6210                 return ret;
6211         }
6212
6213         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6214         if (ret)
6215                 PMD_INIT_LOG(WARNING,
6216                         "failed to allocate switch domain for device %d", ret);
6217
6218         if (pf->flags & I40E_FLAG_FDIR) {
6219                 /* make queue allocated first, let FDIR use queue pair 0*/
6220                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6221                 if (ret != I40E_FDIR_QUEUE_ID) {
6222                         PMD_DRV_LOG(ERR,
6223                                 "queue allocation fails for FDIR: ret =%d",
6224                                 ret);
6225                         pf->flags &= ~I40E_FLAG_FDIR;
6226                 }
6227         }
6228         /*  main VSI setup */
6229         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6230         if (!vsi) {
6231                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6232                 return I40E_ERR_NOT_READY;
6233         }
6234         pf->main_vsi = vsi;
6235
6236         /* Configure filter control */
6237         memset(&settings, 0, sizeof(settings));
6238         if (hw->func_caps.rss_table_size == RTE_ETH_RSS_RETA_SIZE_128)
6239                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6240         else if (hw->func_caps.rss_table_size == RTE_ETH_RSS_RETA_SIZE_512)
6241                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6242         else {
6243                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6244                         hw->func_caps.rss_table_size);
6245                 return I40E_ERR_PARAM;
6246         }
6247         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6248                 hw->func_caps.rss_table_size);
6249         pf->hash_lut_size = hw->func_caps.rss_table_size;
6250
6251         /* Enable ethtype and macvlan filters */
6252         settings.enable_ethtype = TRUE;
6253         settings.enable_macvlan = TRUE;
6254         ret = i40e_set_filter_control(hw, &settings);
6255         if (ret)
6256                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6257                                                                 ret);
6258
6259         /* Update flow control according to the auto negotiation */
6260         i40e_update_flow_control(hw);
6261
6262         return I40E_SUCCESS;
6263 }
6264
6265 int
6266 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6267 {
6268         uint32_t reg;
6269         uint16_t j;
6270
6271         /**
6272          * Set or clear TX Queue Disable flags,
6273          * which is required by hardware.
6274          */
6275         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6276         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6277
6278         /* Wait until the request is finished */
6279         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6280                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6281                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6282                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6283                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6284                                                         & 0x1))) {
6285                         break;
6286                 }
6287         }
6288         if (on) {
6289                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6290                         return I40E_SUCCESS; /* already on, skip next steps */
6291
6292                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6293                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6294         } else {
6295                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6296                         return I40E_SUCCESS; /* already off, skip next steps */
6297                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6298         }
6299         /* Write the register */
6300         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6301         /* Check the result */
6302         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6303                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6304                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6305                 if (on) {
6306                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6307                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6308                                 break;
6309                 } else {
6310                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6311                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6312                                 break;
6313                 }
6314         }
6315         /* Check if it is timeout */
6316         if (j >= I40E_CHK_Q_ENA_COUNT) {
6317                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6318                             (on ? "enable" : "disable"), q_idx);
6319                 return I40E_ERR_TIMEOUT;
6320         }
6321
6322         return I40E_SUCCESS;
6323 }
6324
6325 int
6326 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6327 {
6328         uint32_t reg;
6329         uint16_t j;
6330
6331         /* Wait until the request is finished */
6332         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6333                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6334                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6335                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6336                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6337                         break;
6338         }
6339
6340         if (on) {
6341                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6342                         return I40E_SUCCESS; /* Already on, skip next steps */
6343                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6344         } else {
6345                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6346                         return I40E_SUCCESS; /* Already off, skip next steps */
6347                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6348         }
6349
6350         /* Write the register */
6351         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6352         /* Check the result */
6353         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6354                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6355                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6356                 if (on) {
6357                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6358                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6359                                 break;
6360                 } else {
6361                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6362                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6363                                 break;
6364                 }
6365         }
6366
6367         /* Check if it is timeout */
6368         if (j >= I40E_CHK_Q_ENA_COUNT) {
6369                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6370                             (on ? "enable" : "disable"), q_idx);
6371                 return I40E_ERR_TIMEOUT;
6372         }
6373
6374         return I40E_SUCCESS;
6375 }
6376
6377 /* Initialize VSI for TX */
6378 static int
6379 i40e_dev_tx_init(struct i40e_pf *pf)
6380 {
6381         struct rte_eth_dev_data *data = pf->dev_data;
6382         uint16_t i;
6383         uint32_t ret = I40E_SUCCESS;
6384         struct i40e_tx_queue *txq;
6385
6386         for (i = 0; i < data->nb_tx_queues; i++) {
6387                 txq = data->tx_queues[i];
6388                 if (!txq || !txq->q_set)
6389                         continue;
6390                 ret = i40e_tx_queue_init(txq);
6391                 if (ret != I40E_SUCCESS)
6392                         break;
6393         }
6394         if (ret == I40E_SUCCESS)
6395                 i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
6396
6397         return ret;
6398 }
6399
6400 /* Initialize VSI for RX */
6401 static int
6402 i40e_dev_rx_init(struct i40e_pf *pf)
6403 {
6404         struct rte_eth_dev_data *data = pf->dev_data;
6405         int ret = I40E_SUCCESS;
6406         uint16_t i;
6407         struct i40e_rx_queue *rxq;
6408
6409         i40e_pf_config_rss(pf);
6410         for (i = 0; i < data->nb_rx_queues; i++) {
6411                 rxq = data->rx_queues[i];
6412                 if (!rxq || !rxq->q_set)
6413                         continue;
6414
6415                 ret = i40e_rx_queue_init(rxq);
6416                 if (ret != I40E_SUCCESS) {
6417                         PMD_DRV_LOG(ERR,
6418                                 "Failed to do RX queue initialization");
6419                         break;
6420                 }
6421         }
6422         if (ret == I40E_SUCCESS)
6423                 i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
6424
6425         return ret;
6426 }
6427
6428 static int
6429 i40e_dev_rxtx_init(struct i40e_pf *pf)
6430 {
6431         int err;
6432
6433         err = i40e_dev_tx_init(pf);
6434         if (err) {
6435                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6436                 return err;
6437         }
6438         err = i40e_dev_rx_init(pf);
6439         if (err) {
6440                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6441                 return err;
6442         }
6443
6444         return err;
6445 }
6446
6447 static int
6448 i40e_vmdq_setup(struct rte_eth_dev *dev)
6449 {
6450         struct rte_eth_conf *conf = &dev->data->dev_conf;
6451         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6452         int i, err, conf_vsis, j, loop;
6453         struct i40e_vsi *vsi;
6454         struct i40e_vmdq_info *vmdq_info;
6455         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6456         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6457
6458         /*
6459          * Disable interrupt to avoid message from VF. Furthermore, it will
6460          * avoid race condition in VSI creation/destroy.
6461          */
6462         i40e_pf_disable_irq0(hw);
6463
6464         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6465                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6466                 return -ENOTSUP;
6467         }
6468
6469         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6470         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6471                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6472                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6473                         pf->max_nb_vmdq_vsi);
6474                 return -ENOTSUP;
6475         }
6476
6477         if (pf->vmdq != NULL) {
6478                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6479                 return 0;
6480         }
6481
6482         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6483                                 sizeof(*vmdq_info) * conf_vsis, 0);
6484
6485         if (pf->vmdq == NULL) {
6486                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6487                 return -ENOMEM;
6488         }
6489
6490         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6491
6492         /* Create VMDQ VSI */
6493         for (i = 0; i < conf_vsis; i++) {
6494                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6495                                 vmdq_conf->enable_loop_back);
6496                 if (vsi == NULL) {
6497                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6498                         err = -1;
6499                         goto err_vsi_setup;
6500                 }
6501                 vmdq_info = &pf->vmdq[i];
6502                 vmdq_info->pf = pf;
6503                 vmdq_info->vsi = vsi;
6504         }
6505         pf->nb_cfg_vmdq_vsi = conf_vsis;
6506
6507         /* Configure Vlan */
6508         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6509         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6510                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6511                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6512                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6513                                         vmdq_conf->pool_map[i].vlan_id, j);
6514
6515                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6516                                                 vmdq_conf->pool_map[i].vlan_id);
6517                                 if (err) {
6518                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6519                                         err = -1;
6520                                         goto err_vsi_setup;
6521                                 }
6522                         }
6523                 }
6524         }
6525
6526         i40e_pf_enable_irq0(hw);
6527
6528         return 0;
6529
6530 err_vsi_setup:
6531         for (i = 0; i < conf_vsis; i++)
6532                 if (pf->vmdq[i].vsi == NULL)
6533                         break;
6534                 else
6535                         i40e_vsi_release(pf->vmdq[i].vsi);
6536
6537         rte_free(pf->vmdq);
6538         pf->vmdq = NULL;
6539         i40e_pf_enable_irq0(hw);
6540         return err;
6541 }
6542
6543 static void
6544 i40e_stat_update_32(struct i40e_hw *hw,
6545                    uint32_t reg,
6546                    bool offset_loaded,
6547                    uint64_t *offset,
6548                    uint64_t *stat)
6549 {
6550         uint64_t new_data;
6551
6552         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6553         if (!offset_loaded)
6554                 *offset = new_data;
6555
6556         if (new_data >= *offset)
6557                 *stat = (uint64_t)(new_data - *offset);
6558         else
6559                 *stat = (uint64_t)((new_data +
6560                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6561 }
6562
6563 static void
6564 i40e_stat_update_48(struct i40e_hw *hw,
6565                    uint32_t hireg,
6566                    uint32_t loreg,
6567                    bool offset_loaded,
6568                    uint64_t *offset,
6569                    uint64_t *stat)
6570 {
6571         uint64_t new_data;
6572
6573         if (hw->device_id == I40E_DEV_ID_QEMU) {
6574                 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6575                 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6576                                 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6577         } else {
6578                 new_data = I40E_READ_REG64(hw, loreg);
6579         }
6580
6581         if (!offset_loaded)
6582                 *offset = new_data;
6583
6584         if (new_data >= *offset)
6585                 *stat = new_data - *offset;
6586         else
6587                 *stat = (uint64_t)((new_data +
6588                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6589
6590         *stat &= I40E_48_BIT_MASK;
6591 }
6592
6593 /* Disable IRQ0 */
6594 void
6595 i40e_pf_disable_irq0(struct i40e_hw *hw)
6596 {
6597         /* Disable all interrupt types */
6598         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6599                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6600         I40E_WRITE_FLUSH(hw);
6601 }
6602
6603 /* Enable IRQ0 */
6604 void
6605 i40e_pf_enable_irq0(struct i40e_hw *hw)
6606 {
6607         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6608                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6609                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6610                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6611         I40E_WRITE_FLUSH(hw);
6612 }
6613
6614 static void
6615 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6616 {
6617         /* read pending request and disable first */
6618         i40e_pf_disable_irq0(hw);
6619         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6620         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6621                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6622
6623         if (no_queue)
6624                 /* Link no queues with irq0 */
6625                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6626                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6627 }
6628
6629 static void
6630 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6631 {
6632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6634         int i;
6635         uint16_t abs_vf_id;
6636         uint32_t index, offset, val;
6637
6638         if (!pf->vfs)
6639                 return;
6640         /**
6641          * Try to find which VF trigger a reset, use absolute VF id to access
6642          * since the reg is global register.
6643          */
6644         for (i = 0; i < pf->vf_num; i++) {
6645                 abs_vf_id = hw->func_caps.vf_base_id + i;
6646                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6647                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6648                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6649                 /* VFR event occurred */
6650                 if (val & (0x1 << offset)) {
6651                         int ret;
6652
6653                         /* Clear the event first */
6654                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6655                                                         (0x1 << offset));
6656                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6657                         /**
6658                          * Only notify a VF reset event occurred,
6659                          * don't trigger another SW reset
6660                          */
6661                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6662                         if (ret != I40E_SUCCESS)
6663                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6664                 }
6665         }
6666 }
6667
6668 static void
6669 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6670 {
6671         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6672         int i;
6673
6674         for (i = 0; i < pf->vf_num; i++)
6675                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6676 }
6677
6678 static void
6679 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6680 {
6681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682         struct i40e_arq_event_info info;
6683         uint16_t pending, opcode;
6684         int ret;
6685
6686         info.buf_len = I40E_AQ_BUF_SZ;
6687         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6688         if (!info.msg_buf) {
6689                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6690                 return;
6691         }
6692
6693         pending = 1;
6694         while (pending) {
6695                 ret = i40e_clean_arq_element(hw, &info, &pending);
6696
6697                 if (ret != I40E_SUCCESS) {
6698                         PMD_DRV_LOG(INFO,
6699                                 "Failed to read msg from AdminQ, aq_err: %u",
6700                                 hw->aq.asq_last_status);
6701                         break;
6702                 }
6703                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6704
6705                 switch (opcode) {
6706                 case i40e_aqc_opc_send_msg_to_pf:
6707                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6708                         i40e_pf_host_handle_vf_msg(dev,
6709                                         rte_le_to_cpu_16(info.desc.retval),
6710                                         rte_le_to_cpu_32(info.desc.cookie_high),
6711                                         rte_le_to_cpu_32(info.desc.cookie_low),
6712                                         info.msg_buf,
6713                                         info.msg_len);
6714                         break;
6715                 case i40e_aqc_opc_get_link_status:
6716                         ret = i40e_dev_link_update(dev, 0);
6717                         if (!ret)
6718                                 rte_eth_dev_callback_process(dev,
6719                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6720                         break;
6721                 default:
6722                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6723                                     opcode);
6724                         break;
6725                 }
6726         }
6727         rte_free(info.msg_buf);
6728 }
6729
6730 static void
6731 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6732 {
6733 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6734 #define I40E_MDD_CLEAR16 0xFFFF
6735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6737         bool mdd_detected = false;
6738         struct i40e_pf_vf *vf;
6739         uint32_t reg;
6740         int i;
6741
6742         /* find what triggered the MDD event */
6743         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6744         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6745                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6746                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6747                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6748                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6749                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6750                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6751                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6752                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6753                                         hw->func_caps.base_queue;
6754                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6755                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6756                                 event, queue, pf_num, vf_num, dev->data->name);
6757                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6758                 mdd_detected = true;
6759         }
6760         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6761         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6762                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6763                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6764                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6765                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6766                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6767                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6768                                         hw->func_caps.base_queue;
6769
6770                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6771                                 "queue %d of function 0x%02x device %s\n",
6772                                         event, queue, func, dev->data->name);
6773                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6774                 mdd_detected = true;
6775         }
6776
6777         if (mdd_detected) {
6778                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6779                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6780                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6781                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6782                 }
6783                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6784                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6785                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6786                                         I40E_MDD_CLEAR16);
6787                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6788                 }
6789         }
6790
6791         /* see if one of the VFs needs its hand slapped */
6792         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6793                 vf = &pf->vfs[i];
6794                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6795                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6796                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6797                                         I40E_MDD_CLEAR16);
6798                         vf->num_mdd_events++;
6799                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6800                                         PRIu64 "times\n",
6801                                         i, vf->num_mdd_events);
6802                 }
6803
6804                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6805                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6806                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6807                                         I40E_MDD_CLEAR16);
6808                         vf->num_mdd_events++;
6809                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6810                                         PRIu64 "times\n",
6811                                         i, vf->num_mdd_events);
6812                 }
6813         }
6814 }
6815
6816 /**
6817  * Interrupt handler triggered by NIC  for handling
6818  * specific interrupt.
6819  *
6820  * @param handle
6821  *  Pointer to interrupt handle.
6822  * @param param
6823  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6824  *
6825  * @return
6826  *  void
6827  */
6828 static void
6829 i40e_dev_interrupt_handler(void *param)
6830 {
6831         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6833         uint32_t icr0;
6834
6835         /* Disable interrupt */
6836         i40e_pf_disable_irq0(hw);
6837
6838         /* read out interrupt causes */
6839         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6840
6841         /* No interrupt event indicated */
6842         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6843                 PMD_DRV_LOG(INFO, "No interrupt event");
6844                 goto done;
6845         }
6846         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6847                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6848         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6849                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6850                 i40e_handle_mdd_event(dev);
6851         }
6852         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6853                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6854         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6855                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6856         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6857                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6858         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6859                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6860         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6861                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6862
6863         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6864                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6865                 i40e_dev_handle_vfr_event(dev);
6866         }
6867         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6868                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6869                 i40e_dev_handle_aq_msg(dev);
6870         }
6871
6872 done:
6873         /* Enable interrupt */
6874         i40e_pf_enable_irq0(hw);
6875 }
6876
6877 static void
6878 i40e_dev_alarm_handler(void *param)
6879 {
6880         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6881         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6882         uint32_t icr0;
6883
6884         /* Disable interrupt */
6885         i40e_pf_disable_irq0(hw);
6886
6887         /* read out interrupt causes */
6888         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6889
6890         /* No interrupt event indicated */
6891         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6892                 goto done;
6893         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6894                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6895         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6896                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6897                 i40e_handle_mdd_event(dev);
6898         }
6899         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6900                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6901         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6902                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6903         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6904                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6905         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6906                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6907         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6908                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6909
6910         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6911                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6912                 i40e_dev_handle_vfr_event(dev);
6913         }
6914         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6915                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6916                 i40e_dev_handle_aq_msg(dev);
6917         }
6918
6919 done:
6920         /* Enable interrupt */
6921         i40e_pf_enable_irq0(hw);
6922         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6923                           i40e_dev_alarm_handler, dev);
6924 }
6925
6926 int
6927 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6928                          struct i40e_macvlan_filter *filter,
6929                          int total)
6930 {
6931         int ele_num, ele_buff_size;
6932         int num, actual_num, i;
6933         uint16_t flags;
6934         int ret = I40E_SUCCESS;
6935         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6936         struct i40e_aqc_add_macvlan_element_data *req_list;
6937
6938         if (filter == NULL  || total == 0)
6939                 return I40E_ERR_PARAM;
6940         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6941         ele_buff_size = hw->aq.asq_buf_size;
6942
6943         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6944         if (req_list == NULL) {
6945                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6946                 return I40E_ERR_NO_MEMORY;
6947         }
6948
6949         num = 0;
6950         do {
6951                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6952                 memset(req_list, 0, ele_buff_size);
6953
6954                 for (i = 0; i < actual_num; i++) {
6955                         rte_memcpy(req_list[i].mac_addr,
6956                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6957                         req_list[i].vlan_tag =
6958                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6959
6960                         switch (filter[num + i].filter_type) {
6961                         case I40E_MAC_PERFECT_MATCH:
6962                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6963                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6964                                 break;
6965                         case I40E_MACVLAN_PERFECT_MATCH:
6966                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6967                                 break;
6968                         case I40E_MAC_HASH_MATCH:
6969                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6970                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6971                                 break;
6972                         case I40E_MACVLAN_HASH_MATCH:
6973                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6974                                 break;
6975                         default:
6976                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6977                                 ret = I40E_ERR_PARAM;
6978                                 goto DONE;
6979                         }
6980
6981                         req_list[i].queue_number = 0;
6982
6983                         req_list[i].flags = rte_cpu_to_le_16(flags);
6984                 }
6985
6986                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6987                                                 actual_num, NULL);
6988                 if (ret != I40E_SUCCESS) {
6989                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6990                         goto DONE;
6991                 }
6992                 num += actual_num;
6993         } while (num < total);
6994
6995 DONE:
6996         rte_free(req_list);
6997         return ret;
6998 }
6999
7000 int
7001 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7002                             struct i40e_macvlan_filter *filter,
7003                             int total)
7004 {
7005         int ele_num, ele_buff_size;
7006         int num, actual_num, i;
7007         uint16_t flags;
7008         int ret = I40E_SUCCESS;
7009         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7010         struct i40e_aqc_remove_macvlan_element_data *req_list;
7011         enum i40e_admin_queue_err aq_status;
7012
7013         if (filter == NULL  || total == 0)
7014                 return I40E_ERR_PARAM;
7015
7016         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7017         ele_buff_size = hw->aq.asq_buf_size;
7018
7019         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7020         if (req_list == NULL) {
7021                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7022                 return I40E_ERR_NO_MEMORY;
7023         }
7024
7025         num = 0;
7026         do {
7027                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7028                 memset(req_list, 0, ele_buff_size);
7029
7030                 for (i = 0; i < actual_num; i++) {
7031                         rte_memcpy(req_list[i].mac_addr,
7032                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7033                         req_list[i].vlan_tag =
7034                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7035
7036                         switch (filter[num + i].filter_type) {
7037                         case I40E_MAC_PERFECT_MATCH:
7038                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7039                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7040                                 break;
7041                         case I40E_MACVLAN_PERFECT_MATCH:
7042                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7043                                 break;
7044                         case I40E_MAC_HASH_MATCH:
7045                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7046                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7047                                 break;
7048                         case I40E_MACVLAN_HASH_MATCH:
7049                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7050                                 break;
7051                         default:
7052                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7053                                 ret = I40E_ERR_PARAM;
7054                                 goto DONE;
7055                         }
7056                         req_list[i].flags = rte_cpu_to_le_16(flags);
7057                 }
7058
7059                 ret = i40e_aq_remove_macvlan_v2(hw, vsi->seid, req_list,
7060                                                 actual_num, NULL, &aq_status);
7061
7062                 if (ret != I40E_SUCCESS) {
7063                         /* Do not report as an error when firmware returns ENOENT */
7064                         if (aq_status == I40E_AQ_RC_ENOENT) {
7065                                 ret = I40E_SUCCESS;
7066                         } else {
7067                                 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7068                                 goto DONE;
7069                         }
7070                 }
7071                 num += actual_num;
7072         } while (num < total);
7073
7074 DONE:
7075         rte_free(req_list);
7076         return ret;
7077 }
7078
7079 /* Find out specific MAC filter */
7080 static struct i40e_mac_filter *
7081 i40e_find_mac_filter(struct i40e_vsi *vsi,
7082                          struct rte_ether_addr *macaddr)
7083 {
7084         struct i40e_mac_filter *f;
7085
7086         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7087                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7088                         return f;
7089         }
7090
7091         return NULL;
7092 }
7093
7094 static bool
7095 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7096                          uint16_t vlan_id)
7097 {
7098         uint32_t vid_idx, vid_bit;
7099
7100         if (vlan_id > RTE_ETH_VLAN_ID_MAX)
7101                 return 0;
7102
7103         vid_idx = I40E_VFTA_IDX(vlan_id);
7104         vid_bit = I40E_VFTA_BIT(vlan_id);
7105
7106         if (vsi->vfta[vid_idx] & vid_bit)
7107                 return 1;
7108         else
7109                 return 0;
7110 }
7111
7112 static void
7113 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7114                        uint16_t vlan_id, bool on)
7115 {
7116         uint32_t vid_idx, vid_bit;
7117
7118         vid_idx = I40E_VFTA_IDX(vlan_id);
7119         vid_bit = I40E_VFTA_BIT(vlan_id);
7120
7121         if (on)
7122                 vsi->vfta[vid_idx] |= vid_bit;
7123         else
7124                 vsi->vfta[vid_idx] &= ~vid_bit;
7125 }
7126
7127 void
7128 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7129                      uint16_t vlan_id, bool on)
7130 {
7131         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7132         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7133         int ret;
7134
7135         if (vlan_id > RTE_ETH_VLAN_ID_MAX)
7136                 return;
7137
7138         i40e_store_vlan_filter(vsi, vlan_id, on);
7139
7140         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7141                 return;
7142
7143         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7144
7145         if (on) {
7146                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7147                                        &vlan_data, 1, NULL);
7148                 if (ret != I40E_SUCCESS)
7149                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7150         } else {
7151                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7152                                           &vlan_data, 1, NULL);
7153                 if (ret != I40E_SUCCESS)
7154                         PMD_DRV_LOG(ERR,
7155                                     "Failed to remove vlan filter");
7156         }
7157 }
7158
7159 /**
7160  * Find all vlan options for specific mac addr,
7161  * return with actual vlan found.
7162  */
7163 int
7164 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7165                            struct i40e_macvlan_filter *mv_f,
7166                            int num, struct rte_ether_addr *addr)
7167 {
7168         int i;
7169         uint32_t j, k;
7170
7171         /**
7172          * Not to use i40e_find_vlan_filter to decrease the loop time,
7173          * although the code looks complex.
7174           */
7175         if (num < vsi->vlan_num)
7176                 return I40E_ERR_PARAM;
7177
7178         i = 0;
7179         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7180                 if (vsi->vfta[j]) {
7181                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7182                                 if (vsi->vfta[j] & (1 << k)) {
7183                                         if (i > num - 1) {
7184                                                 PMD_DRV_LOG(ERR,
7185                                                         "vlan number doesn't match");
7186                                                 return I40E_ERR_PARAM;
7187                                         }
7188                                         rte_memcpy(&mv_f[i].macaddr,
7189                                                         addr, ETH_ADDR_LEN);
7190                                         mv_f[i].vlan_id =
7191                                                 j * I40E_UINT32_BIT_SIZE + k;
7192                                         i++;
7193                                 }
7194                         }
7195                 }
7196         }
7197         return I40E_SUCCESS;
7198 }
7199
7200 static inline int
7201 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7202                            struct i40e_macvlan_filter *mv_f,
7203                            int num,
7204                            uint16_t vlan)
7205 {
7206         int i = 0;
7207         struct i40e_mac_filter *f;
7208
7209         if (num < vsi->mac_num)
7210                 return I40E_ERR_PARAM;
7211
7212         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7213                 if (i > num - 1) {
7214                         PMD_DRV_LOG(ERR, "buffer number not match");
7215                         return I40E_ERR_PARAM;
7216                 }
7217                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7218                                 ETH_ADDR_LEN);
7219                 mv_f[i].vlan_id = vlan;
7220                 mv_f[i].filter_type = f->mac_info.filter_type;
7221                 i++;
7222         }
7223
7224         return I40E_SUCCESS;
7225 }
7226
7227 static int
7228 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7229 {
7230         int i, j, num;
7231         struct i40e_mac_filter *f;
7232         struct i40e_macvlan_filter *mv_f;
7233         int ret = I40E_SUCCESS;
7234
7235         if (vsi == NULL || vsi->mac_num == 0)
7236                 return I40E_ERR_PARAM;
7237
7238         /* Case that no vlan is set */
7239         if (vsi->vlan_num == 0)
7240                 num = vsi->mac_num;
7241         else
7242                 num = vsi->mac_num * vsi->vlan_num;
7243
7244         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7245         if (mv_f == NULL) {
7246                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7247                 return I40E_ERR_NO_MEMORY;
7248         }
7249
7250         i = 0;
7251         if (vsi->vlan_num == 0) {
7252                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7253                         rte_memcpy(&mv_f[i].macaddr,
7254                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7255                         mv_f[i].filter_type = f->mac_info.filter_type;
7256                         mv_f[i].vlan_id = 0;
7257                         i++;
7258                 }
7259         } else {
7260                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7261                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7262                                         vsi->vlan_num, &f->mac_info.mac_addr);
7263                         if (ret != I40E_SUCCESS)
7264                                 goto DONE;
7265                         for (j = i; j < i + vsi->vlan_num; j++)
7266                                 mv_f[j].filter_type = f->mac_info.filter_type;
7267                         i += vsi->vlan_num;
7268                 }
7269         }
7270
7271         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7272 DONE:
7273         rte_free(mv_f);
7274
7275         return ret;
7276 }
7277
7278 int
7279 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7280 {
7281         struct i40e_macvlan_filter *mv_f;
7282         int mac_num;
7283         int ret = I40E_SUCCESS;
7284
7285         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7286                 return I40E_ERR_PARAM;
7287
7288         /* If it's already set, just return */
7289         if (i40e_find_vlan_filter(vsi,vlan))
7290                 return I40E_SUCCESS;
7291
7292         mac_num = vsi->mac_num;
7293
7294         if (mac_num == 0) {
7295                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7296                 return I40E_ERR_PARAM;
7297         }
7298
7299         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7300
7301         if (mv_f == NULL) {
7302                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7303                 return I40E_ERR_NO_MEMORY;
7304         }
7305
7306         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7307
7308         if (ret != I40E_SUCCESS)
7309                 goto DONE;
7310
7311         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7312
7313         if (ret != I40E_SUCCESS)
7314                 goto DONE;
7315
7316         i40e_set_vlan_filter(vsi, vlan, 1);
7317
7318         vsi->vlan_num++;
7319         ret = I40E_SUCCESS;
7320 DONE:
7321         rte_free(mv_f);
7322         return ret;
7323 }
7324
7325 int
7326 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7327 {
7328         struct i40e_macvlan_filter *mv_f;
7329         int mac_num;
7330         int ret = I40E_SUCCESS;
7331
7332         /**
7333          * Vlan 0 is the generic filter for untagged packets
7334          * and can't be removed.
7335          */
7336         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7337                 return I40E_ERR_PARAM;
7338
7339         /* If can't find it, just return */
7340         if (!i40e_find_vlan_filter(vsi, vlan))
7341                 return I40E_ERR_PARAM;
7342
7343         mac_num = vsi->mac_num;
7344
7345         if (mac_num == 0) {
7346                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7347                 return I40E_ERR_PARAM;
7348         }
7349
7350         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7351
7352         if (mv_f == NULL) {
7353                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7354                 return I40E_ERR_NO_MEMORY;
7355         }
7356
7357         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7358
7359         if (ret != I40E_SUCCESS)
7360                 goto DONE;
7361
7362         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7363
7364         if (ret != I40E_SUCCESS)
7365                 goto DONE;
7366
7367         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7368         if (vsi->vlan_num == 1) {
7369                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7370                 if (ret != I40E_SUCCESS)
7371                         goto DONE;
7372
7373                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7374                 if (ret != I40E_SUCCESS)
7375                         goto DONE;
7376         }
7377
7378         i40e_set_vlan_filter(vsi, vlan, 0);
7379
7380         vsi->vlan_num--;
7381         ret = I40E_SUCCESS;
7382 DONE:
7383         rte_free(mv_f);
7384         return ret;
7385 }
7386
7387 int
7388 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7389 {
7390         struct i40e_mac_filter *f;
7391         struct i40e_macvlan_filter *mv_f;
7392         int i, vlan_num = 0;
7393         int ret = I40E_SUCCESS;
7394
7395         /* If it's add and we've config it, return */
7396         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7397         if (f != NULL)
7398                 return I40E_SUCCESS;
7399         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7400                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7401
7402                 /**
7403                  * If vlan_num is 0, that's the first time to add mac,
7404                  * set mask for vlan_id 0.
7405                  */
7406                 if (vsi->vlan_num == 0) {
7407                         i40e_set_vlan_filter(vsi, 0, 1);
7408                         vsi->vlan_num = 1;
7409                 }
7410                 vlan_num = vsi->vlan_num;
7411         } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7412                         mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7413                 vlan_num = 1;
7414
7415         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7416         if (mv_f == NULL) {
7417                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7418                 return I40E_ERR_NO_MEMORY;
7419         }
7420
7421         for (i = 0; i < vlan_num; i++) {
7422                 mv_f[i].filter_type = mac_filter->filter_type;
7423                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7424                                 ETH_ADDR_LEN);
7425         }
7426
7427         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7428                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7429                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7430                                         &mac_filter->mac_addr);
7431                 if (ret != I40E_SUCCESS)
7432                         goto DONE;
7433         }
7434
7435         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7436         if (ret != I40E_SUCCESS)
7437                 goto DONE;
7438
7439         /* Add the mac addr into mac list */
7440         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7441         if (f == NULL) {
7442                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7443                 ret = I40E_ERR_NO_MEMORY;
7444                 goto DONE;
7445         }
7446         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7447                         ETH_ADDR_LEN);
7448         f->mac_info.filter_type = mac_filter->filter_type;
7449         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7450         vsi->mac_num++;
7451
7452         ret = I40E_SUCCESS;
7453 DONE:
7454         rte_free(mv_f);
7455
7456         return ret;
7457 }
7458
7459 int
7460 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7461 {
7462         struct i40e_mac_filter *f;
7463         struct i40e_macvlan_filter *mv_f;
7464         int i, vlan_num;
7465         enum i40e_mac_filter_type filter_type;
7466         int ret = I40E_SUCCESS;
7467
7468         /* Can't find it, return an error */
7469         f = i40e_find_mac_filter(vsi, addr);
7470         if (f == NULL)
7471                 return I40E_ERR_PARAM;
7472
7473         vlan_num = vsi->vlan_num;
7474         filter_type = f->mac_info.filter_type;
7475         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7476                 filter_type == I40E_MACVLAN_HASH_MATCH) {
7477                 if (vlan_num == 0) {
7478                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7479                         return I40E_ERR_PARAM;
7480                 }
7481         } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7482                         filter_type == I40E_MAC_HASH_MATCH)
7483                 vlan_num = 1;
7484
7485         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7486         if (mv_f == NULL) {
7487                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7488                 return I40E_ERR_NO_MEMORY;
7489         }
7490
7491         for (i = 0; i < vlan_num; i++) {
7492                 mv_f[i].filter_type = filter_type;
7493                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7494                                 ETH_ADDR_LEN);
7495         }
7496         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7497                         filter_type == I40E_MACVLAN_HASH_MATCH) {
7498                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7499                 if (ret != I40E_SUCCESS)
7500                         goto DONE;
7501         }
7502
7503         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7504         if (ret != I40E_SUCCESS)
7505                 goto DONE;
7506
7507         /* Remove the mac addr into mac list */
7508         TAILQ_REMOVE(&vsi->mac_list, f, next);
7509         rte_free(f);
7510         vsi->mac_num--;
7511
7512         ret = I40E_SUCCESS;
7513 DONE:
7514         rte_free(mv_f);
7515         return ret;
7516 }
7517
7518 /* Configure hash enable flags for RSS */
7519 uint64_t
7520 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7521 {
7522         uint64_t hena = 0;
7523         int i;
7524
7525         if (!flags)
7526                 return hena;
7527
7528         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7529                 if (flags & (1ULL << i))
7530                         hena |= adapter->pctypes_tbl[i];
7531         }
7532
7533         return hena;
7534 }
7535
7536 /* Parse the hash enable flags */
7537 uint64_t
7538 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7539 {
7540         uint64_t rss_hf = 0;
7541
7542         if (!flags)
7543                 return rss_hf;
7544         int i;
7545
7546         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7547                 if (flags & adapter->pctypes_tbl[i])
7548                         rss_hf |= (1ULL << i);
7549         }
7550         return rss_hf;
7551 }
7552
7553 /* Disable RSS */
7554 void
7555 i40e_pf_disable_rss(struct i40e_pf *pf)
7556 {
7557         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7558
7559         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7560         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7561         I40E_WRITE_FLUSH(hw);
7562 }
7563
7564 int
7565 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7566 {
7567         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7568         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7569         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7570                            I40E_VFQF_HKEY_MAX_INDEX :
7571                            I40E_PFQF_HKEY_MAX_INDEX;
7572
7573         if (!key || key_len == 0) {
7574                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7575                 return 0;
7576         } else if (key_len != (key_idx + 1) *
7577                 sizeof(uint32_t)) {
7578                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7579                 return -EINVAL;
7580         }
7581
7582         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7583                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7584                                 (struct i40e_aqc_get_set_rss_key_data *)key;
7585                 enum i40e_status_code status =
7586                                 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7587
7588                 if (status) {
7589                         PMD_DRV_LOG(ERR,
7590                                     "Failed to configure RSS key via AQ, error status: %d",
7591                                     status);
7592                         return -EIO;
7593                 }
7594         } else {
7595                 uint32_t *hash_key = (uint32_t *)key;
7596                 uint16_t i;
7597
7598                 if (vsi->type == I40E_VSI_SRIOV) {
7599                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7600                                 I40E_WRITE_REG(
7601                                         hw,
7602                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7603                                         hash_key[i]);
7604
7605                 } else {
7606                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7607                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7608                                                hash_key[i]);
7609                 }
7610                 I40E_WRITE_FLUSH(hw);
7611         }
7612
7613         return 0;
7614 }
7615
7616 static int
7617 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7618 {
7619         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7620         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7621         uint32_t reg;
7622         int ret;
7623
7624         if (!key || !key_len)
7625                 return 0;
7626
7627         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7628                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7629                         (struct i40e_aqc_get_set_rss_key_data *)key);
7630                 if (ret) {
7631                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7632                         return ret;
7633                 }
7634         } else {
7635                 uint32_t *key_dw = (uint32_t *)key;
7636                 uint16_t i;
7637
7638                 if (vsi->type == I40E_VSI_SRIOV) {
7639                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7640                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7641                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7642                         }
7643                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7644                                    sizeof(uint32_t);
7645                 } else {
7646                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7647                                 reg = I40E_PFQF_HKEY(i);
7648                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7649                         }
7650                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7651                                    sizeof(uint32_t);
7652                 }
7653         }
7654         return 0;
7655 }
7656
7657 static int
7658 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7659 {
7660         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7661         uint64_t hena;
7662         int ret;
7663
7664         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7665                                rss_conf->rss_key_len);
7666         if (ret)
7667                 return ret;
7668
7669         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7670         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7671         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7672         I40E_WRITE_FLUSH(hw);
7673
7674         return 0;
7675 }
7676
7677 static int
7678 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7679                          struct rte_eth_rss_conf *rss_conf)
7680 {
7681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7683         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7684         uint64_t hena;
7685
7686         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7687         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7688
7689         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7690                 if (rss_hf != 0) /* Enable RSS */
7691                         return -EINVAL;
7692                 return 0; /* Nothing to do */
7693         }
7694         /* RSS enabled */
7695         if (rss_hf == 0) /* Disable RSS */
7696                 return -EINVAL;
7697
7698         return i40e_hw_rss_hash_set(pf, rss_conf);
7699 }
7700
7701 static int
7702 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7703                            struct rte_eth_rss_conf *rss_conf)
7704 {
7705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7707         uint64_t hena;
7708         int ret;
7709
7710         if (!rss_conf)
7711                 return -EINVAL;
7712
7713         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7714                          &rss_conf->rss_key_len);
7715         if (ret)
7716                 return ret;
7717
7718         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7719         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7720         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7721
7722         return 0;
7723 }
7724
7725 static int
7726 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7727 {
7728         switch (filter_type) {
7729         case RTE_ETH_TUNNEL_FILTER_IMAC_IVLAN:
7730                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7731                 break;
7732         case RTE_ETH_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7733                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7734                 break;
7735         case RTE_ETH_TUNNEL_FILTER_IMAC_TENID:
7736                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7737                 break;
7738         case RTE_ETH_TUNNEL_FILTER_OMAC_TENID_IMAC:
7739                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7740                 break;
7741         case RTE_ETH_TUNNEL_FILTER_IMAC:
7742                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7743                 break;
7744         case RTE_ETH_TUNNEL_FILTER_OIP:
7745                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7746                 break;
7747         case RTE_ETH_TUNNEL_FILTER_IIP:
7748                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7749                 break;
7750         default:
7751                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7752                 return -EINVAL;
7753         }
7754
7755         return 0;
7756 }
7757
7758 /* Convert tunnel filter structure */
7759 static int
7760 i40e_tunnel_filter_convert(
7761         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7762         struct i40e_tunnel_filter *tunnel_filter)
7763 {
7764         rte_ether_addr_copy((struct rte_ether_addr *)
7765                         &cld_filter->element.outer_mac,
7766                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7767         rte_ether_addr_copy((struct rte_ether_addr *)
7768                         &cld_filter->element.inner_mac,
7769                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7770         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7771         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7772              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7773             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7774                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7775         else
7776                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7777         tunnel_filter->input.flags = cld_filter->element.flags;
7778         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7779         tunnel_filter->queue = cld_filter->element.queue_number;
7780         rte_memcpy(tunnel_filter->input.general_fields,
7781                    cld_filter->general_fields,
7782                    sizeof(cld_filter->general_fields));
7783
7784         return 0;
7785 }
7786
7787 /* Check if there exists the tunnel filter */
7788 struct i40e_tunnel_filter *
7789 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7790                              const struct i40e_tunnel_filter_input *input)
7791 {
7792         int ret;
7793
7794         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7795         if (ret < 0)
7796                 return NULL;
7797
7798         return tunnel_rule->hash_map[ret];
7799 }
7800
7801 /* Add a tunnel filter into the SW list */
7802 static int
7803 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7804                              struct i40e_tunnel_filter *tunnel_filter)
7805 {
7806         struct i40e_tunnel_rule *rule = &pf->tunnel;
7807         int ret;
7808
7809         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7810         if (ret < 0) {
7811                 PMD_DRV_LOG(ERR,
7812                             "Failed to insert tunnel filter to hash table %d!",
7813                             ret);
7814                 return ret;
7815         }
7816         rule->hash_map[ret] = tunnel_filter;
7817
7818         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7819
7820         return 0;
7821 }
7822
7823 /* Delete a tunnel filter from the SW list */
7824 int
7825 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7826                           struct i40e_tunnel_filter_input *input)
7827 {
7828         struct i40e_tunnel_rule *rule = &pf->tunnel;
7829         struct i40e_tunnel_filter *tunnel_filter;
7830         int ret;
7831
7832         ret = rte_hash_del_key(rule->hash_table, input);
7833         if (ret < 0) {
7834                 PMD_DRV_LOG(ERR,
7835                             "Failed to delete tunnel filter to hash table %d!",
7836                             ret);
7837                 return ret;
7838         }
7839         tunnel_filter = rule->hash_map[ret];
7840         rule->hash_map[ret] = NULL;
7841
7842         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7843         rte_free(tunnel_filter);
7844
7845         return 0;
7846 }
7847
7848 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7849 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7850 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7851 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7852 #define I40E_TR_GRE_KEY_MASK                    0x400
7853 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7854 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7855 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7856 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7857 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7858 #define I40E_DIRECTION_INGRESS_KEY              0x8000
7859 #define I40E_TR_L4_TYPE_TCP                     0x2
7860 #define I40E_TR_L4_TYPE_UDP                     0x4
7861 #define I40E_TR_L4_TYPE_SCTP                    0x8
7862
7863 static enum
7864 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7865 {
7866         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7867         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7868         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7869         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7870         enum i40e_status_code status = I40E_SUCCESS;
7871
7872         if (pf->support_multi_driver) {
7873                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7874                 return I40E_NOT_SUPPORTED;
7875         }
7876
7877         memset(&filter_replace, 0,
7878                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7879         memset(&filter_replace_buf, 0,
7880                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7881
7882         /* create L1 filter */
7883         filter_replace.old_filter_type =
7884                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7885         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7886         filter_replace.tr_bit = 0;
7887
7888         /* Prepare the buffer, 3 entries */
7889         filter_replace_buf.data[0] =
7890                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7891         filter_replace_buf.data[0] |=
7892                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7893         filter_replace_buf.data[2] = 0xFF;
7894         filter_replace_buf.data[3] = 0xFF;
7895         filter_replace_buf.data[4] =
7896                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7897         filter_replace_buf.data[4] |=
7898                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7899         filter_replace_buf.data[7] = 0xF0;
7900         filter_replace_buf.data[8]
7901                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7902         filter_replace_buf.data[8] |=
7903                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7904         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7905                 I40E_TR_GENEVE_KEY_MASK |
7906                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7907         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7908                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7909                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7910
7911         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7912                                                &filter_replace_buf);
7913         if (!status && (filter_replace.old_filter_type !=
7914                         filter_replace.new_filter_type))
7915                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7916                             " original: 0x%x, new: 0x%x",
7917                             dev->device->name,
7918                             filter_replace.old_filter_type,
7919                             filter_replace.new_filter_type);
7920
7921         return status;
7922 }
7923
7924 static enum
7925 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7926 {
7927         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7928         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7929         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7930         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7931         enum i40e_status_code status = I40E_SUCCESS;
7932
7933         if (pf->support_multi_driver) {
7934                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7935                 return I40E_NOT_SUPPORTED;
7936         }
7937
7938         /* For MPLSoUDP */
7939         memset(&filter_replace, 0,
7940                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7941         memset(&filter_replace_buf, 0,
7942                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7943         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7944                 I40E_AQC_MIRROR_CLOUD_FILTER;
7945         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7946         filter_replace.new_filter_type =
7947                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7948         /* Prepare the buffer, 2 entries */
7949         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7950         filter_replace_buf.data[0] |=
7951                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7952         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7953         filter_replace_buf.data[4] |=
7954                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7955         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7956                                                &filter_replace_buf);
7957         if (status < 0)
7958                 return status;
7959         if (filter_replace.old_filter_type !=
7960             filter_replace.new_filter_type)
7961                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7962                             " original: 0x%x, new: 0x%x",
7963                             dev->device->name,
7964                             filter_replace.old_filter_type,
7965                             filter_replace.new_filter_type);
7966
7967         /* For MPLSoGRE */
7968         memset(&filter_replace, 0,
7969                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7970         memset(&filter_replace_buf, 0,
7971                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7972
7973         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7974                 I40E_AQC_MIRROR_CLOUD_FILTER;
7975         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7976         filter_replace.new_filter_type =
7977                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7978         /* Prepare the buffer, 2 entries */
7979         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7980         filter_replace_buf.data[0] |=
7981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7982         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7983         filter_replace_buf.data[4] |=
7984                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7985
7986         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7987                                                &filter_replace_buf);
7988         if (!status && (filter_replace.old_filter_type !=
7989                         filter_replace.new_filter_type))
7990                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7991                             " original: 0x%x, new: 0x%x",
7992                             dev->device->name,
7993                             filter_replace.old_filter_type,
7994                             filter_replace.new_filter_type);
7995
7996         return status;
7997 }
7998
7999 static enum i40e_status_code
8000 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8001 {
8002         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8003         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8004         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8005         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8006         enum i40e_status_code status = I40E_SUCCESS;
8007
8008         if (pf->support_multi_driver) {
8009                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8010                 return I40E_NOT_SUPPORTED;
8011         }
8012
8013         /* For GTP-C */
8014         memset(&filter_replace, 0,
8015                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8016         memset(&filter_replace_buf, 0,
8017                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8018         /* create L1 filter */
8019         filter_replace.old_filter_type =
8020                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8021         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8022         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8023                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8024         /* Prepare the buffer, 2 entries */
8025         filter_replace_buf.data[0] =
8026                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8027         filter_replace_buf.data[0] |=
8028                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8029         filter_replace_buf.data[2] = 0xFF;
8030         filter_replace_buf.data[3] = 0xFF;
8031         filter_replace_buf.data[4] =
8032                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8033         filter_replace_buf.data[4] |=
8034                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8035         filter_replace_buf.data[6] = 0xFF;
8036         filter_replace_buf.data[7] = 0xFF;
8037         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8038                                                &filter_replace_buf);
8039         if (status < 0)
8040                 return status;
8041         if (filter_replace.old_filter_type !=
8042             filter_replace.new_filter_type)
8043                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8044                             " original: 0x%x, new: 0x%x",
8045                             dev->device->name,
8046                             filter_replace.old_filter_type,
8047                             filter_replace.new_filter_type);
8048
8049         /* for GTP-U */
8050         memset(&filter_replace, 0,
8051                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8052         memset(&filter_replace_buf, 0,
8053                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8054         /* create L1 filter */
8055         filter_replace.old_filter_type =
8056                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8057         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8058         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8059                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8060         /* Prepare the buffer, 2 entries */
8061         filter_replace_buf.data[0] =
8062                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8063         filter_replace_buf.data[0] |=
8064                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8065         filter_replace_buf.data[2] = 0xFF;
8066         filter_replace_buf.data[3] = 0xFF;
8067         filter_replace_buf.data[4] =
8068                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8069         filter_replace_buf.data[4] |=
8070                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8071         filter_replace_buf.data[6] = 0xFF;
8072         filter_replace_buf.data[7] = 0xFF;
8073
8074         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8075                                                &filter_replace_buf);
8076         if (!status && (filter_replace.old_filter_type !=
8077                         filter_replace.new_filter_type))
8078                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8079                             " original: 0x%x, new: 0x%x",
8080                             dev->device->name,
8081                             filter_replace.old_filter_type,
8082                             filter_replace.new_filter_type);
8083
8084         return status;
8085 }
8086
8087 static enum
8088 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8089 {
8090         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8091         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8092         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8093         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8094         enum i40e_status_code status = I40E_SUCCESS;
8095
8096         if (pf->support_multi_driver) {
8097                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8098                 return I40E_NOT_SUPPORTED;
8099         }
8100
8101         /* for GTP-C */
8102         memset(&filter_replace, 0,
8103                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8104         memset(&filter_replace_buf, 0,
8105                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8106         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8107         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8108         filter_replace.new_filter_type =
8109                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8110         /* Prepare the buffer, 2 entries */
8111         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8112         filter_replace_buf.data[0] |=
8113                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8114         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8115         filter_replace_buf.data[4] |=
8116                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8117         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8118                                                &filter_replace_buf);
8119         if (status < 0)
8120                 return status;
8121         if (filter_replace.old_filter_type !=
8122             filter_replace.new_filter_type)
8123                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8124                             " original: 0x%x, new: 0x%x",
8125                             dev->device->name,
8126                             filter_replace.old_filter_type,
8127                             filter_replace.new_filter_type);
8128
8129         /* for GTP-U */
8130         memset(&filter_replace, 0,
8131                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8132         memset(&filter_replace_buf, 0,
8133                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8134         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8135         filter_replace.old_filter_type =
8136                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8137         filter_replace.new_filter_type =
8138                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8139         /* Prepare the buffer, 2 entries */
8140         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8141         filter_replace_buf.data[0] |=
8142                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8143         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8144         filter_replace_buf.data[4] |=
8145                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8146
8147         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8148                                                &filter_replace_buf);
8149         if (!status && (filter_replace.old_filter_type !=
8150                         filter_replace.new_filter_type))
8151                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8152                             " original: 0x%x, new: 0x%x",
8153                             dev->device->name,
8154                             filter_replace.old_filter_type,
8155                             filter_replace.new_filter_type);
8156
8157         return status;
8158 }
8159
8160 static enum i40e_status_code
8161 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8162                             enum i40e_l4_port_type l4_port_type)
8163 {
8164         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8165         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8166         enum i40e_status_code status = I40E_SUCCESS;
8167         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8168         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8169
8170         if (pf->support_multi_driver) {
8171                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8172                 return I40E_NOT_SUPPORTED;
8173         }
8174
8175         memset(&filter_replace, 0,
8176                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8177         memset(&filter_replace_buf, 0,
8178                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8179
8180         /* create L1 filter */
8181         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8182                 filter_replace.old_filter_type =
8183                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8184                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8185                 filter_replace_buf.data[8] =
8186                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8187         } else {
8188                 filter_replace.old_filter_type =
8189                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8190                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8191                 filter_replace_buf.data[8] =
8192                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8193         }
8194
8195         filter_replace.tr_bit = 0;
8196         /* Prepare the buffer, 3 entries */
8197         filter_replace_buf.data[0] =
8198                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8199         filter_replace_buf.data[0] |=
8200                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8201         filter_replace_buf.data[2] = 0x00;
8202         filter_replace_buf.data[3] =
8203                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8204         filter_replace_buf.data[4] =
8205                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8206         filter_replace_buf.data[4] |=
8207                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8208         filter_replace_buf.data[5] = 0x00;
8209         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8210                 I40E_TR_L4_TYPE_TCP |
8211                 I40E_TR_L4_TYPE_SCTP;
8212         filter_replace_buf.data[7] = 0x00;
8213         filter_replace_buf.data[8] |=
8214                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8215         filter_replace_buf.data[9] = 0x00;
8216         filter_replace_buf.data[10] = 0xFF;
8217         filter_replace_buf.data[11] = 0xFF;
8218
8219         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8220                                                &filter_replace_buf);
8221         if (!status && filter_replace.old_filter_type !=
8222             filter_replace.new_filter_type)
8223                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8224                             " original: 0x%x, new: 0x%x",
8225                             dev->device->name,
8226                             filter_replace.old_filter_type,
8227                             filter_replace.new_filter_type);
8228
8229         return status;
8230 }
8231
8232 static enum i40e_status_code
8233 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8234                                enum i40e_l4_port_type l4_port_type)
8235 {
8236         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8237         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8238         enum i40e_status_code status = I40E_SUCCESS;
8239         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8240         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8241
8242         if (pf->support_multi_driver) {
8243                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8244                 return I40E_NOT_SUPPORTED;
8245         }
8246
8247         memset(&filter_replace, 0,
8248                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8249         memset(&filter_replace_buf, 0,
8250                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8251
8252         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8253                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8254                 filter_replace.new_filter_type =
8255                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8256                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8257         } else {
8258                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8259                 filter_replace.new_filter_type =
8260                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8261                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8262         }
8263
8264         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8265         filter_replace.tr_bit = 0;
8266         /* Prepare the buffer, 2 entries */
8267         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8268         filter_replace_buf.data[0] |=
8269                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8270         filter_replace_buf.data[4] |=
8271                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8272         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8273                                                &filter_replace_buf);
8274
8275         if (!status && filter_replace.old_filter_type !=
8276             filter_replace.new_filter_type)
8277                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8278                             " original: 0x%x, new: 0x%x",
8279                             dev->device->name,
8280                             filter_replace.old_filter_type,
8281                             filter_replace.new_filter_type);
8282
8283         return status;
8284 }
8285
8286 int
8287 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8288                       struct i40e_tunnel_filter_conf *tunnel_filter,
8289                       uint8_t add)
8290 {
8291         uint16_t ip_type;
8292         uint32_t ipv4_addr, ipv4_addr_le;
8293         uint8_t i, tun_type = 0;
8294         /* internal variable to convert ipv6 byte order */
8295         uint32_t convert_ipv6[4];
8296         int val, ret = 0;
8297         struct i40e_pf_vf *vf = NULL;
8298         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8299         struct i40e_vsi *vsi;
8300         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8301         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8302         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8303         struct i40e_tunnel_filter *tunnel, *node;
8304         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8305         uint32_t teid_le;
8306         bool big_buffer = 0;
8307
8308         cld_filter = rte_zmalloc("tunnel_filter",
8309                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8310                          0);
8311
8312         if (cld_filter == NULL) {
8313                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8314                 return -ENOMEM;
8315         }
8316         pfilter = cld_filter;
8317
8318         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8319                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8320         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8321                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8322
8323         pfilter->element.inner_vlan =
8324                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8325         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8326                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8327                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8328                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8329                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8330                                 &ipv4_addr_le,
8331                                 sizeof(pfilter->element.ipaddr.v4.data));
8332         } else {
8333                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8334                 for (i = 0; i < 4; i++) {
8335                         convert_ipv6[i] =
8336                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8337                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8338                 }
8339                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8340                            &convert_ipv6,
8341                            sizeof(pfilter->element.ipaddr.v6.data));
8342         }
8343
8344         /* check tunneled type */
8345         switch (tunnel_filter->tunnel_type) {
8346         case I40E_TUNNEL_TYPE_VXLAN:
8347                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8348                 break;
8349         case I40E_TUNNEL_TYPE_NVGRE:
8350                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8351                 break;
8352         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8353                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8354                 break;
8355         case I40E_TUNNEL_TYPE_MPLSoUDP:
8356                 if (!pf->mpls_replace_flag) {
8357                         i40e_replace_mpls_l1_filter(pf);
8358                         i40e_replace_mpls_cloud_filter(pf);
8359                         pf->mpls_replace_flag = 1;
8360                 }
8361                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8362                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8363                         teid_le >> 4;
8364                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8365                         (teid_le & 0xF) << 12;
8366                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8367                         0x40;
8368                 big_buffer = 1;
8369                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8370                 break;
8371         case I40E_TUNNEL_TYPE_MPLSoGRE:
8372                 if (!pf->mpls_replace_flag) {
8373                         i40e_replace_mpls_l1_filter(pf);
8374                         i40e_replace_mpls_cloud_filter(pf);
8375                         pf->mpls_replace_flag = 1;
8376                 }
8377                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8378                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8379                         teid_le >> 4;
8380                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8381                         (teid_le & 0xF) << 12;
8382                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8383                         0x0;
8384                 big_buffer = 1;
8385                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8386                 break;
8387         case I40E_TUNNEL_TYPE_GTPC:
8388                 if (!pf->gtp_replace_flag) {
8389                         i40e_replace_gtp_l1_filter(pf);
8390                         i40e_replace_gtp_cloud_filter(pf);
8391                         pf->gtp_replace_flag = 1;
8392                 }
8393                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8394                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8395                         (teid_le >> 16) & 0xFFFF;
8396                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8397                         teid_le & 0xFFFF;
8398                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8399                         0x0;
8400                 big_buffer = 1;
8401                 break;
8402         case I40E_TUNNEL_TYPE_GTPU:
8403                 if (!pf->gtp_replace_flag) {
8404                         i40e_replace_gtp_l1_filter(pf);
8405                         i40e_replace_gtp_cloud_filter(pf);
8406                         pf->gtp_replace_flag = 1;
8407                 }
8408                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8409                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8410                         (teid_le >> 16) & 0xFFFF;
8411                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8412                         teid_le & 0xFFFF;
8413                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8414                         0x0;
8415                 big_buffer = 1;
8416                 break;
8417         case I40E_TUNNEL_TYPE_QINQ:
8418                 if (!pf->qinq_replace_flag) {
8419                         ret = i40e_cloud_filter_qinq_create(pf);
8420                         if (ret < 0)
8421                                 PMD_DRV_LOG(DEBUG,
8422                                             "QinQ tunnel filter already created.");
8423                         pf->qinq_replace_flag = 1;
8424                 }
8425                 /*      Add in the General fields the values of
8426                  *      the Outer and Inner VLAN
8427                  *      Big Buffer should be set, see changes in
8428                  *      i40e_aq_add_cloud_filters
8429                  */
8430                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8431                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8432                 big_buffer = 1;
8433                 break;
8434         case I40E_CLOUD_TYPE_UDP:
8435         case I40E_CLOUD_TYPE_TCP:
8436         case I40E_CLOUD_TYPE_SCTP:
8437                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8438                         if (!pf->sport_replace_flag) {
8439                                 i40e_replace_port_l1_filter(pf,
8440                                                 tunnel_filter->l4_port_type);
8441                                 i40e_replace_port_cloud_filter(pf,
8442                                                 tunnel_filter->l4_port_type);
8443                                 pf->sport_replace_flag = 1;
8444                         }
8445                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8446                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8447                                 I40E_DIRECTION_INGRESS_KEY;
8448
8449                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8450                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8451                                         I40E_TR_L4_TYPE_UDP;
8452                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8453                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8454                                         I40E_TR_L4_TYPE_TCP;
8455                         else
8456                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8457                                         I40E_TR_L4_TYPE_SCTP;
8458
8459                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8460                                 (teid_le >> 16) & 0xFFFF;
8461                         big_buffer = 1;
8462                 } else {
8463                         if (!pf->dport_replace_flag) {
8464                                 i40e_replace_port_l1_filter(pf,
8465                                                 tunnel_filter->l4_port_type);
8466                                 i40e_replace_port_cloud_filter(pf,
8467                                                 tunnel_filter->l4_port_type);
8468                                 pf->dport_replace_flag = 1;
8469                         }
8470                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8471                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8472                                 I40E_DIRECTION_INGRESS_KEY;
8473
8474                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8475                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8476                                         I40E_TR_L4_TYPE_UDP;
8477                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8478                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8479                                         I40E_TR_L4_TYPE_TCP;
8480                         else
8481                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8482                                         I40E_TR_L4_TYPE_SCTP;
8483
8484                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8485                                 (teid_le >> 16) & 0xFFFF;
8486                         big_buffer = 1;
8487                 }
8488
8489                 break;
8490         default:
8491                 /* Other tunnel types is not supported. */
8492                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8493                 rte_free(cld_filter);
8494                 return -EINVAL;
8495         }
8496
8497         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8498                 pfilter->element.flags =
8499                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8500         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8501                 pfilter->element.flags =
8502                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8503         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8504                 pfilter->element.flags =
8505                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8506         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8507                 pfilter->element.flags =
8508                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8509         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8510                 pfilter->element.flags |=
8511                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8512         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8513                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8514                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8515                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8516                         pfilter->element.flags |=
8517                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8518                 else
8519                         pfilter->element.flags |=
8520                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8521         } else {
8522                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8523                                                 &pfilter->element.flags);
8524                 if (val < 0) {
8525                         rte_free(cld_filter);
8526                         return -EINVAL;
8527                 }
8528         }
8529
8530         pfilter->element.flags |= rte_cpu_to_le_16(
8531                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8532                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8533         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8534         pfilter->element.queue_number =
8535                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8536
8537         if (!tunnel_filter->is_to_vf)
8538                 vsi = pf->main_vsi;
8539         else {
8540                 if (tunnel_filter->vf_id >= pf->vf_num) {
8541                         PMD_DRV_LOG(ERR, "Invalid argument.");
8542                         rte_free(cld_filter);
8543                         return -EINVAL;
8544                 }
8545                 vf = &pf->vfs[tunnel_filter->vf_id];
8546                 vsi = vf->vsi;
8547         }
8548
8549         /* Check if there is the filter in SW list */
8550         memset(&check_filter, 0, sizeof(check_filter));
8551         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8552         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8553         check_filter.vf_id = tunnel_filter->vf_id;
8554         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8555         if (add && node) {
8556                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8557                 rte_free(cld_filter);
8558                 return -EINVAL;
8559         }
8560
8561         if (!add && !node) {
8562                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8563                 rte_free(cld_filter);
8564                 return -EINVAL;
8565         }
8566
8567         if (add) {
8568                 if (big_buffer)
8569                         ret = i40e_aq_add_cloud_filters_bb(hw,
8570                                                    vsi->seid, cld_filter, 1);
8571                 else
8572                         ret = i40e_aq_add_cloud_filters(hw,
8573                                         vsi->seid, &cld_filter->element, 1);
8574                 if (ret < 0) {
8575                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8576                         rte_free(cld_filter);
8577                         return -ENOTSUP;
8578                 }
8579                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8580                 if (tunnel == NULL) {
8581                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8582                         rte_free(cld_filter);
8583                         return -ENOMEM;
8584                 }
8585
8586                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8587                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8588                 if (ret < 0)
8589                         rte_free(tunnel);
8590         } else {
8591                 if (big_buffer)
8592                         ret = i40e_aq_rem_cloud_filters_bb(
8593                                 hw, vsi->seid, cld_filter, 1);
8594                 else
8595                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8596                                                 &cld_filter->element, 1);
8597                 if (ret < 0) {
8598                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8599                         rte_free(cld_filter);
8600                         return -ENOTSUP;
8601                 }
8602                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8603         }
8604
8605         rte_free(cld_filter);
8606         return ret;
8607 }
8608
8609 static int
8610 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8611 {
8612         uint8_t i;
8613
8614         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8615                 if (pf->vxlan_ports[i] == port)
8616                         return i;
8617         }
8618
8619         return -1;
8620 }
8621
8622 static int
8623 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8624 {
8625         int  idx, ret;
8626         uint8_t filter_idx = 0;
8627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8628
8629         idx = i40e_get_vxlan_port_idx(pf, port);
8630
8631         /* Check if port already exists */
8632         if (idx >= 0) {
8633                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8634                 return -EINVAL;
8635         }
8636
8637         /* Now check if there is space to add the new port */
8638         idx = i40e_get_vxlan_port_idx(pf, 0);
8639         if (idx < 0) {
8640                 PMD_DRV_LOG(ERR,
8641                         "Maximum number of UDP ports reached, not adding port %d",
8642                         port);
8643                 return -ENOSPC;
8644         }
8645
8646         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8647                                         &filter_idx, NULL);
8648         if (ret < 0) {
8649                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8650                 return -1;
8651         }
8652
8653         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8654                          port,  filter_idx);
8655
8656         /* New port: add it and mark its index in the bitmap */
8657         pf->vxlan_ports[idx] = port;
8658         pf->vxlan_bitmap |= (1 << idx);
8659
8660         if (!(pf->flags & I40E_FLAG_VXLAN))
8661                 pf->flags |= I40E_FLAG_VXLAN;
8662
8663         return 0;
8664 }
8665
8666 static int
8667 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8668 {
8669         int idx;
8670         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8671
8672         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8673                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8674                 return -EINVAL;
8675         }
8676
8677         idx = i40e_get_vxlan_port_idx(pf, port);
8678
8679         if (idx < 0) {
8680                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8681                 return -EINVAL;
8682         }
8683
8684         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8685                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8686                 return -1;
8687         }
8688
8689         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8690                         port, idx);
8691
8692         pf->vxlan_ports[idx] = 0;
8693         pf->vxlan_bitmap &= ~(1 << idx);
8694
8695         if (!pf->vxlan_bitmap)
8696                 pf->flags &= ~I40E_FLAG_VXLAN;
8697
8698         return 0;
8699 }
8700
8701 /* Add UDP tunneling port */
8702 static int
8703 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8704                              struct rte_eth_udp_tunnel *udp_tunnel)
8705 {
8706         int ret = 0;
8707         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8708
8709         if (udp_tunnel == NULL)
8710                 return -EINVAL;
8711
8712         switch (udp_tunnel->prot_type) {
8713         case RTE_ETH_TUNNEL_TYPE_VXLAN:
8714                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8715                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8716                 break;
8717         case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE:
8718                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8719                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8720                 break;
8721         case RTE_ETH_TUNNEL_TYPE_GENEVE:
8722         case RTE_ETH_TUNNEL_TYPE_TEREDO:
8723                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8724                 ret = -1;
8725                 break;
8726
8727         default:
8728                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8729                 ret = -1;
8730                 break;
8731         }
8732
8733         return ret;
8734 }
8735
8736 /* Remove UDP tunneling port */
8737 static int
8738 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8739                              struct rte_eth_udp_tunnel *udp_tunnel)
8740 {
8741         int ret = 0;
8742         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8743
8744         if (udp_tunnel == NULL)
8745                 return -EINVAL;
8746
8747         switch (udp_tunnel->prot_type) {
8748         case RTE_ETH_TUNNEL_TYPE_VXLAN:
8749         case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE:
8750                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8751                 break;
8752         case RTE_ETH_TUNNEL_TYPE_GENEVE:
8753         case RTE_ETH_TUNNEL_TYPE_TEREDO:
8754                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8755                 ret = -1;
8756                 break;
8757         default:
8758                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8759                 ret = -1;
8760                 break;
8761         }
8762
8763         return ret;
8764 }
8765
8766 /* Calculate the maximum number of contiguous PF queues that are configured */
8767 int
8768 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8769 {
8770         struct rte_eth_dev_data *data = pf->dev_data;
8771         int i, num;
8772         struct i40e_rx_queue *rxq;
8773
8774         num = 0;
8775         for (i = 0; i < pf->lan_nb_qps; i++) {
8776                 rxq = data->rx_queues[i];
8777                 if (rxq && rxq->q_set)
8778                         num++;
8779                 else
8780                         break;
8781         }
8782
8783         return num;
8784 }
8785
8786 /* Reset the global configure of hash function and input sets */
8787 static void
8788 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8789 {
8790         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8791         uint32_t reg, reg_val;
8792         int i;
8793
8794         /* Reset global RSS function sets */
8795         reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8796         if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8797                 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8798                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8799         }
8800
8801         for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8802                 uint64_t inset;
8803                 int j, pctype;
8804
8805                 if (hw->mac.type == I40E_MAC_X722)
8806                         pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8807                 else
8808                         pctype = i;
8809
8810                 /* Reset pctype insets */
8811                 inset = i40e_get_default_input_set(i);
8812                 if (inset) {
8813                         pf->hash_input_set[pctype] = inset;
8814                         inset = i40e_translate_input_set_reg(hw->mac.type,
8815                                                              inset);
8816
8817                         reg = I40E_GLQF_HASH_INSET(0, pctype);
8818                         i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8819                         reg = I40E_GLQF_HASH_INSET(1, pctype);
8820                         i40e_check_write_global_reg(hw, reg,
8821                                                     (uint32_t)(inset >> 32));
8822
8823                         /* Clear unused mask registers of the pctype */
8824                         for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8825                                 reg = I40E_GLQF_HASH_MSK(j, pctype);
8826                                 i40e_check_write_global_reg(hw, reg, 0);
8827                         }
8828                 }
8829
8830                 /* Reset pctype symmetric sets */
8831                 reg = I40E_GLQF_HSYM(pctype);
8832                 reg_val = i40e_read_rx_ctl(hw, reg);
8833                 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8834                         reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8835                         i40e_write_global_rx_ctl(hw, reg, reg_val);
8836                 }
8837         }
8838         I40E_WRITE_FLUSH(hw);
8839 }
8840
8841 int
8842 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8843 {
8844         struct i40e_hw *hw = &pf->adapter->hw;
8845         uint8_t lut[RTE_ETH_RSS_RETA_SIZE_512];
8846         uint32_t i;
8847         int num;
8848
8849         /* If both VMDQ and RSS enabled, not all of PF queues are
8850          * configured. It's necessary to calculate the actual PF
8851          * queues that are configured.
8852          */
8853         if (pf->dev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG)
8854                 num = i40e_pf_calc_configured_queues_num(pf);
8855         else
8856                 num = pf->dev_data->nb_rx_queues;
8857
8858         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8859         if (num <= 0)
8860                 return 0;
8861
8862         for (i = 0; i < hw->func_caps.rss_table_size; i++)
8863                 lut[i] = (uint8_t)(i % (uint32_t)num);
8864
8865         return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8866 }
8867
8868 int
8869 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8870 {
8871         const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8872                         sizeof(uint32_t);
8873         uint8_t *rss_key;
8874
8875         /* Reset key */
8876         rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8877         if (!rss_key ||
8878             pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8879                 static uint32_t rss_key_default[] = {0x6b793944,
8880                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8881                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8882                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8883
8884                 rss_key = (uint8_t *)rss_key_default;
8885         }
8886
8887         return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8888 }
8889
8890 static int
8891 i40e_pf_rss_reset(struct i40e_pf *pf)
8892 {
8893         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8894
8895         int ret;
8896
8897         pf->hash_filter_enabled = 0;
8898         i40e_pf_disable_rss(pf);
8899         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8900
8901         if (!pf->support_multi_driver)
8902                 i40e_pf_global_rss_reset(pf);
8903
8904         /* Reset RETA table */
8905         if (pf->adapter->rss_reta_updated == 0) {
8906                 ret = i40e_pf_reset_rss_reta(pf);
8907                 if (ret)
8908                         return ret;
8909         }
8910
8911         return i40e_pf_reset_rss_key(pf);
8912 }
8913
8914 /* Configure RSS */
8915 int
8916 i40e_pf_config_rss(struct i40e_pf *pf)
8917 {
8918         struct i40e_hw *hw;
8919         enum rte_eth_rx_mq_mode mq_mode;
8920         uint64_t rss_hf, hena;
8921         int ret;
8922
8923         ret = i40e_pf_rss_reset(pf);
8924         if (ret) {
8925                 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8926                 return ret;
8927         }
8928
8929         rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8930         mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8931         if (!(rss_hf & pf->adapter->flow_types_mask) ||
8932             !(mq_mode & RTE_ETH_MQ_RX_RSS_FLAG))
8933                 return 0;
8934
8935         hw = I40E_PF_TO_HW(pf);
8936         hena = i40e_config_hena(pf->adapter, rss_hf);
8937         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8938         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8939         I40E_WRITE_FLUSH(hw);
8940
8941         return 0;
8942 }
8943
8944 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8945 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8946 int
8947 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8948 {
8949         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8950         uint32_t val, reg;
8951         int ret = -EINVAL;
8952
8953         if (pf->support_multi_driver) {
8954                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8955                 return -ENOTSUP;
8956         }
8957
8958         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8959         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8960
8961         if (len == 3) {
8962                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8963         } else if (len == 4) {
8964                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8965         } else {
8966                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8967                 return ret;
8968         }
8969
8970         if (reg != val) {
8971                 ret = i40e_aq_debug_write_global_register(hw,
8972                                                    I40E_GL_PRS_FVBM(2),
8973                                                    reg, NULL);
8974                 if (ret != 0)
8975                         return ret;
8976                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8977                             "with value 0x%08x",
8978                             I40E_GL_PRS_FVBM(2), reg);
8979         } else {
8980                 ret = 0;
8981         }
8982         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8983                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8984
8985         return ret;
8986 }
8987
8988 /* Set the symmetric hash enable configurations per port */
8989 void
8990 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8991 {
8992         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8993
8994         if (enable > 0) {
8995                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
8996                         return;
8997
8998                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8999         } else {
9000                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9001                         return;
9002
9003                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9004         }
9005         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9006         I40E_WRITE_FLUSH(hw);
9007 }
9008
9009 /**
9010  * Valid input sets for hash and flow director filters per PCTYPE
9011  */
9012 static uint64_t
9013 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9014                 enum rte_filter_type filter)
9015 {
9016         uint64_t valid;
9017
9018         static const uint64_t valid_hash_inset_table[] = {
9019                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9020                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9021                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9022                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9023                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9024                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9025                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9026                         I40E_INSET_FLEX_PAYLOAD,
9027                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9028                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9029                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9030                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9031                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9032                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9033                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9034                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9035                         I40E_INSET_FLEX_PAYLOAD,
9036                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9037                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9038                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9039                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9040                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9041                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9042                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9043                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9044                         I40E_INSET_FLEX_PAYLOAD,
9045                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9046                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9047                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9048                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9049                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9050                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9051                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9052                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9053                         I40E_INSET_FLEX_PAYLOAD,
9054                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9055                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9056                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9057                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9058                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9059                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9060                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9061                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9062                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9063                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9064                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9065                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9066                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9067                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9068                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9069                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9070                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9071                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9072                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9076                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9077                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9078                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9079                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9080                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9081                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9082                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9083                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9084                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9085                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9086                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9087                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9088                         I40E_INSET_FLEX_PAYLOAD,
9089                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9090                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9091                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9092                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9093                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9094                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9095                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9096                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9097                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9098                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9099                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9100                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9101                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9102                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9103                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9104                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9105                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9109                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9110                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9111                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9112                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9113                         I40E_INSET_FLEX_PAYLOAD,
9114                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9118                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9119                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9120                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9121                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9122                         I40E_INSET_FLEX_PAYLOAD,
9123                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9127                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9128                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9129                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9130                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9131                         I40E_INSET_FLEX_PAYLOAD,
9132                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9136                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9137                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9138                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9139                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9140                         I40E_INSET_FLEX_PAYLOAD,
9141                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9145                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9146                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9147                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9148                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9149                         I40E_INSET_FLEX_PAYLOAD,
9150                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9151                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9152                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9153                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9154                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9155                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9156                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9157                         I40E_INSET_FLEX_PAYLOAD,
9158                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9159                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9160                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9161                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9162                         I40E_INSET_FLEX_PAYLOAD,
9163         };
9164
9165         /**
9166          * Flow director supports only fields defined in
9167          * union rte_eth_fdir_flow.
9168          */
9169         static const uint64_t valid_fdir_inset_table[] = {
9170                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9171                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9173                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9174                 I40E_INSET_IPV4_TTL,
9175                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9176                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9177                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9178                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9179                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9180                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9181                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9183                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9184                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9185                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9186                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9187                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9188                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9189                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9190                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9191                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9192                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9193                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9194                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9195                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9196                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9197                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9198                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9199                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9200                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9201                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9202                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9203                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9204                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9205                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9206                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9207                 I40E_INSET_SCTP_VT,
9208                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9209                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9210                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9211                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9212                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9213                 I40E_INSET_IPV4_TTL,
9214                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9215                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9216                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9217                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9218                 I40E_INSET_IPV6_HOP_LIMIT,
9219                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9220                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9221                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9222                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9223                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9224                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9225                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9226                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9227                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9228                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9229                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9230                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9231                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9232                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9233                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9234                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9235                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9236                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9237                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9238                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9239                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9240                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9241                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9242                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9243                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9244                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9245                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9246                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9247                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9248                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9249                 I40E_INSET_SCTP_VT,
9250                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9251                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9252                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9253                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9254                 I40E_INSET_IPV6_HOP_LIMIT,
9255                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9256                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257                 I40E_INSET_LAST_ETHER_TYPE,
9258         };
9259
9260         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9261                 return 0;
9262         if (filter == RTE_ETH_FILTER_HASH)
9263                 valid = valid_hash_inset_table[pctype];
9264         else
9265                 valid = valid_fdir_inset_table[pctype];
9266
9267         return valid;
9268 }
9269
9270 /**
9271  * Validate if the input set is allowed for a specific PCTYPE
9272  */
9273 int
9274 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9275                 enum rte_filter_type filter, uint64_t inset)
9276 {
9277         uint64_t valid;
9278
9279         valid = i40e_get_valid_input_set(pctype, filter);
9280         if (inset & (~valid))
9281                 return -EINVAL;
9282
9283         return 0;
9284 }
9285
9286 /* default input set fields combination per pctype */
9287 uint64_t
9288 i40e_get_default_input_set(uint16_t pctype)
9289 {
9290         static const uint64_t default_inset_table[] = {
9291                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9292                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9293                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9294                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9295                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9297                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9298                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9299                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9300                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9301                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9302                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9303                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9304                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9305                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9306                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9307                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9308                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9309                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9310                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9311                         I40E_INSET_SCTP_VT,
9312                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9313                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9314                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9315                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9316                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9317                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9318                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9319                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9320                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9321                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9322                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9323                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9324                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9325                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9326                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9327                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9328                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9329                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9330                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9331                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9332                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9333                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9334                         I40E_INSET_SCTP_VT,
9335                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9336                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9337                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9338                         I40E_INSET_LAST_ETHER_TYPE,
9339         };
9340
9341         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9342                 return 0;
9343
9344         return default_inset_table[pctype];
9345 }
9346
9347 /**
9348  * Translate the input set from bit masks to register aware bit masks
9349  * and vice versa
9350  */
9351 uint64_t
9352 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9353 {
9354         uint64_t val = 0;
9355         uint16_t i;
9356
9357         struct inset_map {
9358                 uint64_t inset;
9359                 uint64_t inset_reg;
9360         };
9361
9362         static const struct inset_map inset_map_common[] = {
9363                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9364                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9365                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9366                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9367                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9368                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9369                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9370                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9371                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9372                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9373                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9374                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9375                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9376                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9377                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9378                 {I40E_INSET_TUNNEL_DMAC,
9379                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9380                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9381                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9382                 {I40E_INSET_TUNNEL_SRC_PORT,
9383                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9384                 {I40E_INSET_TUNNEL_DST_PORT,
9385                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9386                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9387                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9388                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9389                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9390                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9391                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9392                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9393                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9394                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9395         };
9396
9397     /* some different registers map in x722*/
9398         static const struct inset_map inset_map_diff_x722[] = {
9399                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9400                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9401                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9402                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9403         };
9404
9405         static const struct inset_map inset_map_diff_not_x722[] = {
9406                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9407                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9408                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9409                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9410         };
9411
9412         if (input == 0)
9413                 return val;
9414
9415         /* Translate input set to register aware inset */
9416         if (type == I40E_MAC_X722) {
9417                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9418                         if (input & inset_map_diff_x722[i].inset)
9419                                 val |= inset_map_diff_x722[i].inset_reg;
9420                 }
9421         } else {
9422                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9423                         if (input & inset_map_diff_not_x722[i].inset)
9424                                 val |= inset_map_diff_not_x722[i].inset_reg;
9425                 }
9426         }
9427
9428         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9429                 if (input & inset_map_common[i].inset)
9430                         val |= inset_map_common[i].inset_reg;
9431         }
9432
9433         return val;
9434 }
9435
9436 static int
9437 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9438                             uint32_t pit_reg_count, uint32_t hdr_off)
9439 {
9440         const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9441         uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9442         uint32_t i, reg_val, src_off, count;
9443
9444         for (i = pit_reg_start; i < pit_reg_end; i++) {
9445                 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9446
9447                 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9448                 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9449
9450                 if (src_off <= field_off && (src_off + count) > field_off)
9451                         break;
9452         }
9453
9454         if (i >= pit_reg_end) {
9455                 PMD_DRV_LOG(ERR,
9456                             "Hardware GLQF_PIT configuration does not support this field mask");
9457                 return -1;
9458         }
9459
9460         return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9461 }
9462
9463 int
9464 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9465                              uint32_t *mask, uint8_t nb_elem)
9466 {
9467         static const uint64_t mask_inset[] = {
9468                 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9469                 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9470
9471         static const struct {
9472                 uint64_t inset;
9473                 uint32_t mask;
9474                 uint32_t offset;
9475         } inset_mask_offset_map[] = {
9476                 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9477                   offsetof(struct rte_ipv4_hdr, type_of_service) },
9478
9479                 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9480                   offsetof(struct rte_ipv4_hdr, next_proto_id) },
9481
9482                 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9483                   offsetof(struct rte_ipv4_hdr, time_to_live) },
9484
9485                 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9486                   offsetof(struct rte_ipv6_hdr, vtc_flow) },
9487
9488                 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9489                   offsetof(struct rte_ipv6_hdr, proto) },
9490
9491                 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9492                   offsetof(struct rte_ipv6_hdr, hop_limits) },
9493         };
9494
9495         uint32_t i;
9496         int idx = 0;
9497
9498         assert(mask);
9499         if (!inset)
9500                 return 0;
9501
9502         for (i = 0; i < RTE_DIM(mask_inset); i++) {
9503                 /* Clear the inset bit, if no MASK is required,
9504                  * for example proto + ttl
9505                  */
9506                 if ((mask_inset[i] & inset) == mask_inset[i]) {
9507                         inset &= ~mask_inset[i];
9508                         if (!inset)
9509                                 return 0;
9510                 }
9511         }
9512
9513         for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9514                 uint32_t pit_start, pit_count;
9515                 int offset;
9516
9517                 if (!(inset_mask_offset_map[i].inset & inset))
9518                         continue;
9519
9520                 if (inset_mask_offset_map[i].inset &
9521                     (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9522                      I40E_INSET_IPV4_TTL)) {
9523                         pit_start = I40E_GLQF_PIT_IPV4_START;
9524                         pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9525                 } else {
9526                         pit_start = I40E_GLQF_PIT_IPV6_START;
9527                         pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9528                 }
9529
9530                 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9531                                 inset_mask_offset_map[i].offset);
9532
9533                 if (offset < 0)
9534                         return -EINVAL;
9535
9536                 if (idx >= nb_elem) {
9537                         PMD_DRV_LOG(ERR,
9538                                     "Configuration of inset mask out of range %u",
9539                                     nb_elem);
9540                         return -ERANGE;
9541                 }
9542
9543                 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9544                                                 inset_mask_offset_map[i].mask);
9545                 idx++;
9546         }
9547
9548         return idx;
9549 }
9550
9551 void
9552 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9553 {
9554         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9555
9556         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9557         if (reg != val)
9558                 i40e_write_rx_ctl(hw, addr, val);
9559         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9560                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9561 }
9562
9563 void
9564 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9565 {
9566         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9567         struct rte_eth_dev_data *dev_data =
9568                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
9569         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
9570
9571         if (reg != val) {
9572                 i40e_write_rx_ctl(hw, addr, val);
9573                 PMD_DRV_LOG(WARNING,
9574                             "i40e device %s changed global register [0x%08x]."
9575                             " original: 0x%08x, new: 0x%08x",
9576                             dev->device->name, addr, reg,
9577                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9578         }
9579 }
9580
9581 static void
9582 i40e_filter_input_set_init(struct i40e_pf *pf)
9583 {
9584         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9585         enum i40e_filter_pctype pctype;
9586         uint64_t input_set, inset_reg;
9587         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9588         int num, i;
9589         uint16_t flow_type;
9590
9591         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9592              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9593                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9594
9595                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9596                         continue;
9597
9598                 input_set = i40e_get_default_input_set(pctype);
9599
9600                 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9601                                                    I40E_INSET_MASK_NUM_REG);
9602                 if (num < 0)
9603                         return;
9604                 if (pf->support_multi_driver && num > 0) {
9605                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9606                         return;
9607                 }
9608                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9609                                         input_set);
9610
9611                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9612                                       (uint32_t)(inset_reg & UINT32_MAX));
9613                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9614                                      (uint32_t)((inset_reg >>
9615                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9616                 if (!pf->support_multi_driver) {
9617                         i40e_check_write_global_reg(hw,
9618                                             I40E_GLQF_HASH_INSET(0, pctype),
9619                                             (uint32_t)(inset_reg & UINT32_MAX));
9620                         i40e_check_write_global_reg(hw,
9621                                              I40E_GLQF_HASH_INSET(1, pctype),
9622                                              (uint32_t)((inset_reg >>
9623                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9624
9625                         for (i = 0; i < num; i++) {
9626                                 i40e_check_write_global_reg(hw,
9627                                                     I40E_GLQF_FD_MSK(i, pctype),
9628                                                     mask_reg[i]);
9629                                 i40e_check_write_global_reg(hw,
9630                                                   I40E_GLQF_HASH_MSK(i, pctype),
9631                                                   mask_reg[i]);
9632                         }
9633                         /*clear unused mask registers of the pctype */
9634                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9635                                 i40e_check_write_global_reg(hw,
9636                                                     I40E_GLQF_FD_MSK(i, pctype),
9637                                                     0);
9638                                 i40e_check_write_global_reg(hw,
9639                                                   I40E_GLQF_HASH_MSK(i, pctype),
9640                                                   0);
9641                         }
9642                 } else {
9643                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9644                 }
9645                 I40E_WRITE_FLUSH(hw);
9646
9647                 /* store the default input set */
9648                 if (!pf->support_multi_driver)
9649                         pf->hash_input_set[pctype] = input_set;
9650                 pf->fdir.input_set[pctype] = input_set;
9651         }
9652 }
9653
9654 int
9655 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9656                     uint32_t pctype, bool add)
9657 {
9658         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9659         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9660         uint64_t inset_reg = 0;
9661         int num, i;
9662
9663         if (pf->support_multi_driver) {
9664                 PMD_DRV_LOG(ERR,
9665                             "Modify input set is not permitted when multi-driver enabled.");
9666                 return -EPERM;
9667         }
9668
9669         /* For X722, get translated pctype in fd pctype register */
9670         if (hw->mac.type == I40E_MAC_X722)
9671                 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9672
9673         if (add) {
9674                 /* get inset value in register */
9675                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9676                 inset_reg <<= I40E_32_BIT_WIDTH;
9677                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9678                 input_set |= pf->hash_input_set[pctype];
9679         }
9680         num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9681                                            I40E_INSET_MASK_NUM_REG);
9682         if (num < 0)
9683                 return -EINVAL;
9684
9685         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9686
9687         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9688                                     (uint32_t)(inset_reg & UINT32_MAX));
9689         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9690                                     (uint32_t)((inset_reg >>
9691                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9692
9693         for (i = 0; i < num; i++)
9694                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9695                                             mask_reg[i]);
9696         /*clear unused mask registers of the pctype */
9697         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9698                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9699                                             0);
9700         I40E_WRITE_FLUSH(hw);
9701
9702         pf->hash_input_set[pctype] = input_set;
9703         return 0;
9704 }
9705
9706 /* Convert ethertype filter structure */
9707 static int
9708 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9709                               struct i40e_ethertype_filter *filter)
9710 {
9711         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9712                 RTE_ETHER_ADDR_LEN);
9713         filter->input.ether_type = input->ether_type;
9714         filter->flags = input->flags;
9715         filter->queue = input->queue;
9716
9717         return 0;
9718 }
9719
9720 /* Check if there exists the ehtertype filter */
9721 struct i40e_ethertype_filter *
9722 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9723                                 const struct i40e_ethertype_filter_input *input)
9724 {
9725         int ret;
9726
9727         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9728         if (ret < 0)
9729                 return NULL;
9730
9731         return ethertype_rule->hash_map[ret];
9732 }
9733
9734 /* Add ethertype filter in SW list */
9735 static int
9736 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9737                                 struct i40e_ethertype_filter *filter)
9738 {
9739         struct i40e_ethertype_rule *rule = &pf->ethertype;
9740         int ret;
9741
9742         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9743         if (ret < 0) {
9744                 PMD_DRV_LOG(ERR,
9745                             "Failed to insert ethertype filter"
9746                             " to hash table %d!",
9747                             ret);
9748                 return ret;
9749         }
9750         rule->hash_map[ret] = filter;
9751
9752         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9753
9754         return 0;
9755 }
9756
9757 /* Delete ethertype filter in SW list */
9758 int
9759 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9760                              struct i40e_ethertype_filter_input *input)
9761 {
9762         struct i40e_ethertype_rule *rule = &pf->ethertype;
9763         struct i40e_ethertype_filter *filter;
9764         int ret;
9765
9766         ret = rte_hash_del_key(rule->hash_table, input);
9767         if (ret < 0) {
9768                 PMD_DRV_LOG(ERR,
9769                             "Failed to delete ethertype filter"
9770                             " to hash table %d!",
9771                             ret);
9772                 return ret;
9773         }
9774         filter = rule->hash_map[ret];
9775         rule->hash_map[ret] = NULL;
9776
9777         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9778         rte_free(filter);
9779
9780         return 0;
9781 }
9782
9783 /*
9784  * Configure ethertype filter, which can director packet by filtering
9785  * with mac address and ether_type or only ether_type
9786  */
9787 int
9788 i40e_ethertype_filter_set(struct i40e_pf *pf,
9789                         struct rte_eth_ethertype_filter *filter,
9790                         bool add)
9791 {
9792         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9793         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9794         struct i40e_ethertype_filter *ethertype_filter, *node;
9795         struct i40e_ethertype_filter check_filter;
9796         struct i40e_control_filter_stats stats;
9797         uint16_t flags = 0;
9798         int ret;
9799
9800         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9801                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9802                 return -EINVAL;
9803         }
9804         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9805                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9806                 PMD_DRV_LOG(ERR,
9807                         "unsupported ether_type(0x%04x) in control packet filter.",
9808                         filter->ether_type);
9809                 return -EINVAL;
9810         }
9811         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9812                 PMD_DRV_LOG(WARNING,
9813                         "filter vlan ether_type in first tag is not supported.");
9814
9815         /* Check if there is the filter in SW list */
9816         memset(&check_filter, 0, sizeof(check_filter));
9817         i40e_ethertype_filter_convert(filter, &check_filter);
9818         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9819                                                &check_filter.input);
9820         if (add && node) {
9821                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9822                 return -EINVAL;
9823         }
9824
9825         if (!add && !node) {
9826                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9827                 return -EINVAL;
9828         }
9829
9830         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9831                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9832         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9833                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9834         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9835
9836         memset(&stats, 0, sizeof(stats));
9837         ret = i40e_aq_add_rem_control_packet_filter(hw,
9838                         filter->mac_addr.addr_bytes,
9839                         filter->ether_type, flags,
9840                         pf->main_vsi->seid,
9841                         filter->queue, add, &stats, NULL);
9842
9843         PMD_DRV_LOG(INFO,
9844                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9845                 ret, stats.mac_etype_used, stats.etype_used,
9846                 stats.mac_etype_free, stats.etype_free);
9847         if (ret < 0)
9848                 return -ENOSYS;
9849
9850         /* Add or delete a filter in SW list */
9851         if (add) {
9852                 ethertype_filter = rte_zmalloc("ethertype_filter",
9853                                        sizeof(*ethertype_filter), 0);
9854                 if (ethertype_filter == NULL) {
9855                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9856                         return -ENOMEM;
9857                 }
9858
9859                 rte_memcpy(ethertype_filter, &check_filter,
9860                            sizeof(check_filter));
9861                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9862                 if (ret < 0)
9863                         rte_free(ethertype_filter);
9864         } else {
9865                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9866         }
9867
9868         return ret;
9869 }
9870
9871 static int
9872 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9873                       const struct rte_flow_ops **ops)
9874 {
9875         if (dev == NULL)
9876                 return -EINVAL;
9877
9878         *ops = &i40e_flow_ops;
9879         return 0;
9880 }
9881
9882 /*
9883  * Check and enable Extended Tag.
9884  * Enabling Extended Tag is important for 40G performance.
9885  */
9886 static void
9887 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9888 {
9889         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9890         uint32_t buf = 0;
9891         int ret;
9892
9893         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9894                                       PCI_DEV_CAP_REG);
9895         if (ret < 0) {
9896                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9897                             PCI_DEV_CAP_REG);
9898                 return;
9899         }
9900         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9901                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9902                 return;
9903         }
9904
9905         buf = 0;
9906         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9907                                       PCI_DEV_CTRL_REG);
9908         if (ret < 0) {
9909                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9910                             PCI_DEV_CTRL_REG);
9911                 return;
9912         }
9913         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9914                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9915                 return;
9916         }
9917         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9918         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9919                                        PCI_DEV_CTRL_REG);
9920         if (ret < 0) {
9921                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9922                             PCI_DEV_CTRL_REG);
9923                 return;
9924         }
9925 }
9926
9927 /*
9928  * As some registers wouldn't be reset unless a global hardware reset,
9929  * hardware initialization is needed to put those registers into an
9930  * expected initial state.
9931  */
9932 static void
9933 i40e_hw_init(struct rte_eth_dev *dev)
9934 {
9935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9936
9937         i40e_enable_extended_tag(dev);
9938
9939         /* clear the PF Queue Filter control register */
9940         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9941
9942         /* Disable symmetric hash per port */
9943         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9944 }
9945
9946 /*
9947  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9948  * however this function will return only one highest pctype index,
9949  * which is not quite correct. This is known problem of i40e driver
9950  * and needs to be fixed later.
9951  */
9952 enum i40e_filter_pctype
9953 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9954 {
9955         int i;
9956         uint64_t pctype_mask;
9957
9958         if (flow_type < I40E_FLOW_TYPE_MAX) {
9959                 pctype_mask = adapter->pctypes_tbl[flow_type];
9960                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9961                         if (pctype_mask & (1ULL << i))
9962                                 return (enum i40e_filter_pctype)i;
9963                 }
9964         }
9965         return I40E_FILTER_PCTYPE_INVALID;
9966 }
9967
9968 uint16_t
9969 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9970                         enum i40e_filter_pctype pctype)
9971 {
9972         uint16_t flowtype;
9973         uint64_t pctype_mask = 1ULL << pctype;
9974
9975         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9976              flowtype++) {
9977                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9978                         return flowtype;
9979         }
9980
9981         return RTE_ETH_FLOW_UNKNOWN;
9982 }
9983
9984 /*
9985  * On X710, performance number is far from the expectation on recent firmware
9986  * versions; on XL710, performance number is also far from the expectation on
9987  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9988  * mode is enabled and port MAC address is equal to the packet destination MAC
9989  * address. The fix for this issue may not be integrated in the following
9990  * firmware version. So the workaround in software driver is needed. It needs
9991  * to modify the initial values of 3 internal only registers for both X710 and
9992  * XL710. Note that the values for X710 or XL710 could be different, and the
9993  * workaround can be removed when it is fixed in firmware in the future.
9994  */
9995
9996 /* For both X710 and XL710 */
9997 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9998 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9999 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10000
10001 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10002 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10003
10004 /* For X722 */
10005 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10006 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10007
10008 /* For X710 */
10009 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10010 /* For XL710 */
10011 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10012 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10013
10014 /*
10015  * GL_SWR_PM_UP_THR:
10016  * The value is not impacted from the link speed, its value is set according
10017  * to the total number of ports for a better pipe-monitor configuration.
10018  */
10019 static bool
10020 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10021 {
10022 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10023                 .device_id = (dev),   \
10024                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10025
10026 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10027                 .device_id = (dev),   \
10028                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10029
10030         static const struct {
10031                 uint16_t device_id;
10032                 uint32_t val;
10033         } swr_pm_table[] = {
10034                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10035                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10036                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10037                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10038                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10039
10040                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10041                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10042                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10043                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10044                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10045                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10046                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10047         };
10048         uint32_t i;
10049
10050         if (value == NULL) {
10051                 PMD_DRV_LOG(ERR, "value is NULL");
10052                 return false;
10053         }
10054
10055         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10056                 if (hw->device_id == swr_pm_table[i].device_id) {
10057                         *value = swr_pm_table[i].val;
10058
10059                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10060                                     "value - 0x%08x",
10061                                     hw->device_id, *value);
10062                         return true;
10063                 }
10064         }
10065
10066         return false;
10067 }
10068
10069 static int
10070 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10071 {
10072         enum i40e_status_code status;
10073         struct i40e_aq_get_phy_abilities_resp phy_ab;
10074         int ret = -ENOTSUP;
10075         int retries = 0;
10076
10077         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10078                                               NULL);
10079
10080         while (status) {
10081                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10082                         status);
10083                 retries++;
10084                 rte_delay_us(100000);
10085                 if  (retries < 5)
10086                         status = i40e_aq_get_phy_capabilities(hw, false,
10087                                         true, &phy_ab, NULL);
10088                 else
10089                         return ret;
10090         }
10091         return 0;
10092 }
10093
10094 static void
10095 i40e_configure_registers(struct i40e_hw *hw)
10096 {
10097         static struct {
10098                 uint32_t addr;
10099                 uint64_t val;
10100         } reg_table[] = {
10101                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10102                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10103                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10104         };
10105         uint64_t reg;
10106         uint32_t i;
10107         int ret;
10108
10109         for (i = 0; i < RTE_DIM(reg_table); i++) {
10110                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10111                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10112                                 reg_table[i].val =
10113                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10114                         else /* For X710/XL710/XXV710 */
10115                                 if (hw->aq.fw_maj_ver < 6)
10116                                         reg_table[i].val =
10117                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10118                                 else
10119                                         reg_table[i].val =
10120                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10121                 }
10122
10123                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10124                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10125                                 reg_table[i].val =
10126                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10127                         else /* For X710/XL710/XXV710 */
10128                                 reg_table[i].val =
10129                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10130                 }
10131
10132                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10133                         uint32_t cfg_val;
10134
10135                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10136                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10137                                             "GL_SWR_PM_UP_THR value fixup",
10138                                             hw->device_id);
10139                                 continue;
10140                         }
10141
10142                         reg_table[i].val = cfg_val;
10143                 }
10144
10145                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10146                                                         &reg, NULL);
10147                 if (ret < 0) {
10148                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10149                                                         reg_table[i].addr);
10150                         break;
10151                 }
10152                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10153                                                 reg_table[i].addr, reg);
10154                 if (reg == reg_table[i].val)
10155                         continue;
10156
10157                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10158                                                 reg_table[i].val, NULL);
10159                 if (ret < 0) {
10160                         PMD_DRV_LOG(ERR,
10161                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10162                                 reg_table[i].val, reg_table[i].addr);
10163                         break;
10164                 }
10165                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10166                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10167         }
10168 }
10169
10170 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10171 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10172 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10173 static int
10174 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10175 {
10176         uint32_t reg;
10177         int ret;
10178
10179         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10180                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10181                 return -EINVAL;
10182         }
10183
10184         /* Configure for double VLAN RX stripping */
10185         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10186         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10187                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10188                 ret = i40e_aq_debug_write_register(hw,
10189                                                    I40E_VSI_TSR(vsi->vsi_id),
10190                                                    reg, NULL);
10191                 if (ret < 0) {
10192                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10193                                     vsi->vsi_id);
10194                         return I40E_ERR_CONFIG;
10195                 }
10196         }
10197
10198         /* Configure for double VLAN TX insertion */
10199         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10200         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10201                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10202                 ret = i40e_aq_debug_write_register(hw,
10203                                                    I40E_VSI_L2TAGSTXVALID(
10204                                                    vsi->vsi_id), reg, NULL);
10205                 if (ret < 0) {
10206                         PMD_DRV_LOG(ERR,
10207                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10208                                 vsi->vsi_id);
10209                         return I40E_ERR_CONFIG;
10210                 }
10211         }
10212
10213         return 0;
10214 }
10215
10216 static uint64_t
10217 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10218 {
10219         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10220         uint64_t systim_cycles;
10221
10222         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10223         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10224                         << 32;
10225
10226         return systim_cycles;
10227 }
10228
10229 static uint64_t
10230 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10231 {
10232         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10233         uint64_t rx_tstamp;
10234
10235         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10236         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10237                         << 32;
10238
10239         return rx_tstamp;
10240 }
10241
10242 static uint64_t
10243 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10244 {
10245         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10246         uint64_t tx_tstamp;
10247
10248         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10249         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10250                         << 32;
10251
10252         return tx_tstamp;
10253 }
10254
10255 static void
10256 i40e_start_timecounters(struct rte_eth_dev *dev)
10257 {
10258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10259         struct i40e_adapter *adapter = dev->data->dev_private;
10260         struct rte_eth_link link;
10261         uint32_t tsync_inc_l;
10262         uint32_t tsync_inc_h;
10263
10264         /* Get current link speed. */
10265         i40e_dev_link_update(dev, 1);
10266         rte_eth_linkstatus_get(dev, &link);
10267
10268         switch (link.link_speed) {
10269         case RTE_ETH_SPEED_NUM_40G:
10270         case RTE_ETH_SPEED_NUM_25G:
10271                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10272                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10273                 break;
10274         case RTE_ETH_SPEED_NUM_10G:
10275                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10276                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10277                 break;
10278         case RTE_ETH_SPEED_NUM_1G:
10279                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10280                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10281                 break;
10282         default:
10283                 tsync_inc_l = 0x0;
10284                 tsync_inc_h = 0x0;
10285         }
10286
10287         /* Set the timesync increment value. */
10288         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10289         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10290
10291         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10292         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10293         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10294
10295         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10296         adapter->systime_tc.cc_shift = 0;
10297         adapter->systime_tc.nsec_mask = 0;
10298
10299         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10300         adapter->rx_tstamp_tc.cc_shift = 0;
10301         adapter->rx_tstamp_tc.nsec_mask = 0;
10302
10303         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10304         adapter->tx_tstamp_tc.cc_shift = 0;
10305         adapter->tx_tstamp_tc.nsec_mask = 0;
10306 }
10307
10308 static int
10309 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10310 {
10311         struct i40e_adapter *adapter = dev->data->dev_private;
10312
10313         adapter->systime_tc.nsec += delta;
10314         adapter->rx_tstamp_tc.nsec += delta;
10315         adapter->tx_tstamp_tc.nsec += delta;
10316
10317         return 0;
10318 }
10319
10320 static int
10321 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10322 {
10323         uint64_t ns;
10324         struct i40e_adapter *adapter = dev->data->dev_private;
10325
10326         ns = rte_timespec_to_ns(ts);
10327
10328         /* Set the timecounters to a new value. */
10329         adapter->systime_tc.nsec = ns;
10330         adapter->rx_tstamp_tc.nsec = ns;
10331         adapter->tx_tstamp_tc.nsec = ns;
10332
10333         return 0;
10334 }
10335
10336 static int
10337 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10338 {
10339         uint64_t ns, systime_cycles;
10340         struct i40e_adapter *adapter = dev->data->dev_private;
10341
10342         systime_cycles = i40e_read_systime_cyclecounter(dev);
10343         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10344         *ts = rte_ns_to_timespec(ns);
10345
10346         return 0;
10347 }
10348
10349 static int
10350 i40e_timesync_enable(struct rte_eth_dev *dev)
10351 {
10352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10353         uint32_t tsync_ctl_l;
10354         uint32_t tsync_ctl_h;
10355
10356         /* Stop the timesync system time. */
10357         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10358         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10359         /* Reset the timesync system time value. */
10360         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10361         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10362
10363         i40e_start_timecounters(dev);
10364
10365         /* Clear timesync registers. */
10366         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10367         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10368         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10369         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10370         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10371         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10372
10373         /* Enable timestamping of PTP packets. */
10374         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10375         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10376
10377         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10378         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10379         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10380
10381         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10382         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10383
10384         return 0;
10385 }
10386
10387 static int
10388 i40e_timesync_disable(struct rte_eth_dev *dev)
10389 {
10390         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10391         uint32_t tsync_ctl_l;
10392         uint32_t tsync_ctl_h;
10393
10394         /* Disable timestamping of transmitted PTP packets. */
10395         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10396         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10397
10398         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10399         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10400
10401         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10402         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10403
10404         /* Reset the timesync increment value. */
10405         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10406         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10407
10408         return 0;
10409 }
10410
10411 static int
10412 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10413                                 struct timespec *timestamp, uint32_t flags)
10414 {
10415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10416         struct i40e_adapter *adapter = dev->data->dev_private;
10417         uint32_t sync_status;
10418         uint32_t index = flags & 0x03;
10419         uint64_t rx_tstamp_cycles;
10420         uint64_t ns;
10421
10422         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10423         if ((sync_status & (1 << index)) == 0)
10424                 return -EINVAL;
10425
10426         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10427         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10428         *timestamp = rte_ns_to_timespec(ns);
10429
10430         return 0;
10431 }
10432
10433 static int
10434 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10435                                 struct timespec *timestamp)
10436 {
10437         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10438         struct i40e_adapter *adapter = dev->data->dev_private;
10439         uint32_t sync_status;
10440         uint64_t tx_tstamp_cycles;
10441         uint64_t ns;
10442
10443         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10444         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10445                 return -EINVAL;
10446
10447         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10448         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10449         *timestamp = rte_ns_to_timespec(ns);
10450
10451         return 0;
10452 }
10453
10454 /*
10455  * i40e_parse_dcb_configure - parse dcb configure from user
10456  * @dev: the device being configured
10457  * @dcb_cfg: pointer of the result of parse
10458  * @*tc_map: bit map of enabled traffic classes
10459  *
10460  * Returns 0 on success, negative value on failure
10461  */
10462 static int
10463 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10464                          struct i40e_dcbx_config *dcb_cfg,
10465                          uint8_t *tc_map)
10466 {
10467         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10468         uint8_t i, tc_bw, bw_lf;
10469
10470         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10471
10472         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10473         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10474                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10475                 return -EINVAL;
10476         }
10477
10478         /* assume each tc has the same bw */
10479         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10480         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10481                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10482         /* to ensure the sum of tcbw is equal to 100 */
10483         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10484         for (i = 0; i < bw_lf; i++)
10485                 dcb_cfg->etscfg.tcbwtable[i]++;
10486
10487         /* assume each tc has the same Transmission Selection Algorithm */
10488         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10489                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10490
10491         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10492                 dcb_cfg->etscfg.prioritytable[i] =
10493                                 dcb_rx_conf->dcb_tc[i];
10494
10495         /* FW needs one App to configure HW */
10496         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10497         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10498         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10499         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10500
10501         if (dcb_rx_conf->nb_tcs == 0)
10502                 *tc_map = 1; /* tc0 only */
10503         else
10504                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10505
10506         if (dev->data->dev_conf.dcb_capability_en & RTE_ETH_DCB_PFC_SUPPORT) {
10507                 dcb_cfg->pfc.willing = 0;
10508                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10509                 dcb_cfg->pfc.pfcenable = *tc_map;
10510         }
10511         return 0;
10512 }
10513
10514
10515 static enum i40e_status_code
10516 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10517                               struct i40e_aqc_vsi_properties_data *info,
10518                               uint8_t enabled_tcmap)
10519 {
10520         enum i40e_status_code ret;
10521         int i, total_tc = 0;
10522         uint16_t qpnum_per_tc, bsf, qp_idx;
10523         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10524         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10525         uint16_t used_queues;
10526
10527         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10528         if (ret != I40E_SUCCESS)
10529                 return ret;
10530
10531         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10532                 if (enabled_tcmap & (1 << i))
10533                         total_tc++;
10534         }
10535         if (total_tc == 0)
10536                 total_tc = 1;
10537         vsi->enabled_tc = enabled_tcmap;
10538
10539         /* different VSI has different queues assigned */
10540         if (vsi->type == I40E_VSI_MAIN)
10541                 used_queues = dev_data->nb_rx_queues -
10542                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10543         else if (vsi->type == I40E_VSI_VMDQ2)
10544                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10545         else {
10546                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10547                 return I40E_ERR_NO_AVAILABLE_VSI;
10548         }
10549
10550         qpnum_per_tc = used_queues / total_tc;
10551         /* Number of queues per enabled TC */
10552         if (qpnum_per_tc == 0) {
10553                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10554                 return I40E_ERR_INVALID_QP_ID;
10555         }
10556         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10557                                 I40E_MAX_Q_PER_TC);
10558         bsf = rte_bsf32(qpnum_per_tc);
10559
10560         /**
10561          * Configure TC and queue mapping parameters, for enabled TC,
10562          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10563          * default queue will serve it.
10564          */
10565         qp_idx = 0;
10566         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10567                 if (vsi->enabled_tc & (1 << i)) {
10568                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10569                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10570                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10571                         qp_idx += qpnum_per_tc;
10572                 } else
10573                         info->tc_mapping[i] = 0;
10574         }
10575
10576         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10577         if (vsi->type == I40E_VSI_SRIOV) {
10578                 info->mapping_flags |=
10579                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10580                 for (i = 0; i < vsi->nb_qps; i++)
10581                         info->queue_mapping[i] =
10582                                 rte_cpu_to_le_16(vsi->base_queue + i);
10583         } else {
10584                 info->mapping_flags |=
10585                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10586                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10587         }
10588         info->valid_sections |=
10589                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10590
10591         return I40E_SUCCESS;
10592 }
10593
10594 /*
10595  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10596  * @veb: VEB to be configured
10597  * @tc_map: enabled TC bitmap
10598  *
10599  * Returns 0 on success, negative value on failure
10600  */
10601 static enum i40e_status_code
10602 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10603 {
10604         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10605         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10606         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10607         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10608         enum i40e_status_code ret = I40E_SUCCESS;
10609         int i;
10610         uint32_t bw_max;
10611
10612         /* Check if enabled_tc is same as existing or new TCs */
10613         if (veb->enabled_tc == tc_map)
10614                 return ret;
10615
10616         /* configure tc bandwidth */
10617         memset(&veb_bw, 0, sizeof(veb_bw));
10618         veb_bw.tc_valid_bits = tc_map;
10619         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10620         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10621                 if (tc_map & BIT_ULL(i))
10622                         veb_bw.tc_bw_share_credits[i] = 1;
10623         }
10624         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10625                                                    &veb_bw, NULL);
10626         if (ret) {
10627                 PMD_INIT_LOG(ERR,
10628                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10629                         hw->aq.asq_last_status);
10630                 return ret;
10631         }
10632
10633         memset(&ets_query, 0, sizeof(ets_query));
10634         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10635                                                    &ets_query, NULL);
10636         if (ret != I40E_SUCCESS) {
10637                 PMD_DRV_LOG(ERR,
10638                         "Failed to get switch_comp ETS configuration %u",
10639                         hw->aq.asq_last_status);
10640                 return ret;
10641         }
10642         memset(&bw_query, 0, sizeof(bw_query));
10643         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10644                                                   &bw_query, NULL);
10645         if (ret != I40E_SUCCESS) {
10646                 PMD_DRV_LOG(ERR,
10647                         "Failed to get switch_comp bandwidth configuration %u",
10648                         hw->aq.asq_last_status);
10649                 return ret;
10650         }
10651
10652         /* store and print out BW info */
10653         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10654         veb->bw_info.bw_max = ets_query.tc_bw_max;
10655         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10656         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10657         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10658                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10659                      I40E_16_BIT_WIDTH);
10660         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10661                 veb->bw_info.bw_ets_share_credits[i] =
10662                                 bw_query.tc_bw_share_credits[i];
10663                 veb->bw_info.bw_ets_credits[i] =
10664                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10665                 /* 4 bits per TC, 4th bit is reserved */
10666                 veb->bw_info.bw_ets_max[i] =
10667                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10668                                   RTE_LEN2MASK(3, uint8_t));
10669                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10670                             veb->bw_info.bw_ets_share_credits[i]);
10671                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10672                             veb->bw_info.bw_ets_credits[i]);
10673                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10674                             veb->bw_info.bw_ets_max[i]);
10675         }
10676
10677         veb->enabled_tc = tc_map;
10678
10679         return ret;
10680 }
10681
10682
10683 /*
10684  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10685  * @vsi: VSI to be configured
10686  * @tc_map: enabled TC bitmap
10687  *
10688  * Returns 0 on success, negative value on failure
10689  */
10690 static enum i40e_status_code
10691 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10692 {
10693         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10694         struct i40e_vsi_context ctxt;
10695         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10696         enum i40e_status_code ret = I40E_SUCCESS;
10697         int i;
10698
10699         /* Check if enabled_tc is same as existing or new TCs */
10700         if (vsi->enabled_tc == tc_map)
10701                 return ret;
10702
10703         /* configure tc bandwidth */
10704         memset(&bw_data, 0, sizeof(bw_data));
10705         bw_data.tc_valid_bits = tc_map;
10706         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10707         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10708                 if (tc_map & BIT_ULL(i))
10709                         bw_data.tc_bw_credits[i] = 1;
10710         }
10711         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10712         if (ret) {
10713                 PMD_INIT_LOG(ERR,
10714                         "AQ command Config VSI BW allocation per TC failed = %d",
10715                         hw->aq.asq_last_status);
10716                 goto out;
10717         }
10718         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10719                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10720
10721         /* Update Queue Pairs Mapping for currently enabled UPs */
10722         ctxt.seid = vsi->seid;
10723         ctxt.pf_num = hw->pf_id;
10724         ctxt.vf_num = 0;
10725         ctxt.uplink_seid = vsi->uplink_seid;
10726         ctxt.info = vsi->info;
10727         i40e_get_cap(hw);
10728         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10729         if (ret)
10730                 goto out;
10731
10732         /* Update the VSI after updating the VSI queue-mapping information */
10733         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10734         if (ret) {
10735                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10736                         hw->aq.asq_last_status);
10737                 goto out;
10738         }
10739         /* update the local VSI info with updated queue map */
10740         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10741                                         sizeof(vsi->info.tc_mapping));
10742         rte_memcpy(&vsi->info.queue_mapping,
10743                         &ctxt.info.queue_mapping,
10744                 sizeof(vsi->info.queue_mapping));
10745         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10746         vsi->info.valid_sections = 0;
10747
10748         /* query and update current VSI BW information */
10749         ret = i40e_vsi_get_bw_config(vsi);
10750         if (ret) {
10751                 PMD_INIT_LOG(ERR,
10752                          "Failed updating vsi bw info, err %s aq_err %s",
10753                          i40e_stat_str(hw, ret),
10754                          i40e_aq_str(hw, hw->aq.asq_last_status));
10755                 goto out;
10756         }
10757
10758         vsi->enabled_tc = tc_map;
10759
10760 out:
10761         return ret;
10762 }
10763
10764 /*
10765  * i40e_dcb_hw_configure - program the dcb setting to hw
10766  * @pf: pf the configuration is taken on
10767  * @new_cfg: new configuration
10768  * @tc_map: enabled TC bitmap
10769  *
10770  * Returns 0 on success, negative value on failure
10771  */
10772 static enum i40e_status_code
10773 i40e_dcb_hw_configure(struct i40e_pf *pf,
10774                       struct i40e_dcbx_config *new_cfg,
10775                       uint8_t tc_map)
10776 {
10777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10778         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10779         struct i40e_vsi *main_vsi = pf->main_vsi;
10780         struct i40e_vsi_list *vsi_list;
10781         enum i40e_status_code ret;
10782         int i;
10783         uint32_t val;
10784
10785         /* Use the FW API if FW > v4.4*/
10786         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10787               (hw->aq.fw_maj_ver >= 5))) {
10788                 PMD_INIT_LOG(ERR,
10789                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10790                 return I40E_ERR_FIRMWARE_API_VERSION;
10791         }
10792
10793         /* Check if need reconfiguration */
10794         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10795                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10796                 return I40E_SUCCESS;
10797         }
10798
10799         /* Copy the new config to the current config */
10800         *old_cfg = *new_cfg;
10801         old_cfg->etsrec = old_cfg->etscfg;
10802         ret = i40e_set_dcb_config(hw);
10803         if (ret) {
10804                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10805                          i40e_stat_str(hw, ret),
10806                          i40e_aq_str(hw, hw->aq.asq_last_status));
10807                 return ret;
10808         }
10809         /* set receive Arbiter to RR mode and ETS scheme by default */
10810         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10811                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10812                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10813                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10814                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10815                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10816                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10817                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10818                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10819                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10820                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10821                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10822                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10823         }
10824         /* get local mib to check whether it is configured correctly */
10825         /* IEEE mode */
10826         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10827         /* Get Local DCB Config */
10828         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10829                                      &hw->local_dcbx_config);
10830
10831         /* if Veb is created, need to update TC of it at first */
10832         if (main_vsi->veb) {
10833                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10834                 if (ret)
10835                         PMD_INIT_LOG(WARNING,
10836                                  "Failed configuring TC for VEB seid=%d",
10837                                  main_vsi->veb->seid);
10838         }
10839         /* Update each VSI */
10840         i40e_vsi_config_tc(main_vsi, tc_map);
10841         if (main_vsi->veb) {
10842                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10843                         /* Beside main VSI and VMDQ VSIs, only enable default
10844                          * TC for other VSIs
10845                          */
10846                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10847                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10848                                                          tc_map);
10849                         else
10850                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10851                                                          I40E_DEFAULT_TCMAP);
10852                         if (ret)
10853                                 PMD_INIT_LOG(WARNING,
10854                                         "Failed configuring TC for VSI seid=%d",
10855                                         vsi_list->vsi->seid);
10856                         /* continue */
10857                 }
10858         }
10859         return I40E_SUCCESS;
10860 }
10861
10862 /*
10863  * i40e_dcb_init_configure - initial dcb config
10864  * @dev: device being configured
10865  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10866  *
10867  * Returns 0 on success, negative value on failure
10868  */
10869 int
10870 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10871 {
10872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10874         int i, ret = 0;
10875
10876         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10877                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10878                 return -ENOTSUP;
10879         }
10880
10881         /* DCB initialization:
10882          * Update DCB configuration from the Firmware and configure
10883          * LLDP MIB change event.
10884          */
10885         if (sw_dcb == TRUE) {
10886                 /* Stopping lldp is necessary for DPDK, but it will cause
10887                  * DCB init failed. For i40e_init_dcb(), the prerequisite
10888                  * for successful initialization of DCB is that LLDP is
10889                  * enabled. So it is needed to start lldp before DCB init
10890                  * and stop it after initialization.
10891                  */
10892                 ret = i40e_aq_start_lldp(hw, true, NULL);
10893                 if (ret != I40E_SUCCESS)
10894                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10895
10896                 ret = i40e_init_dcb(hw, true);
10897                 /* If lldp agent is stopped, the return value from
10898                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10899                  * adminq status. Otherwise, it should return success.
10900                  */
10901                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10902                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10903                         memset(&hw->local_dcbx_config, 0,
10904                                 sizeof(struct i40e_dcbx_config));
10905                         /* set dcb default configuration */
10906                         hw->local_dcbx_config.etscfg.willing = 0;
10907                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10908                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10909                         hw->local_dcbx_config.etscfg.tsatable[0] =
10910                                                 I40E_IEEE_TSA_ETS;
10911                         /* all UPs mapping to TC0 */
10912                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10913                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10914                         hw->local_dcbx_config.etsrec =
10915                                 hw->local_dcbx_config.etscfg;
10916                         hw->local_dcbx_config.pfc.willing = 0;
10917                         hw->local_dcbx_config.pfc.pfccap =
10918                                                 I40E_MAX_TRAFFIC_CLASS;
10919                         /* FW needs one App to configure HW */
10920                         hw->local_dcbx_config.numapps = 1;
10921                         hw->local_dcbx_config.app[0].selector =
10922                                                 I40E_APP_SEL_ETHTYPE;
10923                         hw->local_dcbx_config.app[0].priority = 3;
10924                         hw->local_dcbx_config.app[0].protocolid =
10925                                                 I40E_APP_PROTOID_FCOE;
10926                         ret = i40e_set_dcb_config(hw);
10927                         if (ret) {
10928                                 PMD_INIT_LOG(ERR,
10929                                         "default dcb config fails. err = %d, aq_err = %d.",
10930                                         ret, hw->aq.asq_last_status);
10931                                 return -ENOSYS;
10932                         }
10933                 } else {
10934                         PMD_INIT_LOG(ERR,
10935                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10936                                 ret, hw->aq.asq_last_status);
10937                         return -ENOTSUP;
10938                 }
10939
10940                 if (i40e_need_stop_lldp(dev)) {
10941                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
10942                         if (ret != I40E_SUCCESS)
10943                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
10944                 }
10945         } else {
10946                 ret = i40e_aq_start_lldp(hw, true, NULL);
10947                 if (ret != I40E_SUCCESS)
10948                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10949
10950                 ret = i40e_init_dcb(hw, true);
10951                 if (!ret) {
10952                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10953                                 PMD_INIT_LOG(ERR,
10954                                         "HW doesn't support DCBX offload.");
10955                                 return -ENOTSUP;
10956                         }
10957                 } else {
10958                         PMD_INIT_LOG(ERR,
10959                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10960                                 ret, hw->aq.asq_last_status);
10961                         return -ENOTSUP;
10962                 }
10963         }
10964         return 0;
10965 }
10966
10967 /*
10968  * i40e_dcb_setup - setup dcb related config
10969  * @dev: device being configured
10970  *
10971  * Returns 0 on success, negative value on failure
10972  */
10973 static int
10974 i40e_dcb_setup(struct rte_eth_dev *dev)
10975 {
10976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10977         struct i40e_dcbx_config dcb_cfg;
10978         uint8_t tc_map = 0;
10979         int ret = 0;
10980
10981         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10982                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10983                 return -ENOTSUP;
10984         }
10985
10986         if (pf->vf_num != 0)
10987                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10988
10989         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10990         if (ret) {
10991                 PMD_INIT_LOG(ERR, "invalid dcb config");
10992                 return -EINVAL;
10993         }
10994         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10995         if (ret) {
10996                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10997                 return -ENOSYS;
10998         }
10999
11000         return 0;
11001 }
11002
11003 static int
11004 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11005                       struct rte_eth_dcb_info *dcb_info)
11006 {
11007         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11009         struct i40e_vsi *vsi = pf->main_vsi;
11010         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11011         uint16_t bsf, tc_mapping;
11012         int i, j = 0;
11013
11014         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
11015                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11016         else
11017                 dcb_info->nb_tcs = 1;
11018         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11019                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11020         for (i = 0; i < dcb_info->nb_tcs; i++)
11021                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11022
11023         /* get queue mapping if vmdq is disabled */
11024         if (!pf->nb_cfg_vmdq_vsi) {
11025                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11026                         if (!(vsi->enabled_tc & (1 << i)))
11027                                 continue;
11028                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11029                         dcb_info->tc_queue.tc_rxq[j][i].base =
11030                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11031                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11032                         dcb_info->tc_queue.tc_txq[j][i].base =
11033                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11034                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11035                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11036                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11037                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11038                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11039                 }
11040                 return 0;
11041         }
11042
11043         /* get queue mapping if vmdq is enabled */
11044         do {
11045                 vsi = pf->vmdq[j].vsi;
11046                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11047                         if (!(vsi->enabled_tc & (1 << i)))
11048                                 continue;
11049                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11050                         dcb_info->tc_queue.tc_rxq[j][i].base =
11051                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11052                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11053                         dcb_info->tc_queue.tc_txq[j][i].base =
11054                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11055                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11056                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11057                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11058                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11059                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11060                 }
11061                 j++;
11062         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, RTE_ETH_MAX_VMDQ_POOL));
11063         return 0;
11064 }
11065
11066 static int
11067 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11068 {
11069         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11070         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
11071         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11072         uint16_t msix_intr;
11073
11074         msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
11075         if (msix_intr == I40E_MISC_VEC_ID)
11076                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11077                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11078                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11079                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11080         else
11081                 I40E_WRITE_REG(hw,
11082                                I40E_PFINT_DYN_CTLN(msix_intr -
11083                                                    I40E_RX_VEC_START),
11084                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11085                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11086                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11087
11088         I40E_WRITE_FLUSH(hw);
11089         rte_intr_ack(pci_dev->intr_handle);
11090
11091         return 0;
11092 }
11093
11094 static int
11095 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11096 {
11097         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11098         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
11099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11100         uint16_t msix_intr;
11101
11102         msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
11103         if (msix_intr == I40E_MISC_VEC_ID)
11104                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11105                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11106         else
11107                 I40E_WRITE_REG(hw,
11108                                I40E_PFINT_DYN_CTLN(msix_intr -
11109                                                    I40E_RX_VEC_START),
11110                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11111         I40E_WRITE_FLUSH(hw);
11112
11113         return 0;
11114 }
11115
11116 /**
11117  * This function is used to check if the register is valid.
11118  * Below is the valid registers list for X722 only:
11119  * 0x2b800--0x2bb00
11120  * 0x38700--0x38a00
11121  * 0x3d800--0x3db00
11122  * 0x208e00--0x209000
11123  * 0x20be00--0x20c000
11124  * 0x263c00--0x264000
11125  * 0x265c00--0x266000
11126  */
11127 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11128 {
11129         if ((type != I40E_MAC_X722) &&
11130             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11131              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11132              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11133              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11134              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11135              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11136              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11137                 return 0;
11138         else
11139                 return 1;
11140 }
11141
11142 static int i40e_get_regs(struct rte_eth_dev *dev,
11143                          struct rte_dev_reg_info *regs)
11144 {
11145         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11146         uint32_t *ptr_data = regs->data;
11147         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11148         const struct i40e_reg_info *reg_info;
11149
11150         if (ptr_data == NULL) {
11151                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11152                 regs->width = sizeof(uint32_t);
11153                 return 0;
11154         }
11155
11156         /* The first few registers have to be read using AQ operations */
11157         reg_idx = 0;
11158         while (i40e_regs_adminq[reg_idx].name) {
11159                 reg_info = &i40e_regs_adminq[reg_idx++];
11160                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11161                         for (arr_idx2 = 0;
11162                                         arr_idx2 <= reg_info->count2;
11163                                         arr_idx2++) {
11164                                 reg_offset = arr_idx * reg_info->stride1 +
11165                                         arr_idx2 * reg_info->stride2;
11166                                 reg_offset += reg_info->base_addr;
11167                                 ptr_data[reg_offset >> 2] =
11168                                         i40e_read_rx_ctl(hw, reg_offset);
11169                         }
11170         }
11171
11172         /* The remaining registers can be read using primitives */
11173         reg_idx = 0;
11174         while (i40e_regs_others[reg_idx].name) {
11175                 reg_info = &i40e_regs_others[reg_idx++];
11176                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11177                         for (arr_idx2 = 0;
11178                                         arr_idx2 <= reg_info->count2;
11179                                         arr_idx2++) {
11180                                 reg_offset = arr_idx * reg_info->stride1 +
11181                                         arr_idx2 * reg_info->stride2;
11182                                 reg_offset += reg_info->base_addr;
11183                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11184                                         ptr_data[reg_offset >> 2] = 0;
11185                                 else
11186                                         ptr_data[reg_offset >> 2] =
11187                                                 I40E_READ_REG(hw, reg_offset);
11188                         }
11189         }
11190
11191         return 0;
11192 }
11193
11194 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11195 {
11196         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11197
11198         /* Convert word count to byte count */
11199         return hw->nvm.sr_size << 1;
11200 }
11201
11202 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11203                            struct rte_dev_eeprom_info *eeprom)
11204 {
11205         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11206         uint16_t *data = eeprom->data;
11207         uint16_t offset, length, cnt_words;
11208         int ret_code;
11209
11210         offset = eeprom->offset >> 1;
11211         length = eeprom->length >> 1;
11212         cnt_words = length;
11213
11214         if (offset > hw->nvm.sr_size ||
11215                 offset + length > hw->nvm.sr_size) {
11216                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11217                 return -EINVAL;
11218         }
11219
11220         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11221
11222         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11223         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11224                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11225                 return -EIO;
11226         }
11227
11228         return 0;
11229 }
11230
11231 static int i40e_get_module_info(struct rte_eth_dev *dev,
11232                                 struct rte_eth_dev_module_info *modinfo)
11233 {
11234         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11235         uint32_t sff8472_comp = 0;
11236         uint32_t sff8472_swap = 0;
11237         uint32_t sff8636_rev = 0;
11238         i40e_status status;
11239         uint32_t type = 0;
11240
11241         /* Check if firmware supports reading module EEPROM. */
11242         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11243                 PMD_DRV_LOG(ERR,
11244                             "Module EEPROM memory read not supported. "
11245                             "Please update the NVM image.\n");
11246                 return -EINVAL;
11247         }
11248
11249         status = i40e_update_link_info(hw);
11250         if (status)
11251                 return -EIO;
11252
11253         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11254                 PMD_DRV_LOG(ERR,
11255                             "Cannot read module EEPROM memory. "
11256                             "No module connected.\n");
11257                 return -EINVAL;
11258         }
11259
11260         type = hw->phy.link_info.module_type[0];
11261
11262         switch (type) {
11263         case I40E_MODULE_TYPE_SFP:
11264                 status = i40e_aq_get_phy_register(hw,
11265                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11266                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11267                                 I40E_MODULE_SFF_8472_COMP,
11268                                 &sff8472_comp, NULL);
11269                 if (status)
11270                         return -EIO;
11271
11272                 status = i40e_aq_get_phy_register(hw,
11273                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11274                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11275                                 I40E_MODULE_SFF_8472_SWAP,
11276                                 &sff8472_swap, NULL);
11277                 if (status)
11278                         return -EIO;
11279
11280                 /* Check if the module requires address swap to access
11281                  * the other EEPROM memory page.
11282                  */
11283                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11284                         PMD_DRV_LOG(WARNING,
11285                                     "Module address swap to access "
11286                                     "page 0xA2 is not supported.\n");
11287                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11288                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11289                 } else if (sff8472_comp == 0x00) {
11290                         /* Module is not SFF-8472 compliant */
11291                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11292                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11293                 } else {
11294                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11295                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11296                 }
11297                 break;
11298         case I40E_MODULE_TYPE_QSFP_PLUS:
11299                 /* Read from memory page 0. */
11300                 status = i40e_aq_get_phy_register(hw,
11301                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11302                                 0, 1,
11303                                 I40E_MODULE_REVISION_ADDR,
11304                                 &sff8636_rev, NULL);
11305                 if (status)
11306                         return -EIO;
11307                 /* Determine revision compliance byte */
11308                 if (sff8636_rev > 0x02) {
11309                         /* Module is SFF-8636 compliant */
11310                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11311                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11312                 } else {
11313                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11314                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11315                 }
11316                 break;
11317         case I40E_MODULE_TYPE_QSFP28:
11318                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11319                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11320                 break;
11321         default:
11322                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11323                 return -EINVAL;
11324         }
11325         return 0;
11326 }
11327
11328 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11329                                   struct rte_dev_eeprom_info *info)
11330 {
11331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11332         bool is_sfp = false;
11333         i40e_status status;
11334         uint8_t *data;
11335         uint32_t value = 0;
11336         uint32_t i;
11337
11338         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11339                 is_sfp = true;
11340
11341         data = info->data;
11342         for (i = 0; i < info->length; i++) {
11343                 u32 offset = i + info->offset;
11344                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11345
11346                 /* Check if we need to access the other memory page */
11347                 if (is_sfp) {
11348                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11349                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11350                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11351                         }
11352                 } else {
11353                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11354                                 /* Compute memory page number and offset. */
11355                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11356                                 addr++;
11357                         }
11358                 }
11359                 status = i40e_aq_get_phy_register(hw,
11360                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11361                                 addr, 1, offset, &value, NULL);
11362                 if (status)
11363                         return -EIO;
11364                 data[i] = (uint8_t)value;
11365         }
11366         return 0;
11367 }
11368
11369 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11370                                      struct rte_ether_addr *mac_addr)
11371 {
11372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11374         struct i40e_vsi *vsi = pf->main_vsi;
11375         struct i40e_mac_filter_info mac_filter;
11376         struct i40e_mac_filter *f;
11377         int ret;
11378
11379         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11380                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11381                 return -EINVAL;
11382         }
11383
11384         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11385                 if (rte_is_same_ether_addr(&pf->dev_addr,
11386                                                 &f->mac_info.mac_addr))
11387                         break;
11388         }
11389
11390         if (f == NULL) {
11391                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11392                 return -EIO;
11393         }
11394
11395         mac_filter = f->mac_info;
11396         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11397         if (ret != I40E_SUCCESS) {
11398                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11399                 return -EIO;
11400         }
11401         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11402         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11403         if (ret != I40E_SUCCESS) {
11404                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11405                 return -EIO;
11406         }
11407         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11408
11409         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11410                                         mac_addr->addr_bytes, NULL);
11411         if (ret != I40E_SUCCESS) {
11412                 PMD_DRV_LOG(ERR, "Failed to change mac");
11413                 return -EIO;
11414         }
11415
11416         return 0;
11417 }
11418
11419 static int
11420 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused)
11421 {
11422         /* mtu setting is forbidden if port is start */
11423         if (dev->data->dev_started != 0) {
11424                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11425                             dev->data->port_id);
11426                 return -EBUSY;
11427         }
11428
11429         return 0;
11430 }
11431
11432 /* Restore ethertype filter */
11433 static void
11434 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11435 {
11436         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11437         struct i40e_ethertype_filter_list
11438                 *ethertype_list = &pf->ethertype.ethertype_list;
11439         struct i40e_ethertype_filter *f;
11440         struct i40e_control_filter_stats stats;
11441         uint16_t flags;
11442
11443         TAILQ_FOREACH(f, ethertype_list, rules) {
11444                 flags = 0;
11445                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11446                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11447                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11448                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11449                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11450
11451                 memset(&stats, 0, sizeof(stats));
11452                 i40e_aq_add_rem_control_packet_filter(hw,
11453                                             f->input.mac_addr.addr_bytes,
11454                                             f->input.ether_type,
11455                                             flags, pf->main_vsi->seid,
11456                                             f->queue, 1, &stats, NULL);
11457         }
11458         PMD_DRV_LOG(INFO, "Ethertype filter:"
11459                     " mac_etype_used = %u, etype_used = %u,"
11460                     " mac_etype_free = %u, etype_free = %u",
11461                     stats.mac_etype_used, stats.etype_used,
11462                     stats.mac_etype_free, stats.etype_free);
11463 }
11464
11465 /* Restore tunnel filter */
11466 static void
11467 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11468 {
11469         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11470         struct i40e_vsi *vsi;
11471         struct i40e_pf_vf *vf;
11472         struct i40e_tunnel_filter_list
11473                 *tunnel_list = &pf->tunnel.tunnel_list;
11474         struct i40e_tunnel_filter *f;
11475         struct i40e_aqc_cloud_filters_element_bb cld_filter;
11476         bool big_buffer = 0;
11477
11478         TAILQ_FOREACH(f, tunnel_list, rules) {
11479                 if (!f->is_to_vf)
11480                         vsi = pf->main_vsi;
11481                 else {
11482                         vf = &pf->vfs[f->vf_id];
11483                         vsi = vf->vsi;
11484                 }
11485                 memset(&cld_filter, 0, sizeof(cld_filter));
11486                 rte_ether_addr_copy((struct rte_ether_addr *)
11487                                 &f->input.outer_mac,
11488                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11489                 rte_ether_addr_copy((struct rte_ether_addr *)
11490                                 &f->input.inner_mac,
11491                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11492                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11493                 cld_filter.element.flags = f->input.flags;
11494                 cld_filter.element.tenant_id = f->input.tenant_id;
11495                 cld_filter.element.queue_number = f->queue;
11496                 rte_memcpy(cld_filter.general_fields,
11497                            f->input.general_fields,
11498                            sizeof(f->input.general_fields));
11499
11500                 if (((f->input.flags &
11501                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11502                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11503                     ((f->input.flags &
11504                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11505                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11506                     ((f->input.flags &
11507                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11508                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11509                         big_buffer = 1;
11510
11511                 if (big_buffer)
11512                         i40e_aq_add_cloud_filters_bb(hw,
11513                                         vsi->seid, &cld_filter, 1);
11514                 else
11515                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11516                                                   &cld_filter.element, 1);
11517         }
11518 }
11519
11520 static void
11521 i40e_filter_restore(struct i40e_pf *pf)
11522 {
11523         i40e_ethertype_filter_restore(pf);
11524         i40e_tunnel_filter_restore(pf);
11525         i40e_fdir_filter_restore(pf);
11526         (void)i40e_hash_filter_restore(pf);
11527 }
11528
11529 bool
11530 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11531 {
11532         if (strcmp(dev->device->driver->name, drv->driver.name))
11533                 return false;
11534
11535         return true;
11536 }
11537
11538 bool
11539 is_i40e_supported(struct rte_eth_dev *dev)
11540 {
11541         return is_device_supported(dev, &rte_i40e_pmd);
11542 }
11543
11544 struct i40e_customized_pctype*
11545 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11546 {
11547         int i;
11548
11549         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11550                 if (pf->customized_pctype[i].index == index)
11551                         return &pf->customized_pctype[i];
11552         }
11553         return NULL;
11554 }
11555
11556 static int
11557 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11558                               uint32_t pkg_size, uint32_t proto_num,
11559                               struct rte_pmd_i40e_proto_info *proto,
11560                               enum rte_pmd_i40e_package_op op)
11561 {
11562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11563         uint32_t pctype_num;
11564         struct rte_pmd_i40e_ptype_info *pctype;
11565         uint32_t buff_size;
11566         struct i40e_customized_pctype *new_pctype = NULL;
11567         uint8_t proto_id;
11568         uint8_t pctype_value;
11569         char name[64];
11570         uint32_t i, j, n;
11571         int ret;
11572
11573         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11574             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11575                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11576                 return -1;
11577         }
11578
11579         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11580                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11581                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11582         if (ret) {
11583                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11584                 return -1;
11585         }
11586         if (!pctype_num) {
11587                 PMD_DRV_LOG(INFO, "No new pctype added");
11588                 return -1;
11589         }
11590
11591         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11592         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11593         if (!pctype) {
11594                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11595                 return -1;
11596         }
11597         /* get information about new pctype list */
11598         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11599                                         (uint8_t *)pctype, buff_size,
11600                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11601         if (ret) {
11602                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11603                 rte_free(pctype);
11604                 return -1;
11605         }
11606
11607         /* Update customized pctype. */
11608         for (i = 0; i < pctype_num; i++) {
11609                 pctype_value = pctype[i].ptype_id;
11610                 memset(name, 0, sizeof(name));
11611                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11612                         proto_id = pctype[i].protocols[j];
11613                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11614                                 continue;
11615                         for (n = 0; n < proto_num; n++) {
11616                                 if (proto[n].proto_id != proto_id)
11617                                         continue;
11618                                 strlcat(name, proto[n].name, sizeof(name));
11619                                 strlcat(name, "_", sizeof(name));
11620                                 break;
11621                         }
11622                 }
11623                 name[strlen(name) - 1] = '\0';
11624                 PMD_DRV_LOG(INFO, "name = %s\n", name);
11625                 if (!strcmp(name, "GTPC"))
11626                         new_pctype =
11627                                 i40e_find_customized_pctype(pf,
11628                                                       I40E_CUSTOMIZED_GTPC);
11629                 else if (!strcmp(name, "GTPU_IPV4"))
11630                         new_pctype =
11631                                 i40e_find_customized_pctype(pf,
11632                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11633                 else if (!strcmp(name, "GTPU_IPV6"))
11634                         new_pctype =
11635                                 i40e_find_customized_pctype(pf,
11636                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11637                 else if (!strcmp(name, "GTPU"))
11638                         new_pctype =
11639                                 i40e_find_customized_pctype(pf,
11640                                                       I40E_CUSTOMIZED_GTPU);
11641                 else if (!strcmp(name, "IPV4_L2TPV3"))
11642                         new_pctype =
11643                                 i40e_find_customized_pctype(pf,
11644                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
11645                 else if (!strcmp(name, "IPV6_L2TPV3"))
11646                         new_pctype =
11647                                 i40e_find_customized_pctype(pf,
11648                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
11649                 else if (!strcmp(name, "IPV4_ESP"))
11650                         new_pctype =
11651                                 i40e_find_customized_pctype(pf,
11652                                                 I40E_CUSTOMIZED_ESP_IPV4);
11653                 else if (!strcmp(name, "IPV6_ESP"))
11654                         new_pctype =
11655                                 i40e_find_customized_pctype(pf,
11656                                                 I40E_CUSTOMIZED_ESP_IPV6);
11657                 else if (!strcmp(name, "IPV4_UDP_ESP"))
11658                         new_pctype =
11659                                 i40e_find_customized_pctype(pf,
11660                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
11661                 else if (!strcmp(name, "IPV6_UDP_ESP"))
11662                         new_pctype =
11663                                 i40e_find_customized_pctype(pf,
11664                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
11665                 else if (!strcmp(name, "IPV4_AH"))
11666                         new_pctype =
11667                                 i40e_find_customized_pctype(pf,
11668                                                 I40E_CUSTOMIZED_AH_IPV4);
11669                 else if (!strcmp(name, "IPV6_AH"))
11670                         new_pctype =
11671                                 i40e_find_customized_pctype(pf,
11672                                                 I40E_CUSTOMIZED_AH_IPV6);
11673                 if (new_pctype) {
11674                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11675                                 new_pctype->pctype = pctype_value;
11676                                 new_pctype->valid = true;
11677                         } else {
11678                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11679                                 new_pctype->valid = false;
11680                         }
11681                 }
11682         }
11683
11684         rte_free(pctype);
11685         return 0;
11686 }
11687
11688 static int
11689 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11690                              uint32_t pkg_size, uint32_t proto_num,
11691                              struct rte_pmd_i40e_proto_info *proto,
11692                              enum rte_pmd_i40e_package_op op)
11693 {
11694         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11695         uint16_t port_id = dev->data->port_id;
11696         uint32_t ptype_num;
11697         struct rte_pmd_i40e_ptype_info *ptype;
11698         uint32_t buff_size;
11699         uint8_t proto_id;
11700         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11701         uint32_t i, j, n;
11702         bool in_tunnel;
11703         int ret;
11704
11705         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11706             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11707                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11708                 return -1;
11709         }
11710
11711         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11712                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11713                 return 0;
11714         }
11715
11716         /* get information about new ptype num */
11717         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11718                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11719                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11720         if (ret) {
11721                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11722                 return ret;
11723         }
11724         if (!ptype_num) {
11725                 PMD_DRV_LOG(INFO, "No new ptype added");
11726                 return -1;
11727         }
11728
11729         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11730         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11731         if (!ptype) {
11732                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11733                 return -1;
11734         }
11735
11736         /* get information about new ptype list */
11737         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11738                                         (uint8_t *)ptype, buff_size,
11739                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11740         if (ret) {
11741                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11742                 rte_free(ptype);
11743                 return ret;
11744         }
11745
11746         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11747         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11748         if (!ptype_mapping) {
11749                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11750                 rte_free(ptype);
11751                 return -1;
11752         }
11753
11754         /* Update ptype mapping table. */
11755         for (i = 0; i < ptype_num; i++) {
11756                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11757                 ptype_mapping[i].sw_ptype = 0;
11758                 in_tunnel = false;
11759                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11760                         proto_id = ptype[i].protocols[j];
11761                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11762                                 continue;
11763                         for (n = 0; n < proto_num; n++) {
11764                                 if (proto[n].proto_id != proto_id)
11765                                         continue;
11766                                 memset(name, 0, sizeof(name));
11767                                 strcpy(name, proto[n].name);
11768                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
11769                                 if (!strncasecmp(name, "PPPOE", 5))
11770                                         ptype_mapping[i].sw_ptype |=
11771                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11772                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11773                                          !in_tunnel) {
11774                                         ptype_mapping[i].sw_ptype |=
11775                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11776                                         ptype_mapping[i].sw_ptype |=
11777                                                 RTE_PTYPE_L4_FRAG;
11778                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11779                                            in_tunnel) {
11780                                         ptype_mapping[i].sw_ptype |=
11781                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11782                                         ptype_mapping[i].sw_ptype |=
11783                                                 RTE_PTYPE_INNER_L4_FRAG;
11784                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11785                                         ptype_mapping[i].sw_ptype |=
11786                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11787                                         in_tunnel = true;
11788                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11789                                            !in_tunnel)
11790                                         ptype_mapping[i].sw_ptype |=
11791                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11792                                 else if (!strncasecmp(name, "IPV4", 4) &&
11793                                          in_tunnel)
11794                                         ptype_mapping[i].sw_ptype |=
11795                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11796                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11797                                          !in_tunnel) {
11798                                         ptype_mapping[i].sw_ptype |=
11799                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11800                                         ptype_mapping[i].sw_ptype |=
11801                                                 RTE_PTYPE_L4_FRAG;
11802                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11803                                            in_tunnel) {
11804                                         ptype_mapping[i].sw_ptype |=
11805                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11806                                         ptype_mapping[i].sw_ptype |=
11807                                                 RTE_PTYPE_INNER_L4_FRAG;
11808                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11809                                         ptype_mapping[i].sw_ptype |=
11810                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11811                                         in_tunnel = true;
11812                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11813                                            !in_tunnel)
11814                                         ptype_mapping[i].sw_ptype |=
11815                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11816                                 else if (!strncasecmp(name, "IPV6", 4) &&
11817                                          in_tunnel)
11818                                         ptype_mapping[i].sw_ptype |=
11819                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11820                                 else if (!strncasecmp(name, "UDP", 3) &&
11821                                          !in_tunnel)
11822                                         ptype_mapping[i].sw_ptype |=
11823                                                 RTE_PTYPE_L4_UDP;
11824                                 else if (!strncasecmp(name, "UDP", 3) &&
11825                                          in_tunnel)
11826                                         ptype_mapping[i].sw_ptype |=
11827                                                 RTE_PTYPE_INNER_L4_UDP;
11828                                 else if (!strncasecmp(name, "TCP", 3) &&
11829                                          !in_tunnel)
11830                                         ptype_mapping[i].sw_ptype |=
11831                                                 RTE_PTYPE_L4_TCP;
11832                                 else if (!strncasecmp(name, "TCP", 3) &&
11833                                          in_tunnel)
11834                                         ptype_mapping[i].sw_ptype |=
11835                                                 RTE_PTYPE_INNER_L4_TCP;
11836                                 else if (!strncasecmp(name, "SCTP", 4) &&
11837                                          !in_tunnel)
11838                                         ptype_mapping[i].sw_ptype |=
11839                                                 RTE_PTYPE_L4_SCTP;
11840                                 else if (!strncasecmp(name, "SCTP", 4) &&
11841                                          in_tunnel)
11842                                         ptype_mapping[i].sw_ptype |=
11843                                                 RTE_PTYPE_INNER_L4_SCTP;
11844                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11845                                           !strncasecmp(name, "ICMPV6", 6)) &&
11846                                          !in_tunnel)
11847                                         ptype_mapping[i].sw_ptype |=
11848                                                 RTE_PTYPE_L4_ICMP;
11849                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11850                                           !strncasecmp(name, "ICMPV6", 6)) &&
11851                                          in_tunnel)
11852                                         ptype_mapping[i].sw_ptype |=
11853                                                 RTE_PTYPE_INNER_L4_ICMP;
11854                                 else if (!strncasecmp(name, "GTPC", 4)) {
11855                                         ptype_mapping[i].sw_ptype |=
11856                                                 RTE_PTYPE_TUNNEL_GTPC;
11857                                         in_tunnel = true;
11858                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11859                                         ptype_mapping[i].sw_ptype |=
11860                                                 RTE_PTYPE_TUNNEL_GTPU;
11861                                         in_tunnel = true;
11862                                 } else if (!strncasecmp(name, "ESP", 3)) {
11863                                         ptype_mapping[i].sw_ptype |=
11864                                                 RTE_PTYPE_TUNNEL_ESP;
11865                                         in_tunnel = true;
11866                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11867                                         ptype_mapping[i].sw_ptype |=
11868                                                 RTE_PTYPE_TUNNEL_GRENAT;
11869                                         in_tunnel = true;
11870                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
11871                                            !strncasecmp(name, "L2TPV2", 6) ||
11872                                            !strncasecmp(name, "L2TPV3", 6)) {
11873                                         ptype_mapping[i].sw_ptype |=
11874                                                 RTE_PTYPE_TUNNEL_L2TP;
11875                                         in_tunnel = true;
11876                                 }
11877
11878                                 break;
11879                         }
11880                 }
11881         }
11882
11883         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11884                                                 ptype_num, 0);
11885         if (ret)
11886                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
11887
11888         rte_free(ptype_mapping);
11889         rte_free(ptype);
11890         return ret;
11891 }
11892
11893 void
11894 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11895                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11896 {
11897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11898         uint32_t proto_num;
11899         struct rte_pmd_i40e_proto_info *proto;
11900         uint32_t buff_size;
11901         uint32_t i;
11902         int ret;
11903
11904         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11905             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11906                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11907                 return;
11908         }
11909
11910         /* get information about protocol number */
11911         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11912                                        (uint8_t *)&proto_num, sizeof(proto_num),
11913                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11914         if (ret) {
11915                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11916                 return;
11917         }
11918         if (!proto_num) {
11919                 PMD_DRV_LOG(INFO, "No new protocol added");
11920                 return;
11921         }
11922
11923         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11924         proto = rte_zmalloc("new_proto", buff_size, 0);
11925         if (!proto) {
11926                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11927                 return;
11928         }
11929
11930         /* get information about protocol list */
11931         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11932                                         (uint8_t *)proto, buff_size,
11933                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11934         if (ret) {
11935                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11936                 rte_free(proto);
11937                 return;
11938         }
11939
11940         /* Check if GTP is supported. */
11941         for (i = 0; i < proto_num; i++) {
11942                 if (!strncmp(proto[i].name, "GTP", 3)) {
11943                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11944                                 pf->gtp_support = true;
11945                         else
11946                                 pf->gtp_support = false;
11947                         break;
11948                 }
11949         }
11950
11951         /* Check if ESP is supported. */
11952         for (i = 0; i < proto_num; i++) {
11953                 if (!strncmp(proto[i].name, "ESP", 3)) {
11954                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11955                                 pf->esp_support = true;
11956                         else
11957                                 pf->esp_support = false;
11958                         break;
11959                 }
11960         }
11961
11962         /* Update customized pctype info */
11963         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11964                                             proto_num, proto, op);
11965         if (ret)
11966                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11967
11968         /* Update customized ptype info */
11969         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11970                                            proto_num, proto, op);
11971         if (ret)
11972                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11973
11974         rte_free(proto);
11975 }
11976
11977 /* Create a QinQ cloud filter
11978  *
11979  * The Fortville NIC has limited resources for tunnel filters,
11980  * so we can only reuse existing filters.
11981  *
11982  * In step 1 we define which Field Vector fields can be used for
11983  * filter types.
11984  * As we do not have the inner tag defined as a field,
11985  * we have to define it first, by reusing one of L1 entries.
11986  *
11987  * In step 2 we are replacing one of existing filter types with
11988  * a new one for QinQ.
11989  * As we reusing L1 and replacing L2, some of the default filter
11990  * types will disappear,which depends on L1 and L2 entries we reuse.
11991  *
11992  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11993  *
11994  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11995  *              later when we define the cloud filter.
11996  *      a.      Valid_flags.replace_cloud = 0
11997  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11998  *      c.      New_filter = 0x10
11999  *      d.      TR bit = 0xff (optional, not used here)
12000  *      e.      Buffer – 2 entries:
12001  *              i.      Byte 0 = 8 (outer vlan FV index).
12002  *                      Byte 1 = 0 (rsv)
12003  *                      Byte 2-3 = 0x0fff
12004  *              ii.     Byte 0 = 37 (inner vlan FV index).
12005  *                      Byte 1 =0 (rsv)
12006  *                      Byte 2-3 = 0x0fff
12007  *
12008  * Step 2:
12009  * 2.   Create cloud filter using two L1 filters entries: stag and
12010  *              new filter(outer vlan+ inner vlan)
12011  *      a.      Valid_flags.replace_cloud = 1
12012  *      b.      Old_filter = 1 (instead of outer IP)
12013  *      c.      New_filter = 0x10
12014  *      d.      Buffer – 2 entries:
12015  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12016  *                      Byte 1-3 = 0 (rsv)
12017  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12018  *                      Byte 9-11 = 0 (rsv)
12019  */
12020 static int
12021 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12022 {
12023         int ret = -ENOTSUP;
12024         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12025         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12026         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12027         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
12028
12029         if (pf->support_multi_driver) {
12030                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12031                 return ret;
12032         }
12033
12034         /* Init */
12035         memset(&filter_replace, 0,
12036                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12037         memset(&filter_replace_buf, 0,
12038                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12039
12040         /* create L1 filter */
12041         filter_replace.old_filter_type =
12042                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12043         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12044         filter_replace.tr_bit = 0;
12045
12046         /* Prepare the buffer, 2 entries */
12047         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12048         filter_replace_buf.data[0] |=
12049                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12050         /* Field Vector 12b mask */
12051         filter_replace_buf.data[2] = 0xff;
12052         filter_replace_buf.data[3] = 0x0f;
12053         filter_replace_buf.data[4] =
12054                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12055         filter_replace_buf.data[4] |=
12056                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12057         /* Field Vector 12b mask */
12058         filter_replace_buf.data[6] = 0xff;
12059         filter_replace_buf.data[7] = 0x0f;
12060         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12061                         &filter_replace_buf);
12062         if (ret != I40E_SUCCESS)
12063                 return ret;
12064
12065         if (filter_replace.old_filter_type !=
12066             filter_replace.new_filter_type)
12067                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12068                             " original: 0x%x, new: 0x%x",
12069                             dev->device->name,
12070                             filter_replace.old_filter_type,
12071                             filter_replace.new_filter_type);
12072
12073         /* Apply the second L2 cloud filter */
12074         memset(&filter_replace, 0,
12075                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12076         memset(&filter_replace_buf, 0,
12077                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12078
12079         /* create L2 filter, input for L2 filter will be L1 filter  */
12080         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12081         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12082         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12083
12084         /* Prepare the buffer, 2 entries */
12085         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12086         filter_replace_buf.data[0] |=
12087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12088         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12089         filter_replace_buf.data[4] |=
12090                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12091         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12092                         &filter_replace_buf);
12093         if (!ret && (filter_replace.old_filter_type !=
12094                      filter_replace.new_filter_type))
12095                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12096                             " original: 0x%x, new: 0x%x",
12097                             dev->device->name,
12098                             filter_replace.old_filter_type,
12099                             filter_replace.new_filter_type);
12100
12101         return ret;
12102 }
12103
12104 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12105 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12106 #ifdef RTE_ETHDEV_DEBUG_RX
12107 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12108 #endif
12109 #ifdef RTE_ETHDEV_DEBUG_TX
12110 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12111 #endif
12112
12113 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12114                               ETH_I40E_FLOATING_VEB_ARG "=1"
12115                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12116                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12117                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");