drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int i40e_dev_configure(struct rte_eth_dev *dev);
 249 static int i40e_dev_start(struct rte_eth_dev *dev);
 250 static void i40e_dev_stop(struct rte_eth_dev *dev);
 251 static void i40e_dev_close(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 294                           struct ether_addr *mac_addr,
 295                           uint32_t index,
 296                           uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 313                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 314 static void i40e_stat_update_48(struct i40e_hw *hw,
 315                                uint32_t hireg,
 316                                uint32_t loreg,
 317                                bool offset_loaded,
 318                                uint64_t *offset,
 319                                uint64_t *stat);
 320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 322                                        void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              struct ether_addr *addr);
 340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 341                                              struct i40e_macvlan_filter *mv_f,
 342                                              int num,
 343                                              uint16_t vlan);
 344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 346                                     struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 348                                       struct rte_eth_rss_conf *rss_conf);
 349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                         struct rte_eth_udp_tunnel *udp_tunnel);
 353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 358                                 enum rte_filter_type filter_type,
 359                                 enum rte_filter_op filter_op,
 360                                 void *arg);
 361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 362                                   struct rte_eth_dcb_info *dcb_info);
 363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 364 static void i40e_configure_registers(struct i40e_hw *hw);
 365 static void i40e_hw_init(struct rte_eth_dev *dev);
 366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 483         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 484         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 485         .tx_queue_release             = i40e_dev_tx_queue_release,
 486         .dev_led_on                   = i40e_dev_led_on,
 487         .dev_led_off                  = i40e_dev_led_off,
 488         .flow_ctrl_get                = i40e_flow_ctrl_get,
 489         .flow_ctrl_set                = i40e_flow_ctrl_set,
 490         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 491         .mac_addr_add                 = i40e_macaddr_add,
 492         .mac_addr_remove              = i40e_macaddr_remove,
 493         .reta_update                  = i40e_dev_rss_reta_update,
 494         .reta_query                   = i40e_dev_rss_reta_query,
 495         .rss_hash_update              = i40e_dev_rss_hash_update,
 496         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 497         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 498         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 499         .filter_ctrl                  = i40e_dev_filter_ctrl,
 500         .rxq_info_get                 = i40e_rxq_info_get,
 501         .txq_info_get                 = i40e_txq_info_get,
 502         .mirror_rule_set              = i40e_mirror_rule_set,
 503         .mirror_rule_reset            = i40e_mirror_rule_reset,
 504         .timesync_enable              = i40e_timesync_enable,
 505         .timesync_disable             = i40e_timesync_disable,
 506         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 507         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 508         .get_dcb_info                 = i40e_dev_get_dcb_info,
 509         .timesync_adjust_time         = i40e_timesync_adjust_time,
 510         .timesync_read_time           = i40e_timesync_read_time,
 511         .timesync_write_time          = i40e_timesync_write_time,
 512         .get_reg                      = i40e_get_regs,
 513         .get_eeprom_length            = i40e_get_eeprom_length,
 514         .get_eeprom                   = i40e_get_eeprom,
 515         .mac_addr_set                 = i40e_set_default_mac_addr,
 516         .mtu_set                      = i40e_dev_mtu_set,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static struct eth_driver rte_i40e_pmd = {
 633         .pci_drv = {
 634                 .id_table = pci_id_i40e_map,
 635                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 636                 .probe = rte_eth_dev_pci_probe,
 637                 .remove = rte_eth_dev_pci_remove,
 638         },
 639         .eth_dev_init = eth_i40e_dev_init,
 640         .eth_dev_uninit = eth_i40e_dev_uninit,
 641         .dev_private_size = sizeof(struct i40e_adapter),
 642 };
 643
 644 static inline int
 645 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 646                                      struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = link;
 649         struct rte_eth_link *src = &(dev->data->dev_link);
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 static inline int
 659 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 660                                       struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = &(dev->data->dev_link);
 663         struct rte_eth_link *src = link;
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 673 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 674 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 675
 676 #ifndef I40E_GLQF_ORT
 677 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 678 #endif
 679 #ifndef I40E_GLQF_PIT
 680 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 681 #endif
 682
 683 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 684 {
 685         /*
 686          * Initialize registers for flexible payload, which should be set by NVM.
 687          * This should be removed from code once it is fixed in NVM.
 688          */
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 697         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 699         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 700         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 701
 702         /* Initialize registers for parsing packet type of QinQ */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 704         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 705 }
 706
 707 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 708
 709 /*
 710  * Add a ethertype filter to drop all flow control frames transmitted
 711  * from VSIs.
 712 */
 713 static void
 714 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 715 {
 716         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 717         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 718                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 719                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 720         int ret;
 721
 722         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 723                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 724                                 pf->main_vsi_seid, 0,
 725                                 TRUE, NULL, NULL);
 726         if (ret)
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to add filter to drop flow control frames from VSIs.");
 729 }
 730
 731 static int
 732 floating_veb_list_handler(__rte_unused const char *key,
 733                           const char *floating_veb_value,
 734                           void *opaque)
 735 {
 736         int idx = 0;
 737         unsigned int count = 0;
 738         char *end = NULL;
 739         int min, max;
 740         bool *vf_floating_veb = opaque;
 741
 742         while (isblank(*floating_veb_value))
 743                 floating_veb_value++;
 744
 745         /* Reset floating VEB configuration for VFs */
 746         for (idx = 0; idx < I40E_MAX_VF; idx++)
 747                 vf_floating_veb[idx] = false;
 748
 749         min = I40E_MAX_VF;
 750         do {
 751                 while (isblank(*floating_veb_value))
 752                         floating_veb_value++;
 753                 if (*floating_veb_value == '\0')
 754                         return -1;
 755                 errno = 0;
 756                 idx = strtoul(floating_veb_value, &end, 10);
 757                 if (errno || end == NULL)
 758                         return -1;
 759                 while (isblank(*end))
 760                         end++;
 761                 if (*end == '-') {
 762                         min = idx;
 763                 } else if ((*end == ';') || (*end == '\0')) {
 764                         max = idx;
 765                         if (min == I40E_MAX_VF)
 766                                 min = idx;
 767                         if (max >= I40E_MAX_VF)
 768                                 max = I40E_MAX_VF - 1;
 769                         for (idx = min; idx <= max; idx++) {
 770                                 vf_floating_veb[idx] = true;
 771                                 count++;
 772                         }
 773                         min = I40E_MAX_VF;
 774                 } else {
 775                         return -1;
 776                 }
 777                 floating_veb_value = end + 1;
 778         } while (*end != '\0');
 779
 780         if (count == 0)
 781                 return -1;
 782
 783         return 0;
 784 }
 785
 786 static void
 787 config_vf_floating_veb(struct rte_devargs *devargs,
 788                        uint16_t floating_veb,
 789                        bool *vf_floating_veb)
 790 {
 791         struct rte_kvargs *kvlist;
 792         int i;
 793         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 794
 795         if (!floating_veb)
 796                 return;
 797         /* All the VFs attach to the floating VEB by default
 798          * when the floating VEB is enabled.
 799          */
 800         for (i = 0; i < I40E_MAX_VF; i++)
 801                 vf_floating_veb[i] = true;
 802
 803         if (devargs == NULL)
 804                 return;
 805
 806         kvlist = rte_kvargs_parse(devargs->args, NULL);
 807         if (kvlist == NULL)
 808                 return;
 809
 810         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 811                 rte_kvargs_free(kvlist);
 812                 return;
 813         }
 814         /* When the floating_veb_list parameter exists, all the VFs
 815          * will attach to the legacy VEB firstly, then configure VFs
 816          * to the floating VEB according to the floating_veb_list.
 817          */
 818         if (rte_kvargs_process(kvlist, floating_veb_list,
 819                                floating_veb_list_handler,
 820                                vf_floating_veb) < 0) {
 821                 rte_kvargs_free(kvlist);
 822                 return;
 823         }
 824         rte_kvargs_free(kvlist);
 825 }
 826
 827 static int
 828 i40e_check_floating_handler(__rte_unused const char *key,
 829                             const char *value,
 830                             __rte_unused void *opaque)
 831 {
 832         if (strcmp(value, "1"))
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 static int
 839 is_floating_veb_supported(struct rte_devargs *devargs)
 840 {
 841         struct rte_kvargs *kvlist;
 842         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 843
 844         if (devargs == NULL)
 845                 return 0;
 846
 847         kvlist = rte_kvargs_parse(devargs->args, NULL);
 848         if (kvlist == NULL)
 849                 return 0;
 850
 851         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 852                 rte_kvargs_free(kvlist);
 853                 return 0;
 854         }
 855         /* Floating VEB is enabled when there's key-value:
 856          * enable_floating_veb=1
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_key,
 859                                i40e_check_floating_handler, NULL) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return 0;
 862         }
 863         rte_kvargs_free(kvlist);
 864
 865         return 1;
 866 }
 867
 868 static void
 869 config_floating_veb(struct rte_eth_dev *dev)
 870 {
 871         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874
 875         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 876
 877         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 878                 pf->floating_veb =
 879                         is_floating_veb_supported(pci_dev->device.devargs);
 880                 config_vf_floating_veb(pci_dev->device.devargs,
 881                                        pf->floating_veb,
 882                                        pf->floating_veb_list);
 883         } else {
 884                 pf->floating_veb = false;
 885         }
 886 }
 887
 888 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 889 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 890
 891 static int
 892 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 893 {
 894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 895         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 896         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 897         int ret;
 898
 899         struct rte_hash_parameters ethertype_hash_params = {
 900                 .name = ethertype_hash_name,
 901                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 902                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 903                 .hash_func = rte_hash_crc,
 904         };
 905
 906         /* Initialize ethertype filter rule list and hash */
 907         TAILQ_INIT(&ethertype_rule->ethertype_list);
 908         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 909                  "ethertype_%s", dev->data->name);
 910         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 911         if (!ethertype_rule->hash_table) {
 912                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 913                 return -EINVAL;
 914         }
 915         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 916                                        sizeof(struct i40e_ethertype_filter *) *
 917                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 918                                        0);
 919         if (!ethertype_rule->hash_map) {
 920                 PMD_INIT_LOG(ERR,
 921                              "Failed to allocate memory for ethertype hash map!");
 922                 ret = -ENOMEM;
 923                 goto err_ethertype_hash_map_alloc;
 924         }
 925
 926         return 0;
 927
 928 err_ethertype_hash_map_alloc:
 929         rte_hash_free(ethertype_rule->hash_table);
 930
 931         return ret;
 932 }
 933
 934 static int
 935 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 936 {
 937         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 938         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 939         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 940         int ret;
 941
 942         struct rte_hash_parameters tunnel_hash_params = {
 943                 .name = tunnel_hash_name,
 944                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 945                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 946                 .hash_func = rte_hash_crc,
 947         };
 948
 949         /* Initialize tunnel filter rule list and hash */
 950         TAILQ_INIT(&tunnel_rule->tunnel_list);
 951         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 952                  "tunnel_%s", dev->data->name);
 953         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 954         if (!tunnel_rule->hash_table) {
 955                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 956                 return -EINVAL;
 957         }
 958         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 959                                     sizeof(struct i40e_tunnel_filter *) *
 960                                     I40E_MAX_TUNNEL_FILTER_NUM,
 961                                     0);
 962         if (!tunnel_rule->hash_map) {
 963                 PMD_INIT_LOG(ERR,
 964                              "Failed to allocate memory for tunnel hash map!");
 965                 ret = -ENOMEM;
 966                 goto err_tunnel_hash_map_alloc;
 967         }
 968
 969         return 0;
 970
 971 err_tunnel_hash_map_alloc:
 972         rte_hash_free(tunnel_rule->hash_table);
 973
 974         return ret;
 975 }
 976
 977 static int
 978 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 979 {
 980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 981         struct i40e_fdir_info *fdir_info = &pf->fdir;
 982         char fdir_hash_name[RTE_HASH_NAMESIZE];
 983         int ret;
 984
 985         struct rte_hash_parameters fdir_hash_params = {
 986                 .name = fdir_hash_name,
 987                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 988                 .key_len = sizeof(struct rte_eth_fdir_input),
 989                 .hash_func = rte_hash_crc,
 990         };
 991
 992         /* Initialize flow director filter rule list and hash */
 993         TAILQ_INIT(&fdir_info->fdir_list);
 994         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 995                  "fdir_%s", dev->data->name);
 996         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 997         if (!fdir_info->hash_table) {
 998                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 999                 return -EINVAL;
1000         }
1001         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1002                                           sizeof(struct i40e_fdir_filter *) *
1003                                           I40E_MAX_FDIR_FILTER_NUM,
1004                                           0);
1005         if (!fdir_info->hash_map) {
1006                 PMD_INIT_LOG(ERR,
1007                              "Failed to allocate memory for fdir hash map!");
1008                 ret = -ENOMEM;
1009                 goto err_fdir_hash_map_alloc;
1010         }
1011         return 0;
1012
1013 err_fdir_hash_map_alloc:
1014         rte_hash_free(fdir_info->hash_table);
1015
1016         return ret;
1017 }
1018
1019 static int
1020 eth_i40e_dev_init(struct rte_eth_dev *dev)
1021 {
1022         struct rte_pci_device *pci_dev;
1023         struct rte_intr_handle *intr_handle;
1024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         struct i40e_vsi *vsi;
1027         int ret;
1028         uint32_t len;
1029         uint8_t aq_fail = 0;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         dev->dev_ops = &i40e_eth_dev_ops;
1034         dev->rx_pkt_burst = i40e_recv_pkts;
1035         dev->tx_pkt_burst = i40e_xmit_pkts;
1036         dev->tx_pkt_prepare = i40e_prep_pkts;
1037
1038         /* for secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX function */
1041         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1042                 i40e_set_rx_function(dev);
1043                 i40e_set_tx_function(dev);
1044                 return 0;
1045         }
1046         pci_dev = I40E_DEV_TO_PCI(dev);
1047         intr_handle = &pci_dev->intr_handle;
1048
1049         rte_eth_copy_pci_info(dev, pci_dev);
1050         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1051
1052         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1053         pf->adapter->eth_dev = dev;
1054         pf->dev_data = dev->data;
1055
1056         hw->back = I40E_PF_TO_ADAPTER(pf);
1057         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1058         if (!hw->hw_addr) {
1059                 PMD_INIT_LOG(ERR,
1060                         "Hardware is not available, as address is NULL");
1061                 return -ENODEV;
1062         }
1063
1064         hw->vendor_id = pci_dev->id.vendor_id;
1065         hw->device_id = pci_dev->id.device_id;
1066         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1067         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1068         hw->bus.device = pci_dev->addr.devid;
1069         hw->bus.func = pci_dev->addr.function;
1070         hw->adapter_stopped = 0;
1071
1072         /* Make sure all is clean before doing PF reset */
1073         i40e_clear_hw(hw);
1074
1075         /* Initialize the hardware */
1076         i40e_hw_init(dev);
1077
1078         /* Reset here to make sure all is clean for each PF */
1079         ret = i40e_pf_reset(hw);
1080         if (ret) {
1081                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1082                 return ret;
1083         }
1084
1085         /* Initialize the shared code (base driver) */
1086         ret = i40e_init_shared_code(hw);
1087         if (ret) {
1088                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1089                 return ret;
1090         }
1091
1092         /*
1093          * To work around the NVM issue, initialize registers
1094          * for flexible payload and packet type of QinQ by
1095          * software. It should be removed once issues are fixed
1096          * in NVM.
1097          */
1098         i40e_GLQF_reg_init(hw);
1099
1100         /* Initialize the input set for filters (hash and fd) to default value */
1101         i40e_filter_input_set_init(pf);
1102
1103         /* Initialize the parameters for adminq */
1104         i40e_init_adminq_parameter(hw);
1105         ret = i40e_init_adminq(hw);
1106         if (ret != I40E_SUCCESS) {
1107                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1108                 return -EIO;
1109         }
1110         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1111                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1112                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1113                      ((hw->nvm.version >> 12) & 0xf),
1114                      ((hw->nvm.version >> 4) & 0xff),
1115                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1116
1117         /* Need the special FW version to support floating VEB */
1118         config_floating_veb(dev);
1119         /* Clear PXE mode */
1120         i40e_clear_pxe_mode(hw);
1121         ret = i40e_dev_sync_phy_type(hw);
1122         if (ret) {
1123                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1124                 goto err_sync_phy_type;
1125         }
1126         /*
1127          * On X710, performance number is far from the expectation on recent
1128          * firmware versions. The fix for this issue may not be integrated in
1129          * the following firmware version. So the workaround in software driver
1130          * is needed. It needs to modify the initial values of 3 internal only
1131          * registers. Note that the workaround can be removed when it is fixed
1132          * in firmware in the future.
1133          */
1134         i40e_configure_registers(hw);
1135
1136         /* Get hw capabilities */
1137         ret = i40e_get_cap(hw);
1138         if (ret != I40E_SUCCESS) {
1139                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1140                 goto err_get_capabilities;
1141         }
1142
1143         /* Initialize parameters for PF */
1144         ret = i40e_pf_parameter_init(dev);
1145         if (ret != 0) {
1146                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1147                 goto err_parameter_init;
1148         }
1149
1150         /* Initialize the queue management */
1151         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1152         if (ret < 0) {
1153                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1154                 goto err_qp_pool_init;
1155         }
1156         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1157                                 hw->func_caps.num_msix_vectors - 1);
1158         if (ret < 0) {
1159                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1160                 goto err_msix_pool_init;
1161         }
1162
1163         /* Initialize lan hmc */
1164         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1165                                 hw->func_caps.num_rx_qp, 0, 0);
1166         if (ret != I40E_SUCCESS) {
1167                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1168                 goto err_init_lan_hmc;
1169         }
1170
1171         /* Configure lan hmc */
1172         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1173         if (ret != I40E_SUCCESS) {
1174                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1175                 goto err_configure_lan_hmc;
1176         }
1177
1178         /* Get and check the mac address */
1179         i40e_get_mac_addr(hw, hw->mac.addr);
1180         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1181                 PMD_INIT_LOG(ERR, "mac address is not valid");
1182                 ret = -EIO;
1183                 goto err_get_mac_addr;
1184         }
1185         /* Copy the permanent MAC address */
1186         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1187                         (struct ether_addr *) hw->mac.perm_addr);
1188
1189         /* Disable flow control */
1190         hw->fc.requested_mode = I40E_FC_NONE;
1191         i40e_set_fc(hw, &aq_fail, TRUE);
1192
1193         /* Set the global registers with default ether type value */
1194         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR,
1197                         "Failed to set the default outer VLAN ether type");
1198                 goto err_setup_pf_switch;
1199         }
1200
1201         /* PF setup, which includes VSI setup */
1202         ret = i40e_pf_setup(pf);
1203         if (ret) {
1204                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1205                 goto err_setup_pf_switch;
1206         }
1207
1208         /* reset all stats of the device, including pf and main vsi */
1209         i40e_dev_stats_reset(dev);
1210
1211         vsi = pf->main_vsi;
1212
1213         /* Disable double vlan by default */
1214         i40e_vsi_config_double_vlan(vsi, FALSE);
1215
1216         /* Disable S-TAG identification when floating_veb is disabled */
1217         if (!pf->floating_veb) {
1218                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1219                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1220                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1221                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1222                 }
1223         }
1224
1225         if (!vsi->max_macaddrs)
1226                 len = ETHER_ADDR_LEN;
1227         else
1228                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1229
1230         /* Should be after VSI initialized */
1231         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1232         if (!dev->data->mac_addrs) {
1233                 PMD_INIT_LOG(ERR,
1234                         "Failed to allocated memory for storing mac address");
1235                 goto err_mac_alloc;
1236         }
1237         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1238                                         &dev->data->mac_addrs[0]);
1239
1240         /* initialize pf host driver to setup SRIOV resource if applicable */
1241         i40e_pf_host_init(dev);
1242
1243         /* register callback func to eal lib */
1244         rte_intr_callback_register(intr_handle,
1245                                    i40e_dev_interrupt_handler, dev);
1246
1247         /* configure and enable device interrupt */
1248         i40e_pf_config_irq0(hw, TRUE);
1249         i40e_pf_enable_irq0(hw);
1250
1251         /* enable uio intr after callback register */
1252         rte_intr_enable(intr_handle);
1253         /*
1254          * Add an ethertype filter to drop all flow control frames transmitted
1255          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1256          * frames to wire.
1257          */
1258         i40e_add_tx_flow_control_drop_filter(pf);
1259
1260         /* Set the max frame size to 0x2600 by default,
1261          * in case other drivers changed the default value.
1262          */
1263         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1264
1265         /* initialize mirror rule list */
1266         TAILQ_INIT(&pf->mirror_list);
1267
1268         /* Init dcb to sw mode by default */
1269         ret = i40e_dcb_init_configure(dev, TRUE);
1270         if (ret != I40E_SUCCESS) {
1271                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1272                 pf->flags &= ~I40E_FLAG_DCB;
1273         }
1274
1275         ret = i40e_init_ethtype_filter_list(dev);
1276         if (ret < 0)
1277                 goto err_init_ethtype_filter_list;
1278         ret = i40e_init_tunnel_filter_list(dev);
1279         if (ret < 0)
1280                 goto err_init_tunnel_filter_list;
1281         ret = i40e_init_fdir_filter_list(dev);
1282         if (ret < 0)
1283                 goto err_init_fdir_filter_list;
1284
1285         return 0;
1286
1287 err_init_fdir_filter_list:
1288         rte_free(pf->tunnel.hash_table);
1289         rte_free(pf->tunnel.hash_map);
1290 err_init_tunnel_filter_list:
1291         rte_free(pf->ethertype.hash_table);
1292         rte_free(pf->ethertype.hash_map);
1293 err_init_ethtype_filter_list:
1294         rte_free(dev->data->mac_addrs);
1295 err_mac_alloc:
1296         i40e_vsi_release(pf->main_vsi);
1297 err_setup_pf_switch:
1298 err_get_mac_addr:
1299 err_configure_lan_hmc:
1300         (void)i40e_shutdown_lan_hmc(hw);
1301 err_init_lan_hmc:
1302         i40e_res_pool_destroy(&pf->msix_pool);
1303 err_msix_pool_init:
1304         i40e_res_pool_destroy(&pf->qp_pool);
1305 err_qp_pool_init:
1306 err_parameter_init:
1307 err_get_capabilities:
1308 err_sync_phy_type:
1309         (void)i40e_shutdown_adminq(hw);
1310
1311         return ret;
1312 }
1313
1314 static void
1315 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1316 {
1317         struct i40e_ethertype_filter *p_ethertype;
1318         struct i40e_ethertype_rule *ethertype_rule;
1319
1320         ethertype_rule = &pf->ethertype;
1321         /* Remove all ethertype filter rules and hash */
1322         if (ethertype_rule->hash_map)
1323                 rte_free(ethertype_rule->hash_map);
1324         if (ethertype_rule->hash_table)
1325                 rte_hash_free(ethertype_rule->hash_table);
1326
1327         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1328                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1329                              p_ethertype, rules);
1330                 rte_free(p_ethertype);
1331         }
1332 }
1333
1334 static void
1335 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1336 {
1337         struct i40e_tunnel_filter *p_tunnel;
1338         struct i40e_tunnel_rule *tunnel_rule;
1339
1340         tunnel_rule = &pf->tunnel;
1341         /* Remove all tunnel director rules and hash */
1342         if (tunnel_rule->hash_map)
1343                 rte_free(tunnel_rule->hash_map);
1344         if (tunnel_rule->hash_table)
1345                 rte_hash_free(tunnel_rule->hash_table);
1346
1347         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1348                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1349                 rte_free(p_tunnel);
1350         }
1351 }
1352
1353 static void
1354 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1355 {
1356         struct i40e_fdir_filter *p_fdir;
1357         struct i40e_fdir_info *fdir_info;
1358
1359         fdir_info = &pf->fdir;
1360         /* Remove all flow director rules and hash */
1361         if (fdir_info->hash_map)
1362                 rte_free(fdir_info->hash_map);
1363         if (fdir_info->hash_table)
1364                 rte_hash_free(fdir_info->hash_table);
1365
1366         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1367                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1368                 rte_free(p_fdir);
1369         }
1370 }
1371
1372 static int
1373 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1374 {
1375         struct i40e_pf *pf;
1376         struct rte_pci_device *pci_dev;
1377         struct rte_intr_handle *intr_handle;
1378         struct i40e_hw *hw;
1379         struct i40e_filter_control_settings settings;
1380         struct rte_flow *p_flow;
1381         int ret;
1382         uint8_t aq_fail = 0;
1383
1384         PMD_INIT_FUNC_TRACE();
1385
1386         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1387                 return 0;
1388
1389         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1390         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1391         pci_dev = I40E_DEV_TO_PCI(dev);
1392         intr_handle = &pci_dev->intr_handle;
1393
1394         if (hw->adapter_stopped == 0)
1395                 i40e_dev_close(dev);
1396
1397         dev->dev_ops = NULL;
1398         dev->rx_pkt_burst = NULL;
1399         dev->tx_pkt_burst = NULL;
1400
1401         /* Clear PXE mode */
1402         i40e_clear_pxe_mode(hw);
1403
1404         /* Unconfigure filter control */
1405         memset(&settings, 0, sizeof(settings));
1406         ret = i40e_set_filter_control(hw, &settings);
1407         if (ret)
1408                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1409                                         ret);
1410
1411         /* Disable flow control */
1412         hw->fc.requested_mode = I40E_FC_NONE;
1413         i40e_set_fc(hw, &aq_fail, TRUE);
1414
1415         /* uninitialize pf host driver */
1416         i40e_pf_host_uninit(dev);
1417
1418         rte_free(dev->data->mac_addrs);
1419         dev->data->mac_addrs = NULL;
1420
1421         /* disable uio intr before callback unregister */
1422         rte_intr_disable(intr_handle);
1423
1424         /* register callback func to eal lib */
1425         rte_intr_callback_unregister(intr_handle,
1426                                      i40e_dev_interrupt_handler, dev);
1427
1428         i40e_rm_ethtype_filter_list(pf);
1429         i40e_rm_tunnel_filter_list(pf);
1430         i40e_rm_fdir_filter_list(pf);
1431
1432         /* Remove all flows */
1433         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1434                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1435                 rte_free(p_flow);
1436         }
1437
1438         return 0;
1439 }
1440
1441 static int
1442 i40e_dev_configure(struct rte_eth_dev *dev)
1443 {
1444         struct i40e_adapter *ad =
1445                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1446         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1447         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1448         int i, ret;
1449
1450         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1451          * bulk allocation or vector Rx preconditions we will reset it.
1452          */
1453         ad->rx_bulk_alloc_allowed = true;
1454         ad->rx_vec_allowed = true;
1455         ad->tx_simple_allowed = true;
1456         ad->tx_vec_allowed = true;
1457
1458         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1459                 ret = i40e_fdir_setup(pf);
1460                 if (ret != I40E_SUCCESS) {
1461                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1462                         return -ENOTSUP;
1463                 }
1464                 ret = i40e_fdir_configure(dev);
1465                 if (ret < 0) {
1466                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1467                         goto err;
1468                 }
1469         } else
1470                 i40e_fdir_teardown(pf);
1471
1472         ret = i40e_dev_init_vlan(dev);
1473         if (ret < 0)
1474                 goto err;
1475
1476         /* VMDQ setup.
1477          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1478          *  RSS setting have different requirements.
1479          *  General PMD driver call sequence are NIC init, configure,
1480          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1481          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1482          *  applicable. So, VMDQ setting has to be done before
1483          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1484          *  For RSS setting, it will try to calculate actual configured RX queue
1485          *  number, which will be available after rx_queue_setup(). dev_start()
1486          *  function is good to place RSS setup.
1487          */
1488         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1489                 ret = i40e_vmdq_setup(dev);
1490                 if (ret)
1491                         goto err;
1492         }
1493
1494         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1495                 ret = i40e_dcb_setup(dev);
1496                 if (ret) {
1497                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1498                         goto err_dcb;
1499                 }
1500         }
1501
1502         TAILQ_INIT(&pf->flow_list);
1503
1504         return 0;
1505
1506 err_dcb:
1507         /* need to release vmdq resource if exists */
1508         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1509                 i40e_vsi_release(pf->vmdq[i].vsi);
1510                 pf->vmdq[i].vsi = NULL;
1511         }
1512         rte_free(pf->vmdq);
1513         pf->vmdq = NULL;
1514 err:
1515         /* need to release fdir resource if exists */
1516         i40e_fdir_teardown(pf);
1517         return ret;
1518 }
1519
1520 void
1521 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1522 {
1523         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1524         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1525         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1526         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1527         uint16_t msix_vect = vsi->msix_intr;
1528         uint16_t i;
1529
1530         for (i = 0; i < vsi->nb_qps; i++) {
1531                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1532                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1533                 rte_wmb();
1534         }
1535
1536         if (vsi->type != I40E_VSI_SRIOV) {
1537                 if (!rte_intr_allow_others(intr_handle)) {
1538                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1539                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1540                         I40E_WRITE_REG(hw,
1541                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1542                                        0);
1543                 } else {
1544                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1545                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1546                         I40E_WRITE_REG(hw,
1547                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1548                                                        msix_vect - 1), 0);
1549                 }
1550         } else {
1551                 uint32_t reg;
1552                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1553                         vsi->user_param + (msix_vect - 1);
1554
1555                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1556                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1557         }
1558         I40E_WRITE_FLUSH(hw);
1559 }
1560
1561 static void
1562 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1563                        int base_queue, int nb_queue)
1564 {
1565         int i;
1566         uint32_t val;
1567         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1568
1569         /* Bind all RX queues to allocated MSIX interrupt */
1570         for (i = 0; i < nb_queue; i++) {
1571                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1572                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1573                         ((base_queue + i + 1) <<
1574                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1575                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1576                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1577
1578                 if (i == nb_queue - 1)
1579                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1580                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1581         }
1582
1583         /* Write first RX queue to Link list register as the head element */
1584         if (vsi->type != I40E_VSI_SRIOV) {
1585                 uint16_t interval =
1586                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1587
1588                 if (msix_vect == I40E_MISC_VEC_ID) {
1589                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1590                                        (base_queue <<
1591                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1592                                        (0x0 <<
1593                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1594                         I40E_WRITE_REG(hw,
1595                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1596                                        interval);
1597                 } else {
1598                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1599                                        (base_queue <<
1600                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1601                                        (0x0 <<
1602                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1603                         I40E_WRITE_REG(hw,
1604                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1605                                                        msix_vect - 1),
1606                                        interval);
1607                 }
1608         } else {
1609                 uint32_t reg;
1610
1611                 if (msix_vect == I40E_MISC_VEC_ID) {
1612                         I40E_WRITE_REG(hw,
1613                                        I40E_VPINT_LNKLST0(vsi->user_param),
1614                                        (base_queue <<
1615                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1616                                        (0x0 <<
1617                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1618                 } else {
1619                         /* num_msix_vectors_vf needs to minus irq0 */
1620                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1621                                 vsi->user_param + (msix_vect - 1);
1622
1623                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1624                                        (base_queue <<
1625                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1628                 }
1629         }
1630
1631         I40E_WRITE_FLUSH(hw);
1632 }
1633
1634 void
1635 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1636 {
1637         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1638         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1639         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1640         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1641         uint16_t msix_vect = vsi->msix_intr;
1642         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1643         uint16_t queue_idx = 0;
1644         int record = 0;
1645         uint32_t val;
1646         int i;
1647
1648         for (i = 0; i < vsi->nb_qps; i++) {
1649                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1650                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1651         }
1652
1653         /* INTENA flag is not auto-cleared for interrupt */
1654         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1655         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1656                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1657                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1658         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1659
1660         /* VF bind interrupt */
1661         if (vsi->type == I40E_VSI_SRIOV) {
1662                 __vsi_queues_bind_intr(vsi, msix_vect,
1663                                        vsi->base_queue, vsi->nb_qps);
1664                 return;
1665         }
1666
1667         /* PF & VMDq bind interrupt */
1668         if (rte_intr_dp_is_en(intr_handle)) {
1669                 if (vsi->type == I40E_VSI_MAIN) {
1670                         queue_idx = 0;
1671                         record = 1;
1672                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1673                         struct i40e_vsi *main_vsi =
1674                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1675                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1676                         record = 1;
1677                 }
1678         }
1679
1680         for (i = 0; i < vsi->nb_used_qps; i++) {
1681                 if (nb_msix <= 1) {
1682                         if (!rte_intr_allow_others(intr_handle))
1683                                 /* allow to share MISC_VEC_ID */
1684                                 msix_vect = I40E_MISC_VEC_ID;
1685
1686                         /* no enough msix_vect, map all to one */
1687                         __vsi_queues_bind_intr(vsi, msix_vect,
1688                                                vsi->base_queue + i,
1689                                                vsi->nb_used_qps - i);
1690                         for (; !!record && i < vsi->nb_used_qps; i++)
1691                                 intr_handle->intr_vec[queue_idx + i] =
1692                                         msix_vect;
1693                         break;
1694                 }
1695                 /* 1:1 queue/msix_vect mapping */
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue + i, 1);
1698                 if (!!record)
1699                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1700
1701                 msix_vect++;
1702                 nb_msix--;
1703         }
1704 }
1705
1706 static void
1707 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1708 {
1709         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1710         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1711         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1712         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1713         uint16_t interval = i40e_calc_itr_interval(\
1714                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1715         uint16_t msix_intr, i;
1716
1717         if (rte_intr_allow_others(intr_handle))
1718                 for (i = 0; i < vsi->nb_msix; i++) {
1719                         msix_intr = vsi->msix_intr + i;
1720                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1721                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1722                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1723                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1724                                 (interval <<
1725                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1726                 }
1727         else
1728                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1729                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1730                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1731                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1732                                (interval <<
1733                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1734
1735         I40E_WRITE_FLUSH(hw);
1736 }
1737
1738 static void
1739 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1740 {
1741         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1742         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1743         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1744         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1745         uint16_t msix_intr, i;
1746
1747         if (rte_intr_allow_others(intr_handle))
1748                 for (i = 0; i < vsi->nb_msix; i++) {
1749                         msix_intr = vsi->msix_intr + i;
1750                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1751                                        0);
1752                 }
1753         else
1754                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1755
1756         I40E_WRITE_FLUSH(hw);
1757 }
1758
1759 static inline uint8_t
1760 i40e_parse_link_speeds(uint16_t link_speeds)
1761 {
1762         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1763
1764         if (link_speeds & ETH_LINK_SPEED_40G)
1765                 link_speed |= I40E_LINK_SPEED_40GB;
1766         if (link_speeds & ETH_LINK_SPEED_25G)
1767                 link_speed |= I40E_LINK_SPEED_25GB;
1768         if (link_speeds & ETH_LINK_SPEED_20G)
1769                 link_speed |= I40E_LINK_SPEED_20GB;
1770         if (link_speeds & ETH_LINK_SPEED_10G)
1771                 link_speed |= I40E_LINK_SPEED_10GB;
1772         if (link_speeds & ETH_LINK_SPEED_1G)
1773                 link_speed |= I40E_LINK_SPEED_1GB;
1774         if (link_speeds & ETH_LINK_SPEED_100M)
1775                 link_speed |= I40E_LINK_SPEED_100MB;
1776
1777         return link_speed;
1778 }
1779
1780 static int
1781 i40e_phy_conf_link(struct i40e_hw *hw,
1782                    uint8_t abilities,
1783                    uint8_t force_speed)
1784 {
1785         enum i40e_status_code status;
1786         struct i40e_aq_get_phy_abilities_resp phy_ab;
1787         struct i40e_aq_set_phy_config phy_conf;
1788         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1789                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1790                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1791                         I40E_AQ_PHY_FLAG_LOW_POWER;
1792         const uint8_t advt = I40E_LINK_SPEED_40GB |
1793                         I40E_LINK_SPEED_25GB |
1794                         I40E_LINK_SPEED_10GB |
1795                         I40E_LINK_SPEED_1GB |
1796                         I40E_LINK_SPEED_100MB;
1797         int ret = -ENOTSUP;
1798
1799
1800         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1801                                               NULL);
1802         if (status)
1803                 return ret;
1804
1805         memset(&phy_conf, 0, sizeof(phy_conf));
1806
1807         /* bits 0-2 use the values from get_phy_abilities_resp */
1808         abilities &= ~mask;
1809         abilities |= phy_ab.abilities & mask;
1810
1811         /* update ablities and speed */
1812         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1813                 phy_conf.link_speed = advt;
1814         else
1815                 phy_conf.link_speed = force_speed;
1816
1817         phy_conf.abilities = abilities;
1818
1819         /* use get_phy_abilities_resp value for the rest */
1820         phy_conf.phy_type = phy_ab.phy_type;
1821         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1822         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1823         phy_conf.eee_capability = phy_ab.eee_capability;
1824         phy_conf.eeer = phy_ab.eeer_val;
1825         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1826
1827         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1828                     phy_ab.abilities, phy_ab.link_speed);
1829         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1830                     phy_conf.abilities, phy_conf.link_speed);
1831
1832         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1833         if (status)
1834                 return ret;
1835
1836         return I40E_SUCCESS;
1837 }
1838
1839 static int
1840 i40e_apply_link_speed(struct rte_eth_dev *dev)
1841 {
1842         uint8_t speed;
1843         uint8_t abilities = 0;
1844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct rte_eth_conf *conf = &dev->data->dev_conf;
1846
1847         speed = i40e_parse_link_speeds(conf->link_speeds);
1848         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1849         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1850                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1851         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1852
1853         /* Skip changing speed on 40G interfaces, FW does not support */
1854         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1855                 speed =  I40E_LINK_SPEED_UNKNOWN;
1856                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1857         }
1858
1859         return i40e_phy_conf_link(hw, abilities, speed);
1860 }
1861
1862 static int
1863 i40e_dev_start(struct rte_eth_dev *dev)
1864 {
1865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867         struct i40e_vsi *main_vsi = pf->main_vsi;
1868         int ret, i;
1869         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1870         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1871         uint32_t intr_vector = 0;
1872
1873         hw->adapter_stopped = 0;
1874
1875         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1876                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1877                              dev->data->port_id);
1878                 return -EINVAL;
1879         }
1880
1881         rte_intr_disable(intr_handle);
1882
1883         if ((rte_intr_cap_multiple(intr_handle) ||
1884              !RTE_ETH_DEV_SRIOV(dev).active) &&
1885             dev->data->dev_conf.intr_conf.rxq != 0) {
1886                 intr_vector = dev->data->nb_rx_queues;
1887                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1888                 if (ret)
1889                         return ret;
1890         }
1891
1892         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1893                 intr_handle->intr_vec =
1894                         rte_zmalloc("intr_vec",
1895                                     dev->data->nb_rx_queues * sizeof(int),
1896                                     0);
1897                 if (!intr_handle->intr_vec) {
1898                         PMD_INIT_LOG(ERR,
1899                                 "Failed to allocate %d rx_queues intr_vec",
1900                                 dev->data->nb_rx_queues);
1901                         return -ENOMEM;
1902                 }
1903         }
1904
1905         /* Initialize VSI */
1906         ret = i40e_dev_rxtx_init(pf);
1907         if (ret != I40E_SUCCESS) {
1908                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1909                 goto err_up;
1910         }
1911
1912         /* Map queues with MSIX interrupt */
1913         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1914                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1915         i40e_vsi_queues_bind_intr(main_vsi);
1916         i40e_vsi_enable_queues_intr(main_vsi);
1917
1918         /* Map VMDQ VSI queues with MSIX interrupt */
1919         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1920                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1921                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1922                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1923         }
1924
1925         /* enable FDIR MSIX interrupt */
1926         if (pf->fdir.fdir_vsi) {
1927                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1928                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1929         }
1930
1931         /* Enable all queues which have been configured */
1932         ret = i40e_dev_switch_queues(pf, TRUE);
1933         if (ret != I40E_SUCCESS) {
1934                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1935                 goto err_up;
1936         }
1937
1938         /* Enable receiving broadcast packets */
1939         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1940         if (ret != I40E_SUCCESS)
1941                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1942
1943         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1944                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1945                                                 true, NULL);
1946                 if (ret != I40E_SUCCESS)
1947                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1948         }
1949
1950         /* Apply link configure */
1951         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1952                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1953                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1954                                 ETH_LINK_SPEED_40G)) {
1955                 PMD_DRV_LOG(ERR, "Invalid link setting");
1956                 goto err_up;
1957         }
1958         ret = i40e_apply_link_speed(dev);
1959         if (I40E_SUCCESS != ret) {
1960                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1961                 goto err_up;
1962         }
1963
1964         if (!rte_intr_allow_others(intr_handle)) {
1965                 rte_intr_callback_unregister(intr_handle,
1966                                              i40e_dev_interrupt_handler,
1967                                              (void *)dev);
1968                 /* configure and enable device interrupt */
1969                 i40e_pf_config_irq0(hw, FALSE);
1970                 i40e_pf_enable_irq0(hw);
1971
1972                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1973                         PMD_INIT_LOG(INFO,
1974                                 "lsc won't enable because of no intr multiplex");
1975         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1976                 ret = i40e_aq_set_phy_int_mask(hw,
1977                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1978                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1979                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1980                 if (ret != I40E_SUCCESS)
1981                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1982
1983                 /* Call get_link_info aq commond to enable LSE */
1984                 i40e_dev_link_update(dev, 0);
1985         }
1986
1987         /* enable uio intr after callback register */
1988         rte_intr_enable(intr_handle);
1989
1990         i40e_filter_restore(pf);
1991
1992         return I40E_SUCCESS;
1993
1994 err_up:
1995         i40e_dev_switch_queues(pf, FALSE);
1996         i40e_dev_clear_queues(dev);
1997
1998         return ret;
1999 }
2000
2001 static void
2002 i40e_dev_stop(struct rte_eth_dev *dev)
2003 {
2004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2005         struct i40e_vsi *main_vsi = pf->main_vsi;
2006         struct i40e_mirror_rule *p_mirror;
2007         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2008         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2009         int i;
2010
2011         /* Disable all queues */
2012         i40e_dev_switch_queues(pf, FALSE);
2013
2014         /* un-map queues with interrupt registers */
2015         i40e_vsi_disable_queues_intr(main_vsi);
2016         i40e_vsi_queues_unbind_intr(main_vsi);
2017
2018         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2019                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2020                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2021         }
2022
2023         if (pf->fdir.fdir_vsi) {
2024                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2025                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2026         }
2027         /* Clear all queues and release memory */
2028         i40e_dev_clear_queues(dev);
2029
2030         /* Set link down */
2031         i40e_dev_set_link_down(dev);
2032
2033         /* Remove all mirror rules */
2034         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2035                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2036                 rte_free(p_mirror);
2037         }
2038         pf->nb_mirror_rule = 0;
2039
2040         if (!rte_intr_allow_others(intr_handle))
2041                 /* resume to the default handler */
2042                 rte_intr_callback_register(intr_handle,
2043                                            i40e_dev_interrupt_handler,
2044                                            (void *)dev);
2045
2046         /* Clean datapath event and queue/vec mapping */
2047         rte_intr_efd_disable(intr_handle);
2048         if (intr_handle->intr_vec) {
2049                 rte_free(intr_handle->intr_vec);
2050                 intr_handle->intr_vec = NULL;
2051         }
2052 }
2053
2054 static void
2055 i40e_dev_close(struct rte_eth_dev *dev)
2056 {
2057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2058         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2060         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2061         uint32_t reg;
2062         int i;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         i40e_dev_stop(dev);
2067         hw->adapter_stopped = 1;
2068         i40e_dev_free_queues(dev);
2069
2070         /* Disable interrupt */
2071         i40e_pf_disable_irq0(hw);
2072         rte_intr_disable(intr_handle);
2073
2074         /* shutdown and destroy the HMC */
2075         i40e_shutdown_lan_hmc(hw);
2076
2077         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2078                 i40e_vsi_release(pf->vmdq[i].vsi);
2079                 pf->vmdq[i].vsi = NULL;
2080         }
2081         rte_free(pf->vmdq);
2082         pf->vmdq = NULL;
2083
2084         /* release all the existing VSIs and VEBs */
2085         i40e_fdir_teardown(pf);
2086         i40e_vsi_release(pf->main_vsi);
2087
2088         /* shutdown the adminq */
2089         i40e_aq_queue_shutdown(hw, true);
2090         i40e_shutdown_adminq(hw);
2091
2092         i40e_res_pool_destroy(&pf->qp_pool);
2093         i40e_res_pool_destroy(&pf->msix_pool);
2094
2095         /* force a PF reset to clean anything leftover */
2096         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2097         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2098                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2099         I40E_WRITE_FLUSH(hw);
2100 }
2101
2102 static void
2103 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2104 {
2105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct i40e_vsi *vsi = pf->main_vsi;
2108         int status;
2109
2110         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2111                                                      true, NULL, true);
2112         if (status != I40E_SUCCESS)
2113                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2114
2115         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2116                                                         TRUE, NULL);
2117         if (status != I40E_SUCCESS)
2118                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2119
2120 }
2121
2122 static void
2123 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2124 {
2125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2126         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         struct i40e_vsi *vsi = pf->main_vsi;
2128         int status;
2129
2130         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2131                                                      false, NULL, true);
2132         if (status != I40E_SUCCESS)
2133                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2134
2135         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2136                                                         false, NULL);
2137         if (status != I40E_SUCCESS)
2138                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2139 }
2140
2141 static void
2142 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2143 {
2144         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2145         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146         struct i40e_vsi *vsi = pf->main_vsi;
2147         int ret;
2148
2149         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2150         if (ret != I40E_SUCCESS)
2151                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2152 }
2153
2154 static void
2155 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2156 {
2157         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159         struct i40e_vsi *vsi = pf->main_vsi;
2160         int ret;
2161
2162         if (dev->data->promiscuous == 1)
2163                 return; /* must remain in all_multicast mode */
2164
2165         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2166                                 vsi->seid, FALSE, NULL);
2167         if (ret != I40E_SUCCESS)
2168                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2169 }
2170
2171 /*
2172  * Set device link up.
2173  */
2174 static int
2175 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2176 {
2177         /* re-apply link speed setting */
2178         return i40e_apply_link_speed(dev);
2179 }
2180
2181 /*
2182  * Set device link down.
2183  */
2184 static int
2185 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2186 {
2187         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2188         uint8_t abilities = 0;
2189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190
2191         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2192         return i40e_phy_conf_link(hw, abilities, speed);
2193 }
2194
2195 int
2196 i40e_dev_link_update(struct rte_eth_dev *dev,
2197                      int wait_to_complete)
2198 {
2199 #define CHECK_INTERVAL 100  /* 100ms */
2200 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         struct i40e_link_status link_status;
2203         struct rte_eth_link link, old;
2204         int status;
2205         unsigned rep_cnt = MAX_REPEAT_TIME;
2206         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2207
2208         memset(&link, 0, sizeof(link));
2209         memset(&old, 0, sizeof(old));
2210         memset(&link_status, 0, sizeof(link_status));
2211         rte_i40e_dev_atomic_read_link_status(dev, &old);
2212
2213         do {
2214                 /* Get link status information from hardware */
2215                 status = i40e_aq_get_link_info(hw, enable_lse,
2216                                                 &link_status, NULL);
2217                 if (status != I40E_SUCCESS) {
2218                         link.link_speed = ETH_SPEED_NUM_100M;
2219                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2220                         PMD_DRV_LOG(ERR, "Failed to get link info");
2221                         goto out;
2222                 }
2223
2224                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2225                 if (!wait_to_complete || link.link_status)
2226                         break;
2227
2228                 rte_delay_ms(CHECK_INTERVAL);
2229         } while (--rep_cnt);
2230
2231         if (!link.link_status)
2232                 goto out;
2233
2234         /* i40e uses full duplex only */
2235         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2236
2237         /* Parse the link status */
2238         switch (link_status.link_speed) {
2239         case I40E_LINK_SPEED_100MB:
2240                 link.link_speed = ETH_SPEED_NUM_100M;
2241                 break;
2242         case I40E_LINK_SPEED_1GB:
2243                 link.link_speed = ETH_SPEED_NUM_1G;
2244                 break;
2245         case I40E_LINK_SPEED_10GB:
2246                 link.link_speed = ETH_SPEED_NUM_10G;
2247                 break;
2248         case I40E_LINK_SPEED_20GB:
2249                 link.link_speed = ETH_SPEED_NUM_20G;
2250                 break;
2251         case I40E_LINK_SPEED_25GB:
2252                 link.link_speed = ETH_SPEED_NUM_25G;
2253                 break;
2254         case I40E_LINK_SPEED_40GB:
2255                 link.link_speed = ETH_SPEED_NUM_40G;
2256                 break;
2257         default:
2258                 link.link_speed = ETH_SPEED_NUM_100M;
2259                 break;
2260         }
2261
2262         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2263                         ETH_LINK_SPEED_FIXED);
2264
2265 out:
2266         rte_i40e_dev_atomic_write_link_status(dev, &link);
2267         if (link.link_status == old.link_status)
2268                 return -1;
2269
2270         return 0;
2271 }
2272
2273 /* Get all the statistics of a VSI */
2274 void
2275 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2276 {
2277         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2278         struct i40e_eth_stats *nes = &vsi->eth_stats;
2279         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2280         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2281
2282         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2283                             vsi->offset_loaded, &oes->rx_bytes,
2284                             &nes->rx_bytes);
2285         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2286                             vsi->offset_loaded, &oes->rx_unicast,
2287                             &nes->rx_unicast);
2288         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2289                             vsi->offset_loaded, &oes->rx_multicast,
2290                             &nes->rx_multicast);
2291         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2292                             vsi->offset_loaded, &oes->rx_broadcast,
2293                             &nes->rx_broadcast);
2294         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2295                             &oes->rx_discards, &nes->rx_discards);
2296         /* GLV_REPC not supported */
2297         /* GLV_RMPC not supported */
2298         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2299                             &oes->rx_unknown_protocol,
2300                             &nes->rx_unknown_protocol);
2301         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2302                             vsi->offset_loaded, &oes->tx_bytes,
2303                             &nes->tx_bytes);
2304         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2305                             vsi->offset_loaded, &oes->tx_unicast,
2306                             &nes->tx_unicast);
2307         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2308                             vsi->offset_loaded, &oes->tx_multicast,
2309                             &nes->tx_multicast);
2310         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2311                             vsi->offset_loaded,  &oes->tx_broadcast,
2312                             &nes->tx_broadcast);
2313         /* GLV_TDPC not supported */
2314         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2315                             &oes->tx_errors, &nes->tx_errors);
2316         vsi->offset_loaded = true;
2317
2318         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2319                     vsi->vsi_id);
2320         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2321         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2322         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2323         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2324         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2325         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2326                     nes->rx_unknown_protocol);
2327         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2328         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2329         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2330         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2331         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2332         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2333         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2334                     vsi->vsi_id);
2335 }
2336
2337 static void
2338 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2339 {
2340         unsigned int i;
2341         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2342         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2343
2344         /* Get statistics of struct i40e_eth_stats */
2345         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2346                             I40E_GLPRT_GORCL(hw->port),
2347                             pf->offset_loaded, &os->eth.rx_bytes,
2348                             &ns->eth.rx_bytes);
2349         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2350                             I40E_GLPRT_UPRCL(hw->port),
2351                             pf->offset_loaded, &os->eth.rx_unicast,
2352                             &ns->eth.rx_unicast);
2353         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2354                             I40E_GLPRT_MPRCL(hw->port),
2355                             pf->offset_loaded, &os->eth.rx_multicast,
2356                             &ns->eth.rx_multicast);
2357         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2358                             I40E_GLPRT_BPRCL(hw->port),
2359                             pf->offset_loaded, &os->eth.rx_broadcast,
2360                             &ns->eth.rx_broadcast);
2361         /* Workaround: CRC size should not be included in byte statistics,
2362          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2363          */
2364         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2365                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2366
2367         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2368                             pf->offset_loaded, &os->eth.rx_discards,
2369                             &ns->eth.rx_discards);
2370         /* GLPRT_REPC not supported */
2371         /* GLPRT_RMPC not supported */
2372         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2373                             pf->offset_loaded,
2374                             &os->eth.rx_unknown_protocol,
2375                             &ns->eth.rx_unknown_protocol);
2376         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2377                             I40E_GLPRT_GOTCL(hw->port),
2378                             pf->offset_loaded, &os->eth.tx_bytes,
2379                             &ns->eth.tx_bytes);
2380         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2381                             I40E_GLPRT_UPTCL(hw->port),
2382                             pf->offset_loaded, &os->eth.tx_unicast,
2383                             &ns->eth.tx_unicast);
2384         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2385                             I40E_GLPRT_MPTCL(hw->port),
2386                             pf->offset_loaded, &os->eth.tx_multicast,
2387                             &ns->eth.tx_multicast);
2388         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2389                             I40E_GLPRT_BPTCL(hw->port),
2390                             pf->offset_loaded, &os->eth.tx_broadcast,
2391                             &ns->eth.tx_broadcast);
2392         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2393                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2394         /* GLPRT_TEPC not supported */
2395
2396         /* additional port specific stats */
2397         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2398                             pf->offset_loaded, &os->tx_dropped_link_down,
2399                             &ns->tx_dropped_link_down);
2400         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2401                             pf->offset_loaded, &os->crc_errors,
2402                             &ns->crc_errors);
2403         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2404                             pf->offset_loaded, &os->illegal_bytes,
2405                             &ns->illegal_bytes);
2406         /* GLPRT_ERRBC not supported */
2407         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2408                             pf->offset_loaded, &os->mac_local_faults,
2409                             &ns->mac_local_faults);
2410         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2411                             pf->offset_loaded, &os->mac_remote_faults,
2412                             &ns->mac_remote_faults);
2413         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2414                             pf->offset_loaded, &os->rx_length_errors,
2415                             &ns->rx_length_errors);
2416         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2417                             pf->offset_loaded, &os->link_xon_rx,
2418                             &ns->link_xon_rx);
2419         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2420                             pf->offset_loaded, &os->link_xoff_rx,
2421                             &ns->link_xoff_rx);
2422         for (i = 0; i < 8; i++) {
2423                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2424                                     pf->offset_loaded,
2425                                     &os->priority_xon_rx[i],
2426                                     &ns->priority_xon_rx[i]);
2427                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2428                                     pf->offset_loaded,
2429                                     &os->priority_xoff_rx[i],
2430                                     &ns->priority_xoff_rx[i]);
2431         }
2432         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2433                             pf->offset_loaded, &os->link_xon_tx,
2434                             &ns->link_xon_tx);
2435         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2436                             pf->offset_loaded, &os->link_xoff_tx,
2437                             &ns->link_xoff_tx);
2438         for (i = 0; i < 8; i++) {
2439                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2440                                     pf->offset_loaded,
2441                                     &os->priority_xon_tx[i],
2442                                     &ns->priority_xon_tx[i]);
2443                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2444                                     pf->offset_loaded,
2445                                     &os->priority_xoff_tx[i],
2446                                     &ns->priority_xoff_tx[i]);
2447                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2448                                     pf->offset_loaded,
2449                                     &os->priority_xon_2_xoff[i],
2450                                     &ns->priority_xon_2_xoff[i]);
2451         }
2452         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2453                             I40E_GLPRT_PRC64L(hw->port),
2454                             pf->offset_loaded, &os->rx_size_64,
2455                             &ns->rx_size_64);
2456         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2457                             I40E_GLPRT_PRC127L(hw->port),
2458                             pf->offset_loaded, &os->rx_size_127,
2459                             &ns->rx_size_127);
2460         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2461                             I40E_GLPRT_PRC255L(hw->port),
2462                             pf->offset_loaded, &os->rx_size_255,
2463                             &ns->rx_size_255);
2464         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2465                             I40E_GLPRT_PRC511L(hw->port),
2466                             pf->offset_loaded, &os->rx_size_511,
2467                             &ns->rx_size_511);
2468         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2469                             I40E_GLPRT_PRC1023L(hw->port),
2470                             pf->offset_loaded, &os->rx_size_1023,
2471                             &ns->rx_size_1023);
2472         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2473                             I40E_GLPRT_PRC1522L(hw->port),
2474                             pf->offset_loaded, &os->rx_size_1522,
2475                             &ns->rx_size_1522);
2476         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2477                             I40E_GLPRT_PRC9522L(hw->port),
2478                             pf->offset_loaded, &os->rx_size_big,
2479                             &ns->rx_size_big);
2480         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2481                             pf->offset_loaded, &os->rx_undersize,
2482                             &ns->rx_undersize);
2483         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2484                             pf->offset_loaded, &os->rx_fragments,
2485                             &ns->rx_fragments);
2486         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2487                             pf->offset_loaded, &os->rx_oversize,
2488                             &ns->rx_oversize);
2489         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2490                             pf->offset_loaded, &os->rx_jabber,
2491                             &ns->rx_jabber);
2492         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2493                             I40E_GLPRT_PTC64L(hw->port),
2494                             pf->offset_loaded, &os->tx_size_64,
2495                             &ns->tx_size_64);
2496         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2497                             I40E_GLPRT_PTC127L(hw->port),
2498                             pf->offset_loaded, &os->tx_size_127,
2499                             &ns->tx_size_127);
2500         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2501                             I40E_GLPRT_PTC255L(hw->port),
2502                             pf->offset_loaded, &os->tx_size_255,
2503                             &ns->tx_size_255);
2504         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2505                             I40E_GLPRT_PTC511L(hw->port),
2506                             pf->offset_loaded, &os->tx_size_511,
2507                             &ns->tx_size_511);
2508         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2509                             I40E_GLPRT_PTC1023L(hw->port),
2510                             pf->offset_loaded, &os->tx_size_1023,
2511                             &ns->tx_size_1023);
2512         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2513                             I40E_GLPRT_PTC1522L(hw->port),
2514                             pf->offset_loaded, &os->tx_size_1522,
2515                             &ns->tx_size_1522);
2516         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2517                             I40E_GLPRT_PTC9522L(hw->port),
2518                             pf->offset_loaded, &os->tx_size_big,
2519                             &ns->tx_size_big);
2520         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2521                            pf->offset_loaded,
2522                            &os->fd_sb_match, &ns->fd_sb_match);
2523         /* GLPRT_MSPDC not supported */
2524         /* GLPRT_XEC not supported */
2525
2526         pf->offset_loaded = true;
2527
2528         if (pf->main_vsi)
2529                 i40e_update_vsi_stats(pf->main_vsi);
2530 }
2531
2532 /* Get all statistics of a port */
2533 static void
2534 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2535 {
2536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2539         unsigned i;
2540
2541         /* call read registers - updates values, now write them to struct */
2542         i40e_read_stats_registers(pf, hw);
2543
2544         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2545                         pf->main_vsi->eth_stats.rx_multicast +
2546                         pf->main_vsi->eth_stats.rx_broadcast -
2547                         pf->main_vsi->eth_stats.rx_discards;
2548         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2549                         pf->main_vsi->eth_stats.tx_multicast +
2550                         pf->main_vsi->eth_stats.tx_broadcast;
2551         stats->ibytes   = ns->eth.rx_bytes;
2552         stats->obytes   = ns->eth.tx_bytes;
2553         stats->oerrors  = ns->eth.tx_errors +
2554                         pf->main_vsi->eth_stats.tx_errors;
2555
2556         /* Rx Errors */
2557         stats->imissed  = ns->eth.rx_discards +
2558                         pf->main_vsi->eth_stats.rx_discards;
2559         stats->ierrors  = ns->crc_errors +
2560                         ns->rx_length_errors + ns->rx_undersize +
2561                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2562
2563         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2564         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2565         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2566         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2567         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2568         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2569         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2570                     ns->eth.rx_unknown_protocol);
2571         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2572         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2573         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2574         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2575         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2576         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2577
2578         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2579                     ns->tx_dropped_link_down);
2580         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2581         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2582                     ns->illegal_bytes);
2583         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2584         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2585                     ns->mac_local_faults);
2586         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2587                     ns->mac_remote_faults);
2588         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2589                     ns->rx_length_errors);
2590         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2591         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2592         for (i = 0; i < 8; i++) {
2593                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2594                                 i, ns->priority_xon_rx[i]);
2595                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2596                                 i, ns->priority_xoff_rx[i]);
2597         }
2598         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2599         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2600         for (i = 0; i < 8; i++) {
2601                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2602                                 i, ns->priority_xon_tx[i]);
2603                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2604                                 i, ns->priority_xoff_tx[i]);
2605                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2606                                 i, ns->priority_xon_2_xoff[i]);
2607         }
2608         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2609         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2610         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2611         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2612         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2613         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2614         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2615         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2616         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2617         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2618         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2619         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2620         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2621         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2622         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2623         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2624         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2625         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2626         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2627                         ns->mac_short_packet_dropped);
2628         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2629                     ns->checksum_error);
2630         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2631         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2632 }
2633
2634 /* Reset the statistics */
2635 static void
2636 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2637 {
2638         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640
2641         /* Mark PF and VSI stats to update the offset, aka "reset" */
2642         pf->offset_loaded = false;
2643         if (pf->main_vsi)
2644                 pf->main_vsi->offset_loaded = false;
2645
2646         /* read the stats, reading current register values into offset */
2647         i40e_read_stats_registers(pf, hw);
2648 }
2649
2650 static uint32_t
2651 i40e_xstats_calc_num(void)
2652 {
2653         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2654                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2655                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2656 }
2657
2658 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2659                                      struct rte_eth_xstat_name *xstats_names,
2660                                      __rte_unused unsigned limit)
2661 {
2662         unsigned count = 0;
2663         unsigned i, prio;
2664
2665         if (xstats_names == NULL)
2666                 return i40e_xstats_calc_num();
2667
2668         /* Note: limit checked in rte_eth_xstats_names() */
2669
2670         /* Get stats from i40e_eth_stats struct */
2671         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2672                 snprintf(xstats_names[count].name,
2673                          sizeof(xstats_names[count].name),
2674                          "%s", rte_i40e_stats_strings[i].name);
2675                 count++;
2676         }
2677
2678         /* Get individiual stats from i40e_hw_port struct */
2679         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2680                 snprintf(xstats_names[count].name,
2681                         sizeof(xstats_names[count].name),
2682                          "%s", rte_i40e_hw_port_strings[i].name);
2683                 count++;
2684         }
2685
2686         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2687                 for (prio = 0; prio < 8; prio++) {
2688                         snprintf(xstats_names[count].name,
2689                                  sizeof(xstats_names[count].name),
2690                                  "rx_priority%u_%s", prio,
2691                                  rte_i40e_rxq_prio_strings[i].name);
2692                         count++;
2693                 }
2694         }
2695
2696         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2697                 for (prio = 0; prio < 8; prio++) {
2698                         snprintf(xstats_names[count].name,
2699                                  sizeof(xstats_names[count].name),
2700                                  "tx_priority%u_%s", prio,
2701                                  rte_i40e_txq_prio_strings[i].name);
2702                         count++;
2703                 }
2704         }
2705         return count;
2706 }
2707
2708 static int
2709 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2710                     unsigned n)
2711 {
2712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714         unsigned i, count, prio;
2715         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2716
2717         count = i40e_xstats_calc_num();
2718         if (n < count)
2719                 return count;
2720
2721         i40e_read_stats_registers(pf, hw);
2722
2723         if (xstats == NULL)
2724                 return 0;
2725
2726         count = 0;
2727
2728         /* Get stats from i40e_eth_stats struct */
2729         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2730                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2731                         rte_i40e_stats_strings[i].offset);
2732                 xstats[count].id = count;
2733                 count++;
2734         }
2735
2736         /* Get individiual stats from i40e_hw_port struct */
2737         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2738                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2739                         rte_i40e_hw_port_strings[i].offset);
2740                 xstats[count].id = count;
2741                 count++;
2742         }
2743
2744         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2745                 for (prio = 0; prio < 8; prio++) {
2746                         xstats[count].value =
2747                                 *(uint64_t *)(((char *)hw_stats) +
2748                                 rte_i40e_rxq_prio_strings[i].offset +
2749                                 (sizeof(uint64_t) * prio));
2750                         xstats[count].id = count;
2751                         count++;
2752                 }
2753         }
2754
2755         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2756                 for (prio = 0; prio < 8; prio++) {
2757                         xstats[count].value =
2758                                 *(uint64_t *)(((char *)hw_stats) +
2759                                 rte_i40e_txq_prio_strings[i].offset +
2760                                 (sizeof(uint64_t) * prio));
2761                         xstats[count].id = count;
2762                         count++;
2763                 }
2764         }
2765
2766         return count;
2767 }
2768
2769 static int
2770 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2771                                  __rte_unused uint16_t queue_id,
2772                                  __rte_unused uint8_t stat_idx,
2773                                  __rte_unused uint8_t is_rx)
2774 {
2775         PMD_INIT_FUNC_TRACE();
2776
2777         return -ENOSYS;
2778 }
2779
2780 static int
2781 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2782 {
2783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         u32 full_ver;
2785         u8 ver, patch;
2786         u16 build;
2787         int ret;
2788
2789         full_ver = hw->nvm.oem_ver;
2790         ver = (u8)(full_ver >> 24);
2791         build = (u16)((full_ver >> 8) & 0xffff);
2792         patch = (u8)(full_ver & 0xff);
2793
2794         ret = snprintf(fw_version, fw_size,
2795                  "%d.%d%d 0x%08x %d.%d.%d",
2796                  ((hw->nvm.version >> 12) & 0xf),
2797                  ((hw->nvm.version >> 4) & 0xff),
2798                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2799                  ver, build, patch);
2800
2801         ret += 1; /* add the size of '\0' */
2802         if (fw_size < (u32)ret)
2803                 return ret;
2804         else
2805                 return 0;
2806 }
2807
2808 static void
2809 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2810 {
2811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         struct i40e_vsi *vsi = pf->main_vsi;
2814         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2815
2816         dev_info->pci_dev = pci_dev;
2817         dev_info->max_rx_queues = vsi->nb_qps;
2818         dev_info->max_tx_queues = vsi->nb_qps;
2819         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2820         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2821         dev_info->max_mac_addrs = vsi->max_macaddrs;
2822         dev_info->max_vfs = pci_dev->max_vfs;
2823         dev_info->rx_offload_capa =
2824                 DEV_RX_OFFLOAD_VLAN_STRIP |
2825                 DEV_RX_OFFLOAD_QINQ_STRIP |
2826                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2827                 DEV_RX_OFFLOAD_UDP_CKSUM |
2828                 DEV_RX_OFFLOAD_TCP_CKSUM;
2829         dev_info->tx_offload_capa =
2830                 DEV_TX_OFFLOAD_VLAN_INSERT |
2831                 DEV_TX_OFFLOAD_QINQ_INSERT |
2832                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2833                 DEV_TX_OFFLOAD_UDP_CKSUM |
2834                 DEV_TX_OFFLOAD_TCP_CKSUM |
2835                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2836                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2837                 DEV_TX_OFFLOAD_TCP_TSO |
2838                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2839                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2840                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2841                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2842         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2843                                                 sizeof(uint32_t);
2844         dev_info->reta_size = pf->hash_lut_size;
2845         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2846
2847         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2848                 .rx_thresh = {
2849                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2850                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2851                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2852                 },
2853                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2854                 .rx_drop_en = 0,
2855         };
2856
2857         dev_info->default_txconf = (struct rte_eth_txconf) {
2858                 .tx_thresh = {
2859                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2860                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2861                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2862                 },
2863                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2864                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2865                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2866                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2867         };
2868
2869         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2870                 .nb_max = I40E_MAX_RING_DESC,
2871                 .nb_min = I40E_MIN_RING_DESC,
2872                 .nb_align = I40E_ALIGN_RING_DESC,
2873         };
2874
2875         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2876                 .nb_max = I40E_MAX_RING_DESC,
2877                 .nb_min = I40E_MIN_RING_DESC,
2878                 .nb_align = I40E_ALIGN_RING_DESC,
2879                 .nb_seg_max = I40E_TX_MAX_SEG,
2880                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2881         };
2882
2883         if (pf->flags & I40E_FLAG_VMDQ) {
2884                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2885                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2886                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2887                                                 pf->max_nb_vmdq_vsi;
2888                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2889                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2890                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2891         }
2892
2893         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2894                 /* For XL710 */
2895                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2896         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2897                 /* For XXV710 */
2898                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2899         else
2900                 /* For X710 */
2901                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2902 }
2903
2904 static int
2905 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2906 {
2907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2908         struct i40e_vsi *vsi = pf->main_vsi;
2909         PMD_INIT_FUNC_TRACE();
2910
2911         if (on)
2912                 return i40e_vsi_add_vlan(vsi, vlan_id);
2913         else
2914                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2915 }
2916
2917 static int
2918 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2919                    enum rte_vlan_type vlan_type,
2920                    uint16_t tpid)
2921 {
2922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923         uint64_t reg_r = 0, reg_w = 0;
2924         uint16_t reg_id = 0;
2925         int ret = 0;
2926         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2927
2928         switch (vlan_type) {
2929         case ETH_VLAN_TYPE_OUTER:
2930                 if (qinq)
2931                         reg_id = 2;
2932                 else
2933                         reg_id = 3;
2934                 break;
2935         case ETH_VLAN_TYPE_INNER:
2936                 if (qinq)
2937                         reg_id = 3;
2938                 else {
2939                         ret = -EINVAL;
2940                         PMD_DRV_LOG(ERR,
2941                                 "Unsupported vlan type in single vlan.");
2942                         return ret;
2943                 }
2944                 break;
2945         default:
2946                 ret = -EINVAL;
2947                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2948                 return ret;
2949         }
2950         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2951                                           &reg_r, NULL);
2952         if (ret != I40E_SUCCESS) {
2953                 PMD_DRV_LOG(ERR,
2954                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2955                            reg_id);
2956                 ret = -EIO;
2957                 return ret;
2958         }
2959         PMD_DRV_LOG(DEBUG,
2960                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2961                 reg_id, reg_r);
2962
2963         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2964         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2965         if (reg_r == reg_w) {
2966                 ret = 0;
2967                 PMD_DRV_LOG(DEBUG, "No need to write");
2968                 return ret;
2969         }
2970
2971         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2972                                            reg_w, NULL);
2973         if (ret != I40E_SUCCESS) {
2974                 ret = -EIO;
2975                 PMD_DRV_LOG(ERR,
2976                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2977                         reg_id);
2978                 return ret;
2979         }
2980         PMD_DRV_LOG(DEBUG,
2981                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2982                 reg_w, reg_id);
2983
2984         return ret;
2985 }
2986
2987 static void
2988 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2989 {
2990         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2991         struct i40e_vsi *vsi = pf->main_vsi;
2992
2993         if (mask & ETH_VLAN_FILTER_MASK) {
2994                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2995                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2996                 else
2997                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2998         }
2999
3000         if (mask & ETH_VLAN_STRIP_MASK) {
3001                 /* Enable or disable VLAN stripping */
3002                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3003                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3004                 else
3005                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3006         }
3007
3008         if (mask & ETH_VLAN_EXTEND_MASK) {
3009                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3010                         i40e_vsi_config_double_vlan(vsi, TRUE);
3011                         /* Set global registers with default ether type value */
3012                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3013                                            ETHER_TYPE_VLAN);
3014                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3015                                            ETHER_TYPE_VLAN);
3016                 }
3017                 else
3018                         i40e_vsi_config_double_vlan(vsi, FALSE);
3019         }
3020 }
3021
3022 static void
3023 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3024                           __rte_unused uint16_t queue,
3025                           __rte_unused int on)
3026 {
3027         PMD_INIT_FUNC_TRACE();
3028 }
3029
3030 static int
3031 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3032 {
3033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3034         struct i40e_vsi *vsi = pf->main_vsi;
3035         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3036         struct i40e_vsi_vlan_pvid_info info;
3037
3038         memset(&info, 0, sizeof(info));
3039         info.on = on;
3040         if (info.on)
3041                 info.config.pvid = pvid;
3042         else {
3043                 info.config.reject.tagged =
3044                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3045                 info.config.reject.untagged =
3046                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3047         }
3048
3049         return i40e_vsi_vlan_pvid_set(vsi, &info);
3050 }
3051
3052 static int
3053 i40e_dev_led_on(struct rte_eth_dev *dev)
3054 {
3055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         uint32_t mode = i40e_led_get(hw);
3057
3058         if (mode == 0)
3059                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3060
3061         return 0;
3062 }
3063
3064 static int
3065 i40e_dev_led_off(struct rte_eth_dev *dev)
3066 {
3067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         uint32_t mode = i40e_led_get(hw);
3069
3070         if (mode != 0)
3071                 i40e_led_set(hw, 0, false);
3072
3073         return 0;
3074 }
3075
3076 static int
3077 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3078 {
3079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3081
3082         fc_conf->pause_time = pf->fc_conf.pause_time;
3083         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3084         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3085
3086          /* Return current mode according to actual setting*/
3087         switch (hw->fc.current_mode) {
3088         case I40E_FC_FULL:
3089                 fc_conf->mode = RTE_FC_FULL;
3090                 break;
3091         case I40E_FC_TX_PAUSE:
3092                 fc_conf->mode = RTE_FC_TX_PAUSE;
3093                 break;
3094         case I40E_FC_RX_PAUSE:
3095                 fc_conf->mode = RTE_FC_RX_PAUSE;
3096                 break;
3097         case I40E_FC_NONE:
3098         default:
3099                 fc_conf->mode = RTE_FC_NONE;
3100         };
3101
3102         return 0;
3103 }
3104
3105 static int
3106 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3107 {
3108         uint32_t mflcn_reg, fctrl_reg, reg;
3109         uint32_t max_high_water;
3110         uint8_t i, aq_failure;
3111         int err;
3112         struct i40e_hw *hw;
3113         struct i40e_pf *pf;
3114         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3115                 [RTE_FC_NONE] = I40E_FC_NONE,
3116                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3117                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3118                 [RTE_FC_FULL] = I40E_FC_FULL
3119         };
3120
3121         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3122
3123         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3124         if ((fc_conf->high_water > max_high_water) ||
3125                         (fc_conf->high_water < fc_conf->low_water)) {
3126                 PMD_INIT_LOG(ERR,
3127                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3128                         max_high_water);
3129                 return -EINVAL;
3130         }
3131
3132         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3133         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3134         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3135
3136         pf->fc_conf.pause_time = fc_conf->pause_time;
3137         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3138         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3139
3140         PMD_INIT_FUNC_TRACE();
3141
3142         /* All the link flow control related enable/disable register
3143          * configuration is handle by the F/W
3144          */
3145         err = i40e_set_fc(hw, &aq_failure, true);
3146         if (err < 0)
3147                 return -ENOSYS;
3148
3149         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3150                 /* Configure flow control refresh threshold,
3151                  * the value for stat_tx_pause_refresh_timer[8]
3152                  * is used for global pause operation.
3153                  */
3154
3155                 I40E_WRITE_REG(hw,
3156                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3157                                pf->fc_conf.pause_time);
3158
3159                 /* configure the timer value included in transmitted pause
3160                  * frame,
3161                  * the value for stat_tx_pause_quanta[8] is used for global
3162                  * pause operation
3163                  */
3164                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3165                                pf->fc_conf.pause_time);
3166
3167                 fctrl_reg = I40E_READ_REG(hw,
3168                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3169
3170                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3171                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3172                 else
3173                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3174
3175                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3176                                fctrl_reg);
3177         } else {
3178                 /* Configure pause time (2 TCs per register) */
3179                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3180                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3181                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3182
3183                 /* Configure flow control refresh threshold value */
3184                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3185                                pf->fc_conf.pause_time / 2);
3186
3187                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3188
3189                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3190                  *depending on configuration
3191                  */
3192                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3193                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3194                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3195                 } else {
3196                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3197                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3198                 }
3199
3200                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3201         }
3202
3203         /* config the water marker both based on the packets and bytes */
3204         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3205                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3206                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3207         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3208                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3209                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3210         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3211                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3212                        << I40E_KILOSHIFT);
3213         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3214                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3215                        << I40E_KILOSHIFT);
3216
3217         I40E_WRITE_FLUSH(hw);
3218
3219         return 0;
3220 }
3221
3222 static int
3223 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3224                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3225 {
3226         PMD_INIT_FUNC_TRACE();
3227
3228         return -ENOSYS;
3229 }
3230
3231 /* Add a MAC address, and update filters */
3232 static void
3233 i40e_macaddr_add(struct rte_eth_dev *dev,
3234                  struct ether_addr *mac_addr,
3235                  __rte_unused uint32_t index,
3236                  uint32_t pool)
3237 {
3238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3239         struct i40e_mac_filter_info mac_filter;
3240         struct i40e_vsi *vsi;
3241         int ret;
3242
3243         /* If VMDQ not enabled or configured, return */
3244         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3245                           !pf->nb_cfg_vmdq_vsi)) {
3246                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3247                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3248                         pool);
3249                 return;
3250         }
3251
3252         if (pool > pf->nb_cfg_vmdq_vsi) {
3253                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3254                                 pool, pf->nb_cfg_vmdq_vsi);
3255                 return;
3256         }
3257
3258         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3259         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3260                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3261         else
3262                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3263
3264         if (pool == 0)
3265                 vsi = pf->main_vsi;
3266         else
3267                 vsi = pf->vmdq[pool - 1].vsi;
3268
3269         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3270         if (ret != I40E_SUCCESS) {
3271                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3272                 return;
3273         }
3274 }
3275
3276 /* Remove a MAC address, and update filters */
3277 static void
3278 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3279 {
3280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3281         struct i40e_vsi *vsi;
3282         struct rte_eth_dev_data *data = dev->data;
3283         struct ether_addr *macaddr;
3284         int ret;
3285         uint32_t i;
3286         uint64_t pool_sel;
3287
3288         macaddr = &(data->mac_addrs[index]);
3289
3290         pool_sel = dev->data->mac_pool_sel[index];
3291
3292         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3293                 if (pool_sel & (1ULL << i)) {
3294                         if (i == 0)
3295                                 vsi = pf->main_vsi;
3296                         else {
3297                                 /* No VMDQ pool enabled or configured */
3298                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3299                                         (i > pf->nb_cfg_vmdq_vsi)) {
3300                                         PMD_DRV_LOG(ERR,
3301                                                 "No VMDQ pool enabled/configured");
3302                                         return;
3303                                 }
3304                                 vsi = pf->vmdq[i - 1].vsi;
3305                         }
3306                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3307
3308                         if (ret) {
3309                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3310                                 return;
3311                         }
3312                 }
3313         }
3314 }
3315
3316 /* Set perfect match or hash match of MAC and VLAN for a VF */
3317 static int
3318 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3319                  struct rte_eth_mac_filter *filter,
3320                  bool add)
3321 {
3322         struct i40e_hw *hw;
3323         struct i40e_mac_filter_info mac_filter;
3324         struct ether_addr old_mac;
3325         struct ether_addr *new_mac;
3326         struct i40e_pf_vf *vf = NULL;
3327         uint16_t vf_id;
3328         int ret;
3329
3330         if (pf == NULL) {
3331                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3332                 return -EINVAL;
3333         }
3334         hw = I40E_PF_TO_HW(pf);
3335
3336         if (filter == NULL) {
3337                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3338                 return -EINVAL;
3339         }
3340
3341         new_mac = &filter->mac_addr;
3342
3343         if (is_zero_ether_addr(new_mac)) {
3344                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3345                 return -EINVAL;
3346         }
3347
3348         vf_id = filter->dst_id;
3349
3350         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3351                 PMD_DRV_LOG(ERR, "Invalid argument.");
3352                 return -EINVAL;
3353         }
3354         vf = &pf->vfs[vf_id];
3355
3356         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3357                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3358                 return -EINVAL;
3359         }
3360
3361         if (add) {
3362                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3363                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3364                                 ETHER_ADDR_LEN);
3365                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3366                                  ETHER_ADDR_LEN);
3367
3368                 mac_filter.filter_type = filter->filter_type;
3369                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3370                 if (ret != I40E_SUCCESS) {
3371                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3372                         return -1;
3373                 }
3374                 ether_addr_copy(new_mac, &pf->dev_addr);
3375         } else {
3376                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3377                                 ETHER_ADDR_LEN);
3378                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3379                 if (ret != I40E_SUCCESS) {
3380                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3381                         return -1;
3382                 }
3383
3384                 /* Clear device address as it has been removed */
3385                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3386                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3387         }
3388
3389         return 0;
3390 }
3391
3392 /* MAC filter handle */
3393 static int
3394 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3395                 void *arg)
3396 {
3397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3398         struct rte_eth_mac_filter *filter;
3399         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3400         int ret = I40E_NOT_SUPPORTED;
3401
3402         filter = (struct rte_eth_mac_filter *)(arg);
3403
3404         switch (filter_op) {
3405         case RTE_ETH_FILTER_NOP:
3406                 ret = I40E_SUCCESS;
3407                 break;
3408         case RTE_ETH_FILTER_ADD:
3409                 i40e_pf_disable_irq0(hw);
3410                 if (filter->is_vf)
3411                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3412                 i40e_pf_enable_irq0(hw);
3413                 break;
3414         case RTE_ETH_FILTER_DELETE:
3415                 i40e_pf_disable_irq0(hw);
3416                 if (filter->is_vf)
3417                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3418                 i40e_pf_enable_irq0(hw);
3419                 break;
3420         default:
3421                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3422                 ret = I40E_ERR_PARAM;
3423                 break;
3424         }
3425
3426         return ret;
3427 }
3428
3429 static int
3430 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3431 {
3432         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3433         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3434         int ret;
3435
3436         if (!lut)
3437                 return -EINVAL;
3438
3439         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3440                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3441                                           lut, lut_size);
3442                 if (ret) {
3443                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3444                         return ret;
3445                 }
3446         } else {
3447                 uint32_t *lut_dw = (uint32_t *)lut;
3448                 uint16_t i, lut_size_dw = lut_size / 4;
3449
3450                 for (i = 0; i < lut_size_dw; i++)
3451                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3452         }
3453
3454         return 0;
3455 }
3456
3457 static int
3458 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3459 {
3460         struct i40e_pf *pf;
3461         struct i40e_hw *hw;
3462         int ret;
3463
3464         if (!vsi || !lut)
3465                 return -EINVAL;
3466
3467         pf = I40E_VSI_TO_PF(vsi);
3468         hw = I40E_VSI_TO_HW(vsi);
3469
3470         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3471                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3472                                           lut, lut_size);
3473                 if (ret) {
3474                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3475                         return ret;
3476                 }
3477         } else {
3478                 uint32_t *lut_dw = (uint32_t *)lut;
3479                 uint16_t i, lut_size_dw = lut_size / 4;
3480
3481                 for (i = 0; i < lut_size_dw; i++)
3482                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3483                 I40E_WRITE_FLUSH(hw);
3484         }
3485
3486         return 0;
3487 }
3488
3489 static int
3490 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3491                          struct rte_eth_rss_reta_entry64 *reta_conf,
3492                          uint16_t reta_size)
3493 {
3494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3495         uint16_t i, lut_size = pf->hash_lut_size;
3496         uint16_t idx, shift;
3497         uint8_t *lut;
3498         int ret;
3499
3500         if (reta_size != lut_size ||
3501                 reta_size > ETH_RSS_RETA_SIZE_512) {
3502                 PMD_DRV_LOG(ERR,
3503                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3504                         reta_size, lut_size);
3505                 return -EINVAL;
3506         }
3507
3508         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3509         if (!lut) {
3510                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3511                 return -ENOMEM;
3512         }
3513         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3514         if (ret)
3515                 goto out;
3516         for (i = 0; i < reta_size; i++) {
3517                 idx = i / RTE_RETA_GROUP_SIZE;
3518                 shift = i % RTE_RETA_GROUP_SIZE;
3519                 if (reta_conf[idx].mask & (1ULL << shift))
3520                         lut[i] = reta_conf[idx].reta[shift];
3521         }
3522         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3523
3524 out:
3525         rte_free(lut);
3526
3527         return ret;
3528 }
3529
3530 static int
3531 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3532                         struct rte_eth_rss_reta_entry64 *reta_conf,
3533                         uint16_t reta_size)
3534 {
3535         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3536         uint16_t i, lut_size = pf->hash_lut_size;
3537         uint16_t idx, shift;
3538         uint8_t *lut;
3539         int ret;
3540
3541         if (reta_size != lut_size ||
3542                 reta_size > ETH_RSS_RETA_SIZE_512) {
3543                 PMD_DRV_LOG(ERR,
3544                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3545                         reta_size, lut_size);
3546                 return -EINVAL;
3547         }
3548
3549         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3550         if (!lut) {
3551                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3552                 return -ENOMEM;
3553         }
3554
3555         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3556         if (ret)
3557                 goto out;
3558         for (i = 0; i < reta_size; i++) {
3559                 idx = i / RTE_RETA_GROUP_SIZE;
3560                 shift = i % RTE_RETA_GROUP_SIZE;
3561                 if (reta_conf[idx].mask & (1ULL << shift))
3562                         reta_conf[idx].reta[shift] = lut[i];
3563         }
3564
3565 out:
3566         rte_free(lut);
3567
3568         return ret;
3569 }
3570
3571 /**
3572  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3573  * @hw:   pointer to the HW structure
3574  * @mem:  pointer to mem struct to fill out
3575  * @size: size of memory requested
3576  * @alignment: what to align the allocation to
3577  **/
3578 enum i40e_status_code
3579 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3580                         struct i40e_dma_mem *mem,
3581                         u64 size,
3582                         u32 alignment)
3583 {
3584         const struct rte_memzone *mz = NULL;
3585         char z_name[RTE_MEMZONE_NAMESIZE];
3586
3587         if (!mem)
3588                 return I40E_ERR_PARAM;
3589
3590         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3591         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3592                                          alignment, RTE_PGSIZE_2M);
3593         if (!mz)
3594                 return I40E_ERR_NO_MEMORY;
3595
3596         mem->size = size;
3597         mem->va = mz->addr;
3598         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3599         mem->zone = (const void *)mz;
3600         PMD_DRV_LOG(DEBUG,
3601                 "memzone %s allocated with physical address: %"PRIu64,
3602                 mz->name, mem->pa);
3603
3604         return I40E_SUCCESS;
3605 }
3606
3607 /**
3608  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3609  * @hw:   pointer to the HW structure
3610  * @mem:  ptr to mem struct to free
3611  **/
3612 enum i40e_status_code
3613 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3614                     struct i40e_dma_mem *mem)
3615 {
3616         if (!mem)
3617                 return I40E_ERR_PARAM;
3618
3619         PMD_DRV_LOG(DEBUG,
3620                 "memzone %s to be freed with physical address: %"PRIu64,
3621                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3622         rte_memzone_free((const struct rte_memzone *)mem->zone);
3623         mem->zone = NULL;
3624         mem->va = NULL;
3625         mem->pa = (u64)0;
3626
3627         return I40E_SUCCESS;
3628 }
3629
3630 /**
3631  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3632  * @hw:   pointer to the HW structure
3633  * @mem:  pointer to mem struct to fill out
3634  * @size: size of memory requested
3635  **/
3636 enum i40e_status_code
3637 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3638                          struct i40e_virt_mem *mem,
3639                          u32 size)
3640 {
3641         if (!mem)
3642                 return I40E_ERR_PARAM;
3643
3644         mem->size = size;
3645         mem->va = rte_zmalloc("i40e", size, 0);
3646
3647         if (mem->va)
3648                 return I40E_SUCCESS;
3649         else
3650                 return I40E_ERR_NO_MEMORY;
3651 }
3652
3653 /**
3654  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3655  * @hw:   pointer to the HW structure
3656  * @mem:  pointer to mem struct to free
3657  **/
3658 enum i40e_status_code
3659 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3660                      struct i40e_virt_mem *mem)
3661 {
3662         if (!mem)
3663                 return I40E_ERR_PARAM;
3664
3665         rte_free(mem->va);
3666         mem->va = NULL;
3667
3668         return I40E_SUCCESS;
3669 }
3670
3671 void
3672 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3673 {
3674         rte_spinlock_init(&sp->spinlock);
3675 }
3676
3677 void
3678 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3679 {
3680         rte_spinlock_lock(&sp->spinlock);
3681 }
3682
3683 void
3684 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3685 {
3686         rte_spinlock_unlock(&sp->spinlock);
3687 }
3688
3689 void
3690 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3691 {
3692         return;
3693 }
3694
3695 /**
3696  * Get the hardware capabilities, which will be parsed
3697  * and saved into struct i40e_hw.
3698  */
3699 static int
3700 i40e_get_cap(struct i40e_hw *hw)
3701 {
3702         struct i40e_aqc_list_capabilities_element_resp *buf;
3703         uint16_t len, size = 0;
3704         int ret;
3705
3706         /* Calculate a huge enough buff for saving response data temporarily */
3707         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3708                                                 I40E_MAX_CAP_ELE_NUM;
3709         buf = rte_zmalloc("i40e", len, 0);
3710         if (!buf) {
3711                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3712                 return I40E_ERR_NO_MEMORY;
3713         }
3714
3715         /* Get, parse the capabilities and save it to hw */
3716         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3717                         i40e_aqc_opc_list_func_capabilities, NULL);
3718         if (ret != I40E_SUCCESS)
3719                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3720
3721         /* Free the temporary buffer after being used */
3722         rte_free(buf);
3723
3724         return ret;
3725 }
3726
3727 static int
3728 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3729 {
3730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3732         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3733         uint16_t qp_count = 0, vsi_count = 0;
3734
3735         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3736                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3737                 return -EINVAL;
3738         }
3739         /* Add the parameter init for LFC */
3740         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3741         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3742         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3743
3744         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3745         pf->max_num_vsi = hw->func_caps.num_vsis;
3746         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3747         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3748         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3749
3750         /* FDir queue/VSI allocation */
3751         pf->fdir_qp_offset = 0;
3752         if (hw->func_caps.fd) {
3753                 pf->flags |= I40E_FLAG_FDIR;
3754                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3755         } else {
3756                 pf->fdir_nb_qps = 0;
3757         }
3758         qp_count += pf->fdir_nb_qps;
3759         vsi_count += 1;
3760
3761         /* LAN queue/VSI allocation */
3762         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3763         if (!hw->func_caps.rss) {
3764                 pf->lan_nb_qps = 1;
3765         } else {
3766                 pf->flags |= I40E_FLAG_RSS;
3767                 if (hw->mac.type == I40E_MAC_X722)
3768                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3769                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3770         }
3771         qp_count += pf->lan_nb_qps;
3772         vsi_count += 1;
3773
3774         /* VF queue/VSI allocation */
3775         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3776         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3777                 pf->flags |= I40E_FLAG_SRIOV;
3778                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3779                 pf->vf_num = pci_dev->max_vfs;
3780                 PMD_DRV_LOG(DEBUG,
3781                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3782                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3783         } else {
3784                 pf->vf_nb_qps = 0;
3785                 pf->vf_num = 0;
3786         }
3787         qp_count += pf->vf_nb_qps * pf->vf_num;
3788         vsi_count += pf->vf_num;
3789
3790         /* VMDq queue/VSI allocation */
3791         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3792         pf->vmdq_nb_qps = 0;
3793         pf->max_nb_vmdq_vsi = 0;
3794         if (hw->func_caps.vmdq) {
3795                 if (qp_count < hw->func_caps.num_tx_qp &&
3796                         vsi_count < hw->func_caps.num_vsis) {
3797                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3798                                 qp_count) / pf->vmdq_nb_qp_max;
3799
3800                         /* Limit the maximum number of VMDq vsi to the maximum
3801                          * ethdev can support
3802                          */
3803                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3804                                 hw->func_caps.num_vsis - vsi_count);
3805                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3806                                 ETH_64_POOLS);
3807                         if (pf->max_nb_vmdq_vsi) {
3808                                 pf->flags |= I40E_FLAG_VMDQ;
3809                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3810                                 PMD_DRV_LOG(DEBUG,
3811                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3812                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3813                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3814                         } else {
3815                                 PMD_DRV_LOG(INFO,
3816                                         "No enough queues left for VMDq");
3817                         }
3818                 } else {
3819                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3820                 }
3821         }
3822         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3823         vsi_count += pf->max_nb_vmdq_vsi;
3824
3825         if (hw->func_caps.dcb)
3826                 pf->flags |= I40E_FLAG_DCB;
3827
3828         if (qp_count > hw->func_caps.num_tx_qp) {
3829                 PMD_DRV_LOG(ERR,
3830                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3831                         qp_count, hw->func_caps.num_tx_qp);
3832                 return -EINVAL;
3833         }
3834         if (vsi_count > hw->func_caps.num_vsis) {
3835                 PMD_DRV_LOG(ERR,
3836                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3837                         vsi_count, hw->func_caps.num_vsis);
3838                 return -EINVAL;
3839         }
3840
3841         return 0;
3842 }
3843
3844 static int
3845 i40e_pf_get_switch_config(struct i40e_pf *pf)
3846 {
3847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3848         struct i40e_aqc_get_switch_config_resp *switch_config;
3849         struct i40e_aqc_switch_config_element_resp *element;
3850         uint16_t start_seid = 0, num_reported;
3851         int ret;
3852
3853         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3854                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3855         if (!switch_config) {
3856                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3857                 return -ENOMEM;
3858         }
3859
3860         /* Get the switch configurations */
3861         ret = i40e_aq_get_switch_config(hw, switch_config,
3862                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3863         if (ret != I40E_SUCCESS) {
3864                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3865                 goto fail;
3866         }
3867         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3868         if (num_reported != 1) { /* The number should be 1 */
3869                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3870                 goto fail;
3871         }
3872
3873         /* Parse the switch configuration elements */
3874         element = &(switch_config->element[0]);
3875         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3876                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3877                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3878         } else
3879                 PMD_DRV_LOG(INFO, "Unknown element type");
3880
3881 fail:
3882         rte_free(switch_config);
3883
3884         return ret;
3885 }
3886
3887 static int
3888 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3889                         uint32_t num)
3890 {
3891         struct pool_entry *entry;
3892
3893         if (pool == NULL || num == 0)
3894                 return -EINVAL;
3895
3896         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3897         if (entry == NULL) {
3898                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3899                 return -ENOMEM;
3900         }
3901
3902         /* queue heap initialize */
3903         pool->num_free = num;
3904         pool->num_alloc = 0;
3905         pool->base = base;
3906         LIST_INIT(&pool->alloc_list);
3907         LIST_INIT(&pool->free_list);
3908
3909         /* Initialize element  */
3910         entry->base = 0;
3911         entry->len = num;
3912
3913         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3914         return 0;
3915 }
3916
3917 static void
3918 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3919 {
3920         struct pool_entry *entry, *next_entry;
3921
3922         if (pool == NULL)
3923                 return;
3924
3925         for (entry = LIST_FIRST(&pool->alloc_list);
3926                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3927                         entry = next_entry) {
3928                 LIST_REMOVE(entry, next);
3929                 rte_free(entry);
3930         }
3931
3932         for (entry = LIST_FIRST(&pool->free_list);
3933                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3934                         entry = next_entry) {
3935                 LIST_REMOVE(entry, next);
3936                 rte_free(entry);
3937         }
3938
3939         pool->num_free = 0;
3940         pool->num_alloc = 0;
3941         pool->base = 0;
3942         LIST_INIT(&pool->alloc_list);
3943         LIST_INIT(&pool->free_list);
3944 }
3945
3946 static int
3947 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3948                        uint32_t base)
3949 {
3950         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3951         uint32_t pool_offset;
3952         int insert;
3953
3954         if (pool == NULL) {
3955                 PMD_DRV_LOG(ERR, "Invalid parameter");
3956                 return -EINVAL;
3957         }
3958
3959         pool_offset = base - pool->base;
3960         /* Lookup in alloc list */
3961         LIST_FOREACH(entry, &pool->alloc_list, next) {
3962                 if (entry->base == pool_offset) {
3963                         valid_entry = entry;
3964                         LIST_REMOVE(entry, next);
3965                         break;
3966                 }
3967         }
3968
3969         /* Not find, return */
3970         if (valid_entry == NULL) {
3971                 PMD_DRV_LOG(ERR, "Failed to find entry");
3972                 return -EINVAL;
3973         }
3974
3975         /**
3976          * Found it, move it to free list  and try to merge.
3977          * In order to make merge easier, always sort it by qbase.
3978          * Find adjacent prev and last entries.
3979          */
3980         prev = next = NULL;
3981         LIST_FOREACH(entry, &pool->free_list, next) {
3982                 if (entry->base > valid_entry->base) {
3983                         next = entry;
3984                         break;
3985                 }
3986                 prev = entry;
3987         }
3988
3989         insert = 0;
3990         /* Try to merge with next one*/
3991         if (next != NULL) {
3992                 /* Merge with next one */
3993                 if (valid_entry->base + valid_entry->len == next->base) {
3994                         next->base = valid_entry->base;
3995                         next->len += valid_entry->len;
3996                         rte_free(valid_entry);
3997                         valid_entry = next;
3998                         insert = 1;
3999                 }
4000         }
4001
4002         if (prev != NULL) {
4003                 /* Merge with previous one */
4004                 if (prev->base + prev->len == valid_entry->base) {
4005                         prev->len += valid_entry->len;
4006                         /* If it merge with next one, remove next node */
4007                         if (insert == 1) {
4008                                 LIST_REMOVE(valid_entry, next);
4009                                 rte_free(valid_entry);
4010                         } else {
4011                                 rte_free(valid_entry);
4012                                 insert = 1;
4013                         }
4014                 }
4015         }
4016
4017         /* Not find any entry to merge, insert */
4018         if (insert == 0) {
4019                 if (prev != NULL)
4020                         LIST_INSERT_AFTER(prev, valid_entry, next);
4021                 else if (next != NULL)
4022                         LIST_INSERT_BEFORE(next, valid_entry, next);
4023                 else /* It's empty list, insert to head */
4024                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4025         }
4026
4027         pool->num_free += valid_entry->len;
4028         pool->num_alloc -= valid_entry->len;
4029
4030         return 0;
4031 }
4032
4033 static int
4034 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4035                        uint16_t num)
4036 {
4037         struct pool_entry *entry, *valid_entry;
4038
4039         if (pool == NULL || num == 0) {
4040                 PMD_DRV_LOG(ERR, "Invalid parameter");
4041                 return -EINVAL;
4042         }
4043
4044         if (pool->num_free < num) {
4045                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4046                             num, pool->num_free);
4047                 return -ENOMEM;
4048         }
4049
4050         valid_entry = NULL;
4051         /* Lookup  in free list and find most fit one */
4052         LIST_FOREACH(entry, &pool->free_list, next) {
4053                 if (entry->len >= num) {
4054                         /* Find best one */
4055                         if (entry->len == num) {
4056                                 valid_entry = entry;
4057                                 break;
4058                         }
4059                         if (valid_entry == NULL || valid_entry->len > entry->len)
4060                                 valid_entry = entry;
4061                 }
4062         }
4063
4064         /* Not find one to satisfy the request, return */
4065         if (valid_entry == NULL) {
4066                 PMD_DRV_LOG(ERR, "No valid entry found");
4067                 return -ENOMEM;
4068         }
4069         /**
4070          * The entry have equal queue number as requested,
4071          * remove it from alloc_list.
4072          */
4073         if (valid_entry->len == num) {
4074                 LIST_REMOVE(valid_entry, next);
4075         } else {
4076                 /**
4077                  * The entry have more numbers than requested,
4078                  * create a new entry for alloc_list and minus its
4079                  * queue base and number in free_list.
4080                  */
4081                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4082                 if (entry == NULL) {
4083                         PMD_DRV_LOG(ERR,
4084                                 "Failed to allocate memory for resource pool");
4085                         return -ENOMEM;
4086                 }
4087                 entry->base = valid_entry->base;
4088                 entry->len = num;
4089                 valid_entry->base += num;
4090                 valid_entry->len -= num;
4091                 valid_entry = entry;
4092         }
4093
4094         /* Insert it into alloc list, not sorted */
4095         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4096
4097         pool->num_free -= valid_entry->len;
4098         pool->num_alloc += valid_entry->len;
4099
4100         return valid_entry->base + pool->base;
4101 }
4102
4103 /**
4104  * bitmap_is_subset - Check whether src2 is subset of src1
4105  **/
4106 static inline int
4107 bitmap_is_subset(uint8_t src1, uint8_t src2)
4108 {
4109         return !((src1 ^ src2) & src2);
4110 }
4111
4112 static enum i40e_status_code
4113 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4114 {
4115         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4116
4117         /* If DCB is not supported, only default TC is supported */
4118         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4119                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4120                 return I40E_NOT_SUPPORTED;
4121         }
4122
4123         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4124                 PMD_DRV_LOG(ERR,
4125                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4126                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4127                 return I40E_NOT_SUPPORTED;
4128         }
4129         return I40E_SUCCESS;
4130 }
4131
4132 int
4133 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4134                                 struct i40e_vsi_vlan_pvid_info *info)
4135 {
4136         struct i40e_hw *hw;
4137         struct i40e_vsi_context ctxt;
4138         uint8_t vlan_flags = 0;
4139         int ret;
4140
4141         if (vsi == NULL || info == NULL) {
4142                 PMD_DRV_LOG(ERR, "invalid parameters");
4143                 return I40E_ERR_PARAM;
4144         }
4145
4146         if (info->on) {
4147                 vsi->info.pvid = info->config.pvid;
4148                 /**
4149                  * If insert pvid is enabled, only tagged pkts are
4150                  * allowed to be sent out.
4151                  */
4152                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4153                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4154         } else {
4155                 vsi->info.pvid = 0;
4156                 if (info->config.reject.tagged == 0)
4157                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4158
4159                 if (info->config.reject.untagged == 0)
4160                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4161         }
4162         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4163                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4164         vsi->info.port_vlan_flags |= vlan_flags;
4165         vsi->info.valid_sections =
4166                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4167         memset(&ctxt, 0, sizeof(ctxt));
4168         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4169         ctxt.seid = vsi->seid;
4170
4171         hw = I40E_VSI_TO_HW(vsi);
4172         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4173         if (ret != I40E_SUCCESS)
4174                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4175
4176         return ret;
4177 }
4178
4179 static int
4180 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4181 {
4182         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4183         int i, ret;
4184         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4185
4186         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4187         if (ret != I40E_SUCCESS)
4188                 return ret;
4189
4190         if (!vsi->seid) {
4191                 PMD_DRV_LOG(ERR, "seid not valid");
4192                 return -EINVAL;
4193         }
4194
4195         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4196         tc_bw_data.tc_valid_bits = enabled_tcmap;
4197         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4198                 tc_bw_data.tc_bw_credits[i] =
4199                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4200
4201         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4202         if (ret != I40E_SUCCESS) {
4203                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4204                 return ret;
4205         }
4206
4207         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4208                                         sizeof(vsi->info.qs_handle));
4209         return I40E_SUCCESS;
4210 }
4211
4212 static enum i40e_status_code
4213 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4214                                  struct i40e_aqc_vsi_properties_data *info,
4215                                  uint8_t enabled_tcmap)
4216 {
4217         enum i40e_status_code ret;
4218         int i, total_tc = 0;
4219         uint16_t qpnum_per_tc, bsf, qp_idx;
4220
4221         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4222         if (ret != I40E_SUCCESS)
4223                 return ret;
4224
4225         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4226                 if (enabled_tcmap & (1 << i))
4227                         total_tc++;
4228         vsi->enabled_tc = enabled_tcmap;
4229
4230         /* Number of queues per enabled TC */
4231         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4232         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4233         bsf = rte_bsf32(qpnum_per_tc);
4234
4235         /* Adjust the queue number to actual queues that can be applied */
4236         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4237                 vsi->nb_qps = qpnum_per_tc * total_tc;
4238
4239         /**
4240          * Configure TC and queue mapping parameters, for enabled TC,
4241          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4242          * default queue will serve it.
4243          */
4244         qp_idx = 0;
4245         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4246                 if (vsi->enabled_tc & (1 << i)) {
4247                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4248                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4249                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4250                         qp_idx += qpnum_per_tc;
4251                 } else
4252                         info->tc_mapping[i] = 0;
4253         }
4254
4255         /* Associate queue number with VSI */
4256         if (vsi->type == I40E_VSI_SRIOV) {
4257                 info->mapping_flags |=
4258                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4259                 for (i = 0; i < vsi->nb_qps; i++)
4260                         info->queue_mapping[i] =
4261                                 rte_cpu_to_le_16(vsi->base_queue + i);
4262         } else {
4263                 info->mapping_flags |=
4264                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4265                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4266         }
4267         info->valid_sections |=
4268                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4269
4270         return I40E_SUCCESS;
4271 }
4272
4273 static int
4274 i40e_veb_release(struct i40e_veb *veb)
4275 {
4276         struct i40e_vsi *vsi;
4277         struct i40e_hw *hw;
4278
4279         if (veb == NULL)
4280                 return -EINVAL;
4281
4282         if (!TAILQ_EMPTY(&veb->head)) {
4283                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4284                 return -EACCES;
4285         }
4286         /* associate_vsi field is NULL for floating VEB */
4287         if (veb->associate_vsi != NULL) {
4288                 vsi = veb->associate_vsi;
4289                 hw = I40E_VSI_TO_HW(vsi);
4290
4291                 vsi->uplink_seid = veb->uplink_seid;
4292                 vsi->veb = NULL;
4293         } else {
4294                 veb->associate_pf->main_vsi->floating_veb = NULL;
4295                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4296         }
4297
4298         i40e_aq_delete_element(hw, veb->seid, NULL);
4299         rte_free(veb);
4300         return I40E_SUCCESS;
4301 }
4302
4303 /* Setup a veb */
4304 static struct i40e_veb *
4305 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4306 {
4307         struct i40e_veb *veb;
4308         int ret;
4309         struct i40e_hw *hw;
4310
4311         if (pf == NULL) {
4312                 PMD_DRV_LOG(ERR,
4313                             "veb setup failed, associated PF shouldn't null");
4314                 return NULL;
4315         }
4316         hw = I40E_PF_TO_HW(pf);
4317
4318         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4319         if (!veb) {
4320                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4321                 goto fail;
4322         }
4323
4324         veb->associate_vsi = vsi;
4325         veb->associate_pf = pf;
4326         TAILQ_INIT(&veb->head);
4327         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4328
4329         /* create floating veb if vsi is NULL */
4330         if (vsi != NULL) {
4331                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4332                                       I40E_DEFAULT_TCMAP, false,
4333                                       &veb->seid, false, NULL);
4334         } else {
4335                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4336                                       true, &veb->seid, false, NULL);
4337         }
4338
4339         if (ret != I40E_SUCCESS) {
4340                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4341                             hw->aq.asq_last_status);
4342                 goto fail;
4343         }
4344
4345         /* get statistics index */
4346         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4347                                 &veb->stats_idx, NULL, NULL, NULL);
4348         if (ret != I40E_SUCCESS) {
4349                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4350                             hw->aq.asq_last_status);
4351                 goto fail;
4352         }
4353         /* Get VEB bandwidth, to be implemented */
4354         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4355         if (vsi)
4356                 vsi->uplink_seid = veb->seid;
4357
4358         return veb;
4359 fail:
4360         rte_free(veb);
4361         return NULL;
4362 }
4363
4364 int
4365 i40e_vsi_release(struct i40e_vsi *vsi)
4366 {
4367         struct i40e_pf *pf;
4368         struct i40e_hw *hw;
4369         struct i40e_vsi_list *vsi_list;
4370         void *temp;
4371         int ret;
4372         struct i40e_mac_filter *f;
4373         uint16_t user_param;
4374
4375         if (!vsi)
4376                 return I40E_SUCCESS;
4377
4378         if (!vsi->adapter)
4379                 return -EFAULT;
4380
4381         user_param = vsi->user_param;
4382
4383         pf = I40E_VSI_TO_PF(vsi);
4384         hw = I40E_VSI_TO_HW(vsi);
4385
4386         /* VSI has child to attach, release child first */
4387         if (vsi->veb) {
4388                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4389                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4390                                 return -1;
4391                 }
4392                 i40e_veb_release(vsi->veb);
4393         }
4394
4395         if (vsi->floating_veb) {
4396                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4397                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4398                                 return -1;
4399                 }
4400         }
4401
4402         /* Remove all macvlan filters of the VSI */
4403         i40e_vsi_remove_all_macvlan_filter(vsi);
4404         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4405                 rte_free(f);
4406
4407         if (vsi->type != I40E_VSI_MAIN &&
4408             ((vsi->type != I40E_VSI_SRIOV) ||
4409             !pf->floating_veb_list[user_param])) {
4410                 /* Remove vsi from parent's sibling list */
4411                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4412                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4413                         return I40E_ERR_PARAM;
4414                 }
4415                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4416                                 &vsi->sib_vsi_list, list);
4417
4418                 /* Remove all switch element of the VSI */
4419                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4420                 if (ret != I40E_SUCCESS)
4421                         PMD_DRV_LOG(ERR, "Failed to delete element");
4422         }
4423
4424         if ((vsi->type == I40E_VSI_SRIOV) &&
4425             pf->floating_veb_list[user_param]) {
4426                 /* Remove vsi from parent's sibling list */
4427                 if (vsi->parent_vsi == NULL ||
4428                     vsi->parent_vsi->floating_veb == NULL) {
4429                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4430                         return I40E_ERR_PARAM;
4431                 }
4432                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4433                              &vsi->sib_vsi_list, list);
4434
4435                 /* Remove all switch element of the VSI */
4436                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4437                 if (ret != I40E_SUCCESS)
4438                         PMD_DRV_LOG(ERR, "Failed to delete element");
4439         }
4440
4441         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4442
4443         if (vsi->type != I40E_VSI_SRIOV)
4444                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4445         rte_free(vsi);
4446
4447         return I40E_SUCCESS;
4448 }
4449
4450 static int
4451 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4452 {
4453         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4454         struct i40e_aqc_remove_macvlan_element_data def_filter;
4455         struct i40e_mac_filter_info filter;
4456         int ret;
4457
4458         if (vsi->type != I40E_VSI_MAIN)
4459                 return I40E_ERR_CONFIG;
4460         memset(&def_filter, 0, sizeof(def_filter));
4461         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4462                                         ETH_ADDR_LEN);
4463         def_filter.vlan_tag = 0;
4464         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4465                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4466         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4467         if (ret != I40E_SUCCESS) {
4468                 struct i40e_mac_filter *f;
4469                 struct ether_addr *mac;
4470
4471                 PMD_DRV_LOG(WARNING,
4472                         "Cannot remove the default macvlan filter");
4473                 /* It needs to add the permanent mac into mac list */
4474                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4475                 if (f == NULL) {
4476                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4477                         return I40E_ERR_NO_MEMORY;
4478                 }
4479                 mac = &f->mac_info.mac_addr;
4480                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4481                                 ETH_ADDR_LEN);
4482                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4483                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4484                 vsi->mac_num++;
4485
4486                 return ret;
4487         }
4488         (void)rte_memcpy(&filter.mac_addr,
4489                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4490         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4491         return i40e_vsi_add_mac(vsi, &filter);
4492 }
4493
4494 /*
4495  * i40e_vsi_get_bw_config - Query VSI BW Information
4496  * @vsi: the VSI to be queried
4497  *
4498  * Returns 0 on success, negative value on failure
4499  */
4500 static enum i40e_status_code
4501 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4502 {
4503         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4504         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4505         struct i40e_hw *hw = &vsi->adapter->hw;
4506         i40e_status ret;
4507         int i;
4508         uint32_t bw_max;
4509
4510         memset(&bw_config, 0, sizeof(bw_config));
4511         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4512         if (ret != I40E_SUCCESS) {
4513                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4514                             hw->aq.asq_last_status);
4515                 return ret;
4516         }
4517
4518         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4519         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4520                                         &ets_sla_config, NULL);
4521         if (ret != I40E_SUCCESS) {
4522                 PMD_DRV_LOG(ERR,
4523                         "VSI failed to get TC bandwdith configuration %u",
4524                         hw->aq.asq_last_status);
4525                 return ret;
4526         }
4527
4528         /* store and print out BW info */
4529         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4530         vsi->bw_info.bw_max = bw_config.max_bw;
4531         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4532         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4533         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4534                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4535                      I40E_16_BIT_WIDTH);
4536         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4537                 vsi->bw_info.bw_ets_share_credits[i] =
4538                                 ets_sla_config.share_credits[i];
4539                 vsi->bw_info.bw_ets_credits[i] =
4540                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4541                 /* 4 bits per TC, 4th bit is reserved */
4542                 vsi->bw_info.bw_ets_max[i] =
4543                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4544                                   RTE_LEN2MASK(3, uint8_t));
4545                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4546                             vsi->bw_info.bw_ets_share_credits[i]);
4547                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4548                             vsi->bw_info.bw_ets_credits[i]);
4549                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4550                             vsi->bw_info.bw_ets_max[i]);
4551         }
4552
4553         return I40E_SUCCESS;
4554 }
4555
4556 /* i40e_enable_pf_lb
4557  * @pf: pointer to the pf structure
4558  *
4559  * allow loopback on pf
4560  */
4561 static inline void
4562 i40e_enable_pf_lb(struct i40e_pf *pf)
4563 {
4564         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4565         struct i40e_vsi_context ctxt;
4566         int ret;
4567
4568         /* Use the FW API if FW >= v5.0 */
4569         if (hw->aq.fw_maj_ver < 5) {
4570                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4571                 return;
4572         }
4573
4574         memset(&ctxt, 0, sizeof(ctxt));
4575         ctxt.seid = pf->main_vsi_seid;
4576         ctxt.pf_num = hw->pf_id;
4577         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4578         if (ret) {
4579                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4580                             ret, hw->aq.asq_last_status);
4581                 return;
4582         }
4583         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4584         ctxt.info.valid_sections =
4585                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4586         ctxt.info.switch_id |=
4587                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4588
4589         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4590         if (ret)
4591                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4592                             hw->aq.asq_last_status);
4593 }
4594
4595 /* Setup a VSI */
4596 struct i40e_vsi *
4597 i40e_vsi_setup(struct i40e_pf *pf,
4598                enum i40e_vsi_type type,
4599                struct i40e_vsi *uplink_vsi,
4600                uint16_t user_param)
4601 {
4602         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4603         struct i40e_vsi *vsi;
4604         struct i40e_mac_filter_info filter;
4605         int ret;
4606         struct i40e_vsi_context ctxt;
4607         struct ether_addr broadcast =
4608                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4609
4610         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4611             uplink_vsi == NULL) {
4612                 PMD_DRV_LOG(ERR,
4613                         "VSI setup failed, VSI link shouldn't be NULL");
4614                 return NULL;
4615         }
4616
4617         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4618                 PMD_DRV_LOG(ERR,
4619                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4620                 return NULL;
4621         }
4622
4623         /* two situations
4624          * 1.type is not MAIN and uplink vsi is not NULL
4625          * If uplink vsi didn't setup VEB, create one first under veb field
4626          * 2.type is SRIOV and the uplink is NULL
4627          * If floating VEB is NULL, create one veb under floating veb field
4628          */
4629
4630         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4631             uplink_vsi->veb == NULL) {
4632                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4633
4634                 if (uplink_vsi->veb == NULL) {
4635                         PMD_DRV_LOG(ERR, "VEB setup failed");
4636                         return NULL;
4637                 }
4638                 /* set ALLOWLOOPBACk on pf, when veb is created */
4639                 i40e_enable_pf_lb(pf);
4640         }
4641
4642         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4643             pf->main_vsi->floating_veb == NULL) {
4644                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4645
4646                 if (pf->main_vsi->floating_veb == NULL) {
4647                         PMD_DRV_LOG(ERR, "VEB setup failed");
4648                         return NULL;
4649                 }
4650         }
4651
4652         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4653         if (!vsi) {
4654                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4655                 return NULL;
4656         }
4657         TAILQ_INIT(&vsi->mac_list);
4658         vsi->type = type;
4659         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4660         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4661         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4662         vsi->user_param = user_param;
4663         vsi->vlan_anti_spoof_on = 0;
4664         /* Allocate queues */
4665         switch (vsi->type) {
4666         case I40E_VSI_MAIN  :
4667                 vsi->nb_qps = pf->lan_nb_qps;
4668                 break;
4669         case I40E_VSI_SRIOV :
4670                 vsi->nb_qps = pf->vf_nb_qps;
4671                 break;
4672         case I40E_VSI_VMDQ2:
4673                 vsi->nb_qps = pf->vmdq_nb_qps;
4674                 break;
4675         case I40E_VSI_FDIR:
4676                 vsi->nb_qps = pf->fdir_nb_qps;
4677                 break;
4678         default:
4679                 goto fail_mem;
4680         }
4681         /*
4682          * The filter status descriptor is reported in rx queue 0,
4683          * while the tx queue for fdir filter programming has no
4684          * such constraints, can be non-zero queues.
4685          * To simplify it, choose FDIR vsi use queue 0 pair.
4686          * To make sure it will use queue 0 pair, queue allocation
4687          * need be done before this function is called
4688          */
4689         if (type != I40E_VSI_FDIR) {
4690                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4691                         if (ret < 0) {
4692                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4693                                                 vsi->seid, ret);
4694                                 goto fail_mem;
4695                         }
4696                         vsi->base_queue = ret;
4697         } else
4698                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4699
4700         /* VF has MSIX interrupt in VF range, don't allocate here */
4701         if (type == I40E_VSI_MAIN) {
4702                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4703                                           RTE_MIN(vsi->nb_qps,
4704                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4705                 if (ret < 0) {
4706                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4707                                     vsi->seid, ret);
4708                         goto fail_queue_alloc;
4709                 }
4710                 vsi->msix_intr = ret;
4711                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4712         } else if (type != I40E_VSI_SRIOV) {
4713                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4714                 if (ret < 0) {
4715                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4716                         goto fail_queue_alloc;
4717                 }
4718                 vsi->msix_intr = ret;
4719                 vsi->nb_msix = 1;
4720         } else {
4721                 vsi->msix_intr = 0;
4722                 vsi->nb_msix = 0;
4723         }
4724
4725         /* Add VSI */
4726         if (type == I40E_VSI_MAIN) {
4727                 /* For main VSI, no need to add since it's default one */
4728                 vsi->uplink_seid = pf->mac_seid;
4729                 vsi->seid = pf->main_vsi_seid;
4730                 /* Bind queues with specific MSIX interrupt */
4731                 /**
4732                  * Needs 2 interrupt at least, one for misc cause which will
4733                  * enabled from OS side, Another for queues binding the
4734                  * interrupt from device side only.
4735                  */
4736
4737                 /* Get default VSI parameters from hardware */
4738                 memset(&ctxt, 0, sizeof(ctxt));
4739                 ctxt.seid = vsi->seid;
4740                 ctxt.pf_num = hw->pf_id;
4741                 ctxt.uplink_seid = vsi->uplink_seid;
4742                 ctxt.vf_num = 0;
4743                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4744                 if (ret != I40E_SUCCESS) {
4745                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4746                         goto fail_msix_alloc;
4747                 }
4748                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4749                         sizeof(struct i40e_aqc_vsi_properties_data));
4750                 vsi->vsi_id = ctxt.vsi_number;
4751                 vsi->info.valid_sections = 0;
4752
4753                 /* Configure tc, enabled TC0 only */
4754                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4755                         I40E_SUCCESS) {
4756                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4757                         goto fail_msix_alloc;
4758                 }
4759
4760                 /* TC, queue mapping */
4761                 memset(&ctxt, 0, sizeof(ctxt));
4762                 vsi->info.valid_sections |=
4763                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4764                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4765                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4766                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4767                         sizeof(struct i40e_aqc_vsi_properties_data));
4768                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4769                                                 I40E_DEFAULT_TCMAP);
4770                 if (ret != I40E_SUCCESS) {
4771                         PMD_DRV_LOG(ERR,
4772                                 "Failed to configure TC queue mapping");
4773                         goto fail_msix_alloc;
4774                 }
4775                 ctxt.seid = vsi->seid;
4776                 ctxt.pf_num = hw->pf_id;
4777                 ctxt.uplink_seid = vsi->uplink_seid;
4778                 ctxt.vf_num = 0;
4779
4780                 /* Update VSI parameters */
4781                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4782                 if (ret != I40E_SUCCESS) {
4783                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4784                         goto fail_msix_alloc;
4785                 }
4786
4787                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4788                                                 sizeof(vsi->info.tc_mapping));
4789                 (void)rte_memcpy(&vsi->info.queue_mapping,
4790                                 &ctxt.info.queue_mapping,
4791                         sizeof(vsi->info.queue_mapping));
4792                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4793                 vsi->info.valid_sections = 0;
4794
4795                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4796                                 ETH_ADDR_LEN);
4797
4798                 /**
4799                  * Updating default filter settings are necessary to prevent
4800                  * reception of tagged packets.
4801                  * Some old firmware configurations load a default macvlan
4802                  * filter which accepts both tagged and untagged packets.
4803                  * The updating is to use a normal filter instead if needed.
4804                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4805                  * The firmware with correct configurations load the default
4806                  * macvlan filter which is expected and cannot be removed.
4807                  */
4808                 i40e_update_default_filter_setting(vsi);
4809                 i40e_config_qinq(hw, vsi);
4810         } else if (type == I40E_VSI_SRIOV) {
4811                 memset(&ctxt, 0, sizeof(ctxt));
4812                 /**
4813                  * For other VSI, the uplink_seid equals to uplink VSI's
4814                  * uplink_seid since they share same VEB
4815                  */
4816                 if (uplink_vsi == NULL)
4817                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4818                 else
4819                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4820                 ctxt.pf_num = hw->pf_id;
4821                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4822                 ctxt.uplink_seid = vsi->uplink_seid;
4823                 ctxt.connection_type = 0x1;
4824                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4825
4826                 /* Use the VEB configuration if FW >= v5.0 */
4827                 if (hw->aq.fw_maj_ver >= 5) {
4828                         /* Configure switch ID */
4829                         ctxt.info.valid_sections |=
4830                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4831                         ctxt.info.switch_id =
4832                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4833                 }
4834
4835                 /* Configure port/vlan */
4836                 ctxt.info.valid_sections |=
4837                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4838                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4839                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4840                                                 I40E_DEFAULT_TCMAP);
4841                 if (ret != I40E_SUCCESS) {
4842                         PMD_DRV_LOG(ERR,
4843                                 "Failed to configure TC queue mapping");
4844                         goto fail_msix_alloc;
4845                 }
4846                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4847                 ctxt.info.valid_sections |=
4848                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4849                 /**
4850                  * Since VSI is not created yet, only configure parameter,
4851                  * will add vsi below.
4852                  */
4853
4854                 i40e_config_qinq(hw, vsi);
4855         } else if (type == I40E_VSI_VMDQ2) {
4856                 memset(&ctxt, 0, sizeof(ctxt));
4857                 /*
4858                  * For other VSI, the uplink_seid equals to uplink VSI's
4859                  * uplink_seid since they share same VEB
4860                  */
4861                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4862                 ctxt.pf_num = hw->pf_id;
4863                 ctxt.vf_num = 0;
4864                 ctxt.uplink_seid = vsi->uplink_seid;
4865                 ctxt.connection_type = 0x1;
4866                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4867
4868                 ctxt.info.valid_sections |=
4869                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4870                 /* user_param carries flag to enable loop back */
4871                 if (user_param) {
4872                         ctxt.info.switch_id =
4873                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4874                         ctxt.info.switch_id |=
4875                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4876                 }
4877
4878                 /* Configure port/vlan */
4879                 ctxt.info.valid_sections |=
4880                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4881                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4882                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4883                                                 I40E_DEFAULT_TCMAP);
4884                 if (ret != I40E_SUCCESS) {
4885                         PMD_DRV_LOG(ERR,
4886                                 "Failed to configure TC queue mapping");
4887                         goto fail_msix_alloc;
4888                 }
4889                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4890                 ctxt.info.valid_sections |=
4891                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4892         } else if (type == I40E_VSI_FDIR) {
4893                 memset(&ctxt, 0, sizeof(ctxt));
4894                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4895                 ctxt.pf_num = hw->pf_id;
4896                 ctxt.vf_num = 0;
4897                 ctxt.uplink_seid = vsi->uplink_seid;
4898                 ctxt.connection_type = 0x1;     /* regular data port */
4899                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4900                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4901                                                 I40E_DEFAULT_TCMAP);
4902                 if (ret != I40E_SUCCESS) {
4903                         PMD_DRV_LOG(ERR,
4904                                 "Failed to configure TC queue mapping.");
4905                         goto fail_msix_alloc;
4906                 }
4907                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4908                 ctxt.info.valid_sections |=
4909                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4910         } else {
4911                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4912                 goto fail_msix_alloc;
4913         }
4914
4915         if (vsi->type != I40E_VSI_MAIN) {
4916                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4917                 if (ret != I40E_SUCCESS) {
4918                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4919                                     hw->aq.asq_last_status);
4920                         goto fail_msix_alloc;
4921                 }
4922                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4923                 vsi->info.valid_sections = 0;
4924                 vsi->seid = ctxt.seid;
4925                 vsi->vsi_id = ctxt.vsi_number;
4926                 vsi->sib_vsi_list.vsi = vsi;
4927                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4928                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4929                                           &vsi->sib_vsi_list, list);
4930                 } else {
4931                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4932                                           &vsi->sib_vsi_list, list);
4933                 }
4934         }
4935
4936         /* MAC/VLAN configuration */
4937         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4938         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4939
4940         ret = i40e_vsi_add_mac(vsi, &filter);
4941         if (ret != I40E_SUCCESS) {
4942                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4943                 goto fail_msix_alloc;
4944         }
4945
4946         /* Get VSI BW information */
4947         i40e_vsi_get_bw_config(vsi);
4948         return vsi;
4949 fail_msix_alloc:
4950         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4951 fail_queue_alloc:
4952         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4953 fail_mem:
4954         rte_free(vsi);
4955         return NULL;
4956 }
4957
4958 /* Configure vlan filter on or off */
4959 int
4960 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4961 {
4962         int i, num;
4963         struct i40e_mac_filter *f;
4964         void *temp;
4965         struct i40e_mac_filter_info *mac_filter;
4966         enum rte_mac_filter_type desired_filter;
4967         int ret = I40E_SUCCESS;
4968
4969         if (on) {
4970                 /* Filter to match MAC and VLAN */
4971                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4972         } else {
4973                 /* Filter to match only MAC */
4974                 desired_filter = RTE_MAC_PERFECT_MATCH;
4975         }
4976
4977         num = vsi->mac_num;
4978
4979         mac_filter = rte_zmalloc("mac_filter_info_data",
4980                                  num * sizeof(*mac_filter), 0);
4981         if (mac_filter == NULL) {
4982                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4983                 return I40E_ERR_NO_MEMORY;
4984         }
4985
4986         i = 0;
4987
4988         /* Remove all existing mac */
4989         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4990                 mac_filter[i] = f->mac_info;
4991                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4992                 if (ret) {
4993                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4994                                     on ? "enable" : "disable");
4995                         goto DONE;
4996                 }
4997                 i++;
4998         }
4999
5000         /* Override with new filter */
5001         for (i = 0; i < num; i++) {
5002                 mac_filter[i].filter_type = desired_filter;
5003                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5004                 if (ret) {
5005                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5006                                     on ? "enable" : "disable");
5007                         goto DONE;
5008                 }
5009         }
5010
5011 DONE:
5012         rte_free(mac_filter);
5013         return ret;
5014 }
5015
5016 /* Configure vlan stripping on or off */
5017 int
5018 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5019 {
5020         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5021         struct i40e_vsi_context ctxt;
5022         uint8_t vlan_flags;
5023         int ret = I40E_SUCCESS;
5024
5025         /* Check if it has been already on or off */
5026         if (vsi->info.valid_sections &
5027                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5028                 if (on) {
5029                         if ((vsi->info.port_vlan_flags &
5030                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5031                                 return 0; /* already on */
5032                 } else {
5033                         if ((vsi->info.port_vlan_flags &
5034                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5035                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5036                                 return 0; /* already off */
5037                 }
5038         }
5039
5040         if (on)
5041                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5042         else
5043                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5044         vsi->info.valid_sections =
5045                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5046         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5047         vsi->info.port_vlan_flags |= vlan_flags;
5048         ctxt.seid = vsi->seid;
5049         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5050         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5051         if (ret)
5052                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5053                             on ? "enable" : "disable");
5054
5055         return ret;
5056 }
5057
5058 static int
5059 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5060 {
5061         struct rte_eth_dev_data *data = dev->data;
5062         int ret;
5063         int mask = 0;
5064
5065         /* Apply vlan offload setting */
5066         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5067         i40e_vlan_offload_set(dev, mask);
5068
5069         /* Apply double-vlan setting, not implemented yet */
5070
5071         /* Apply pvid setting */
5072         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5073                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5074         if (ret)
5075                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5076
5077         return ret;
5078 }
5079
5080 static int
5081 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5082 {
5083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5084
5085         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5086 }
5087
5088 static int
5089 i40e_update_flow_control(struct i40e_hw *hw)
5090 {
5091 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5092         struct i40e_link_status link_status;
5093         uint32_t rxfc = 0, txfc = 0, reg;
5094         uint8_t an_info;
5095         int ret;
5096
5097         memset(&link_status, 0, sizeof(link_status));
5098         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5099         if (ret != I40E_SUCCESS) {
5100                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5101                 goto write_reg; /* Disable flow control */
5102         }
5103
5104         an_info = hw->phy.link_info.an_info;
5105         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5106                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5107                 ret = I40E_ERR_NOT_READY;
5108                 goto write_reg; /* Disable flow control */
5109         }
5110         /**
5111          * If link auto negotiation is enabled, flow control needs to
5112          * be configured according to it
5113          */
5114         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5115         case I40E_LINK_PAUSE_RXTX:
5116                 rxfc = 1;
5117                 txfc = 1;
5118                 hw->fc.current_mode = I40E_FC_FULL;
5119                 break;
5120         case I40E_AQ_LINK_PAUSE_RX:
5121                 rxfc = 1;
5122                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5123                 break;
5124         case I40E_AQ_LINK_PAUSE_TX:
5125                 txfc = 1;
5126                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5127                 break;
5128         default:
5129                 hw->fc.current_mode = I40E_FC_NONE;
5130                 break;
5131         }
5132
5133 write_reg:
5134         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5135                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5136         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5137         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5138         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5139         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5140
5141         return ret;
5142 }
5143
5144 /* PF setup */
5145 static int
5146 i40e_pf_setup(struct i40e_pf *pf)
5147 {
5148         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5149         struct i40e_filter_control_settings settings;
5150         struct i40e_vsi *vsi;
5151         int ret;
5152
5153         /* Clear all stats counters */
5154         pf->offset_loaded = FALSE;
5155         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5156         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5157
5158         ret = i40e_pf_get_switch_config(pf);
5159         if (ret != I40E_SUCCESS) {
5160                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5161                 return ret;
5162         }
5163         if (pf->flags & I40E_FLAG_FDIR) {
5164                 /* make queue allocated first, let FDIR use queue pair 0*/
5165                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5166                 if (ret != I40E_FDIR_QUEUE_ID) {
5167                         PMD_DRV_LOG(ERR,
5168                                 "queue allocation fails for FDIR: ret =%d",
5169                                 ret);
5170                         pf->flags &= ~I40E_FLAG_FDIR;
5171                 }
5172         }
5173         /*  main VSI setup */
5174         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5175         if (!vsi) {
5176                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5177                 return I40E_ERR_NOT_READY;
5178         }
5179         pf->main_vsi = vsi;
5180
5181         /* Configure filter control */
5182         memset(&settings, 0, sizeof(settings));
5183         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5184                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5185         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5186                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5187         else {
5188                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5189                         hw->func_caps.rss_table_size);
5190                 return I40E_ERR_PARAM;
5191         }
5192         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5193                 hw->func_caps.rss_table_size);
5194         pf->hash_lut_size = hw->func_caps.rss_table_size;
5195
5196         /* Enable ethtype and macvlan filters */
5197         settings.enable_ethtype = TRUE;
5198         settings.enable_macvlan = TRUE;
5199         ret = i40e_set_filter_control(hw, &settings);
5200         if (ret)
5201                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5202                                                                 ret);
5203
5204         /* Update flow control according to the auto negotiation */
5205         i40e_update_flow_control(hw);
5206
5207         return I40E_SUCCESS;
5208 }
5209
5210 int
5211 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5212 {
5213         uint32_t reg;
5214         uint16_t j;
5215
5216         /**
5217          * Set or clear TX Queue Disable flags,
5218          * which is required by hardware.
5219          */
5220         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5221         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5222
5223         /* Wait until the request is finished */
5224         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5225                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5226                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5227                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5228                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5229                                                         & 0x1))) {
5230                         break;
5231                 }
5232         }
5233         if (on) {
5234                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5235                         return I40E_SUCCESS; /* already on, skip next steps */
5236
5237                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5238                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5239         } else {
5240                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5241                         return I40E_SUCCESS; /* already off, skip next steps */
5242                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5243         }
5244         /* Write the register */
5245         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5246         /* Check the result */
5247         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5248                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5249                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5250                 if (on) {
5251                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5252                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5253                                 break;
5254                 } else {
5255                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5256                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5257                                 break;
5258                 }
5259         }
5260         /* Check if it is timeout */
5261         if (j >= I40E_CHK_Q_ENA_COUNT) {
5262                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5263                             (on ? "enable" : "disable"), q_idx);
5264                 return I40E_ERR_TIMEOUT;
5265         }
5266
5267         return I40E_SUCCESS;
5268 }
5269
5270 /* Swith on or off the tx queues */
5271 static int
5272 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5273 {
5274         struct rte_eth_dev_data *dev_data = pf->dev_data;
5275         struct i40e_tx_queue *txq;
5276         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5277         uint16_t i;
5278         int ret;
5279
5280         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5281                 txq = dev_data->tx_queues[i];
5282                 /* Don't operate the queue if not configured or
5283                  * if starting only per queue */
5284                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5285                         continue;
5286                 if (on)
5287                         ret = i40e_dev_tx_queue_start(dev, i);
5288                 else
5289                         ret = i40e_dev_tx_queue_stop(dev, i);
5290                 if ( ret != I40E_SUCCESS)
5291                         return ret;
5292         }
5293
5294         return I40E_SUCCESS;
5295 }
5296
5297 int
5298 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5299 {
5300         uint32_t reg;
5301         uint16_t j;
5302
5303         /* Wait until the request is finished */
5304         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5305                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5306                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5307                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5308                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5309                         break;
5310         }
5311
5312         if (on) {
5313                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5314                         return I40E_SUCCESS; /* Already on, skip next steps */
5315                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5316         } else {
5317                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5318                         return I40E_SUCCESS; /* Already off, skip next steps */
5319                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5320         }
5321
5322         /* Write the register */
5323         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5324         /* Check the result */
5325         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5326                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5327                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5328                 if (on) {
5329                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5330                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5331                                 break;
5332                 } else {
5333                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5334                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5335                                 break;
5336                 }
5337         }
5338
5339         /* Check if it is timeout */
5340         if (j >= I40E_CHK_Q_ENA_COUNT) {
5341                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5342                             (on ? "enable" : "disable"), q_idx);
5343                 return I40E_ERR_TIMEOUT;
5344         }
5345
5346         return I40E_SUCCESS;
5347 }
5348 /* Switch on or off the rx queues */
5349 static int
5350 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5351 {
5352         struct rte_eth_dev_data *dev_data = pf->dev_data;
5353         struct i40e_rx_queue *rxq;
5354         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5355         uint16_t i;
5356         int ret;
5357
5358         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5359                 rxq = dev_data->rx_queues[i];
5360                 /* Don't operate the queue if not configured or
5361                  * if starting only per queue */
5362                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5363                         continue;
5364                 if (on)
5365                         ret = i40e_dev_rx_queue_start(dev, i);
5366                 else
5367                         ret = i40e_dev_rx_queue_stop(dev, i);
5368                 if (ret != I40E_SUCCESS)
5369                         return ret;
5370         }
5371
5372         return I40E_SUCCESS;
5373 }
5374
5375 /* Switch on or off all the rx/tx queues */
5376 int
5377 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5378 {
5379         int ret;
5380
5381         if (on) {
5382                 /* enable rx queues before enabling tx queues */
5383                 ret = i40e_dev_switch_rx_queues(pf, on);
5384                 if (ret) {
5385                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5386                         return ret;
5387                 }
5388                 ret = i40e_dev_switch_tx_queues(pf, on);
5389         } else {
5390                 /* Stop tx queues before stopping rx queues */
5391                 ret = i40e_dev_switch_tx_queues(pf, on);
5392                 if (ret) {
5393                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5394                         return ret;
5395                 }
5396                 ret = i40e_dev_switch_rx_queues(pf, on);
5397         }
5398
5399         return ret;
5400 }
5401
5402 /* Initialize VSI for TX */
5403 static int
5404 i40e_dev_tx_init(struct i40e_pf *pf)
5405 {
5406         struct rte_eth_dev_data *data = pf->dev_data;
5407         uint16_t i;
5408         uint32_t ret = I40E_SUCCESS;
5409         struct i40e_tx_queue *txq;
5410
5411         for (i = 0; i < data->nb_tx_queues; i++) {
5412                 txq = data->tx_queues[i];
5413                 if (!txq || !txq->q_set)
5414                         continue;
5415                 ret = i40e_tx_queue_init(txq);
5416                 if (ret != I40E_SUCCESS)
5417                         break;
5418         }
5419         if (ret == I40E_SUCCESS)
5420                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5421                                      ->eth_dev);
5422
5423         return ret;
5424 }
5425
5426 /* Initialize VSI for RX */
5427 static int
5428 i40e_dev_rx_init(struct i40e_pf *pf)
5429 {
5430         struct rte_eth_dev_data *data = pf->dev_data;
5431         int ret = I40E_SUCCESS;
5432         uint16_t i;
5433         struct i40e_rx_queue *rxq;
5434
5435         i40e_pf_config_mq_rx(pf);
5436         for (i = 0; i < data->nb_rx_queues; i++) {
5437                 rxq = data->rx_queues[i];
5438                 if (!rxq || !rxq->q_set)
5439                         continue;
5440
5441                 ret = i40e_rx_queue_init(rxq);
5442                 if (ret != I40E_SUCCESS) {
5443                         PMD_DRV_LOG(ERR,
5444                                 "Failed to do RX queue initialization");
5445                         break;
5446                 }
5447         }
5448         if (ret == I40E_SUCCESS)
5449                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5450                                      ->eth_dev);
5451
5452         return ret;
5453 }
5454
5455 static int
5456 i40e_dev_rxtx_init(struct i40e_pf *pf)
5457 {
5458         int err;
5459
5460         err = i40e_dev_tx_init(pf);
5461         if (err) {
5462                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5463                 return err;
5464         }
5465         err = i40e_dev_rx_init(pf);
5466         if (err) {
5467                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5468                 return err;
5469         }
5470
5471         return err;
5472 }
5473
5474 static int
5475 i40e_vmdq_setup(struct rte_eth_dev *dev)
5476 {
5477         struct rte_eth_conf *conf = &dev->data->dev_conf;
5478         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5479         int i, err, conf_vsis, j, loop;
5480         struct i40e_vsi *vsi;
5481         struct i40e_vmdq_info *vmdq_info;
5482         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5483         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5484
5485         /*
5486          * Disable interrupt to avoid message from VF. Furthermore, it will
5487          * avoid race condition in VSI creation/destroy.
5488          */
5489         i40e_pf_disable_irq0(hw);
5490
5491         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5492                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5493                 return -ENOTSUP;
5494         }
5495
5496         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5497         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5498                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5499                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5500                         pf->max_nb_vmdq_vsi);
5501                 return -ENOTSUP;
5502         }
5503
5504         if (pf->vmdq != NULL) {
5505                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5506                 return 0;
5507         }
5508
5509         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5510                                 sizeof(*vmdq_info) * conf_vsis, 0);
5511
5512         if (pf->vmdq == NULL) {
5513                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5514                 return -ENOMEM;
5515         }
5516
5517         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5518
5519         /* Create VMDQ VSI */
5520         for (i = 0; i < conf_vsis; i++) {
5521                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5522                                 vmdq_conf->enable_loop_back);
5523                 if (vsi == NULL) {
5524                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5525                         err = -1;
5526                         goto err_vsi_setup;
5527                 }
5528                 vmdq_info = &pf->vmdq[i];
5529                 vmdq_info->pf = pf;
5530                 vmdq_info->vsi = vsi;
5531         }
5532         pf->nb_cfg_vmdq_vsi = conf_vsis;
5533
5534         /* Configure Vlan */
5535         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5536         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5537                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5538                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5539                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5540                                         vmdq_conf->pool_map[i].vlan_id, j);
5541
5542                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5543                                                 vmdq_conf->pool_map[i].vlan_id);
5544                                 if (err) {
5545                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5546                                         err = -1;
5547                                         goto err_vsi_setup;
5548                                 }
5549                         }
5550                 }
5551         }
5552
5553         i40e_pf_enable_irq0(hw);
5554
5555         return 0;
5556
5557 err_vsi_setup:
5558         for (i = 0; i < conf_vsis; i++)
5559                 if (pf->vmdq[i].vsi == NULL)
5560                         break;
5561                 else
5562                         i40e_vsi_release(pf->vmdq[i].vsi);
5563
5564         rte_free(pf->vmdq);
5565         pf->vmdq = NULL;
5566         i40e_pf_enable_irq0(hw);
5567         return err;
5568 }
5569
5570 static void
5571 i40e_stat_update_32(struct i40e_hw *hw,
5572                    uint32_t reg,
5573                    bool offset_loaded,
5574                    uint64_t *offset,
5575                    uint64_t *stat)
5576 {
5577         uint64_t new_data;
5578
5579         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5580         if (!offset_loaded)
5581                 *offset = new_data;
5582
5583         if (new_data >= *offset)
5584                 *stat = (uint64_t)(new_data - *offset);
5585         else
5586                 *stat = (uint64_t)((new_data +
5587                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5588 }
5589
5590 static void
5591 i40e_stat_update_48(struct i40e_hw *hw,
5592                    uint32_t hireg,
5593                    uint32_t loreg,
5594                    bool offset_loaded,
5595                    uint64_t *offset,
5596                    uint64_t *stat)
5597 {
5598         uint64_t new_data;
5599
5600         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5601         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5602                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5603
5604         if (!offset_loaded)
5605                 *offset = new_data;
5606
5607         if (new_data >= *offset)
5608                 *stat = new_data - *offset;
5609         else
5610                 *stat = (uint64_t)((new_data +
5611                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5612
5613         *stat &= I40E_48_BIT_MASK;
5614 }
5615
5616 /* Disable IRQ0 */
5617 void
5618 i40e_pf_disable_irq0(struct i40e_hw *hw)
5619 {
5620         /* Disable all interrupt types */
5621         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5622         I40E_WRITE_FLUSH(hw);
5623 }
5624
5625 /* Enable IRQ0 */
5626 void
5627 i40e_pf_enable_irq0(struct i40e_hw *hw)
5628 {
5629         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5630                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5631                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5632                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5633         I40E_WRITE_FLUSH(hw);
5634 }
5635
5636 static void
5637 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5638 {
5639         /* read pending request and disable first */
5640         i40e_pf_disable_irq0(hw);
5641         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5642         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5643                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5644
5645         if (no_queue)
5646                 /* Link no queues with irq0 */
5647                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5648                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5649 }
5650
5651 static void
5652 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5653 {
5654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5655         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5656         int i;
5657         uint16_t abs_vf_id;
5658         uint32_t index, offset, val;
5659
5660         if (!pf->vfs)
5661                 return;
5662         /**
5663          * Try to find which VF trigger a reset, use absolute VF id to access
5664          * since the reg is global register.
5665          */
5666         for (i = 0; i < pf->vf_num; i++) {
5667                 abs_vf_id = hw->func_caps.vf_base_id + i;
5668                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5669                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5670                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5671                 /* VFR event occured */
5672                 if (val & (0x1 << offset)) {
5673                         int ret;
5674
5675                         /* Clear the event first */
5676                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5677                                                         (0x1 << offset));
5678                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5679                         /**
5680                          * Only notify a VF reset event occured,
5681                          * don't trigger another SW reset
5682                          */
5683                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5684                         if (ret != I40E_SUCCESS)
5685                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5686                 }
5687         }
5688 }
5689
5690 static void
5691 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5692 {
5693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5694         struct i40e_virtchnl_pf_event event;
5695         int i;
5696
5697         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5698         event.event_data.link_event.link_status =
5699                 dev->data->dev_link.link_status;
5700         event.event_data.link_event.link_speed =
5701                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5702
5703         for (i = 0; i < pf->vf_num; i++)
5704                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5705                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5706 }
5707
5708 static void
5709 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5710 {
5711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5712         struct i40e_arq_event_info info;
5713         uint16_t pending, opcode;
5714         int ret;
5715
5716         info.buf_len = I40E_AQ_BUF_SZ;
5717         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5718         if (!info.msg_buf) {
5719                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5720                 return;
5721         }
5722
5723         pending = 1;
5724         while (pending) {
5725                 ret = i40e_clean_arq_element(hw, &info, &pending);
5726
5727                 if (ret != I40E_SUCCESS) {
5728                         PMD_DRV_LOG(INFO,
5729                                 "Failed to read msg from AdminQ, aq_err: %u",
5730                                 hw->aq.asq_last_status);
5731                         break;
5732                 }
5733                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5734
5735                 switch (opcode) {
5736                 case i40e_aqc_opc_send_msg_to_pf:
5737                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5738                         i40e_pf_host_handle_vf_msg(dev,
5739                                         rte_le_to_cpu_16(info.desc.retval),
5740                                         rte_le_to_cpu_32(info.desc.cookie_high),
5741                                         rte_le_to_cpu_32(info.desc.cookie_low),
5742                                         info.msg_buf,
5743                                         info.msg_len);
5744                         break;
5745                 case i40e_aqc_opc_get_link_status:
5746                         ret = i40e_dev_link_update(dev, 0);
5747                         if (!ret) {
5748                                 i40e_notify_all_vfs_link_status(dev);
5749                                 _rte_eth_dev_callback_process(dev,
5750                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5751                         }
5752                         break;
5753                 default:
5754                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5755                                     opcode);
5756                         break;
5757                 }
5758         }
5759         rte_free(info.msg_buf);
5760 }
5761
5762 /**
5763  * Interrupt handler triggered by NIC  for handling
5764  * specific interrupt.
5765  *
5766  * @param handle
5767  *  Pointer to interrupt handle.
5768  * @param param
5769  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5770  *
5771  * @return
5772  *  void
5773  */
5774 static void
5775 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5776                            void *param)
5777 {
5778         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5780         uint32_t icr0;
5781
5782         /* Disable interrupt */
5783         i40e_pf_disable_irq0(hw);
5784
5785         /* read out interrupt causes */
5786         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5787
5788         /* No interrupt event indicated */
5789         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5790                 PMD_DRV_LOG(INFO, "No interrupt event");
5791                 goto done;
5792         }
5793 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5794         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5795                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5796         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5797                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5798         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5799                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5800         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5801                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5802         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5803                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5804         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5805                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5806         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5807                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5808 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5809
5810         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5811                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5812                 i40e_dev_handle_vfr_event(dev);
5813         }
5814         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5815                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5816                 i40e_dev_handle_aq_msg(dev);
5817         }
5818
5819 done:
5820         /* Enable interrupt */
5821         i40e_pf_enable_irq0(hw);
5822         rte_intr_enable(intr_handle);
5823 }
5824
5825 static int
5826 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5827                          struct i40e_macvlan_filter *filter,
5828                          int total)
5829 {
5830         int ele_num, ele_buff_size;
5831         int num, actual_num, i;
5832         uint16_t flags;
5833         int ret = I40E_SUCCESS;
5834         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5835         struct i40e_aqc_add_macvlan_element_data *req_list;
5836
5837         if (filter == NULL  || total == 0)
5838                 return I40E_ERR_PARAM;
5839         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5840         ele_buff_size = hw->aq.asq_buf_size;
5841
5842         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5843         if (req_list == NULL) {
5844                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5845                 return I40E_ERR_NO_MEMORY;
5846         }
5847
5848         num = 0;
5849         do {
5850                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5851                 memset(req_list, 0, ele_buff_size);
5852
5853                 for (i = 0; i < actual_num; i++) {
5854                         (void)rte_memcpy(req_list[i].mac_addr,
5855                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5856                         req_list[i].vlan_tag =
5857                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5858
5859                         switch (filter[num + i].filter_type) {
5860                         case RTE_MAC_PERFECT_MATCH:
5861                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5862                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5863                                 break;
5864                         case RTE_MACVLAN_PERFECT_MATCH:
5865                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5866                                 break;
5867                         case RTE_MAC_HASH_MATCH:
5868                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5869                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5870                                 break;
5871                         case RTE_MACVLAN_HASH_MATCH:
5872                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5873                                 break;
5874                         default:
5875                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5876                                 ret = I40E_ERR_PARAM;
5877                                 goto DONE;
5878                         }
5879
5880                         req_list[i].queue_number = 0;
5881
5882                         req_list[i].flags = rte_cpu_to_le_16(flags);
5883                 }
5884
5885                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5886                                                 actual_num, NULL);
5887                 if (ret != I40E_SUCCESS) {
5888                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5889                         goto DONE;
5890                 }
5891                 num += actual_num;
5892         } while (num < total);
5893
5894 DONE:
5895         rte_free(req_list);
5896         return ret;
5897 }
5898
5899 static int
5900 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5901                             struct i40e_macvlan_filter *filter,
5902                             int total)
5903 {
5904         int ele_num, ele_buff_size;
5905         int num, actual_num, i;
5906         uint16_t flags;
5907         int ret = I40E_SUCCESS;
5908         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5909         struct i40e_aqc_remove_macvlan_element_data *req_list;
5910
5911         if (filter == NULL  || total == 0)
5912                 return I40E_ERR_PARAM;
5913
5914         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5915         ele_buff_size = hw->aq.asq_buf_size;
5916
5917         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5918         if (req_list == NULL) {
5919                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5920                 return I40E_ERR_NO_MEMORY;
5921         }
5922
5923         num = 0;
5924         do {
5925                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5926                 memset(req_list, 0, ele_buff_size);
5927
5928                 for (i = 0; i < actual_num; i++) {
5929                         (void)rte_memcpy(req_list[i].mac_addr,
5930                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5931                         req_list[i].vlan_tag =
5932                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5933
5934                         switch (filter[num + i].filter_type) {
5935                         case RTE_MAC_PERFECT_MATCH:
5936                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5937                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5938                                 break;
5939                         case RTE_MACVLAN_PERFECT_MATCH:
5940                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5941                                 break;
5942                         case RTE_MAC_HASH_MATCH:
5943                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5944                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5945                                 break;
5946                         case RTE_MACVLAN_HASH_MATCH:
5947                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5948                                 break;
5949                         default:
5950                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5951                                 ret = I40E_ERR_PARAM;
5952                                 goto DONE;
5953                         }
5954                         req_list[i].flags = rte_cpu_to_le_16(flags);
5955                 }
5956
5957                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5958                                                 actual_num, NULL);
5959                 if (ret != I40E_SUCCESS) {
5960                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5961                         goto DONE;
5962                 }
5963                 num += actual_num;
5964         } while (num < total);
5965
5966 DONE:
5967         rte_free(req_list);
5968         return ret;
5969 }
5970
5971 /* Find out specific MAC filter */
5972 static struct i40e_mac_filter *
5973 i40e_find_mac_filter(struct i40e_vsi *vsi,
5974                          struct ether_addr *macaddr)
5975 {
5976         struct i40e_mac_filter *f;
5977
5978         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5979                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5980                         return f;
5981         }
5982
5983         return NULL;
5984 }
5985
5986 static bool
5987 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5988                          uint16_t vlan_id)
5989 {
5990         uint32_t vid_idx, vid_bit;
5991
5992         if (vlan_id > ETH_VLAN_ID_MAX)
5993                 return 0;
5994
5995         vid_idx = I40E_VFTA_IDX(vlan_id);
5996         vid_bit = I40E_VFTA_BIT(vlan_id);
5997
5998         if (vsi->vfta[vid_idx] & vid_bit)
5999                 return 1;
6000         else
6001                 return 0;
6002 }
6003
6004 static void
6005 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6006                        uint16_t vlan_id, bool on)
6007 {
6008         uint32_t vid_idx, vid_bit;
6009
6010         vid_idx = I40E_VFTA_IDX(vlan_id);
6011         vid_bit = I40E_VFTA_BIT(vlan_id);
6012
6013         if (on)
6014                 vsi->vfta[vid_idx] |= vid_bit;
6015         else
6016                 vsi->vfta[vid_idx] &= ~vid_bit;
6017 }
6018
6019 static void
6020 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6021                      uint16_t vlan_id, bool on)
6022 {
6023         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6024         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6025         int ret;
6026
6027         if (vlan_id > ETH_VLAN_ID_MAX)
6028                 return;
6029
6030         i40e_store_vlan_filter(vsi, vlan_id, on);
6031
6032         if (!vsi->vlan_anti_spoof_on || !vlan_id)
6033                 return;
6034
6035         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6036
6037         if (on) {
6038                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6039                                        &vlan_data, 1, NULL);
6040                 if (ret != I40E_SUCCESS)
6041                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6042         } else {
6043                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6044                                           &vlan_data, 1, NULL);
6045                 if (ret != I40E_SUCCESS)
6046                         PMD_DRV_LOG(ERR,
6047                                     "Failed to remove vlan filter");
6048         }
6049 }
6050
6051 /**
6052  * Find all vlan options for specific mac addr,
6053  * return with actual vlan found.
6054  */
6055 static inline int
6056 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6057                            struct i40e_macvlan_filter *mv_f,
6058                            int num, struct ether_addr *addr)
6059 {
6060         int i;
6061         uint32_t j, k;
6062
6063         /**
6064          * Not to use i40e_find_vlan_filter to decrease the loop time,
6065          * although the code looks complex.
6066           */
6067         if (num < vsi->vlan_num)
6068                 return I40E_ERR_PARAM;
6069
6070         i = 0;
6071         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6072                 if (vsi->vfta[j]) {
6073                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6074                                 if (vsi->vfta[j] & (1 << k)) {
6075                                         if (i > num - 1) {
6076                                                 PMD_DRV_LOG(ERR,
6077                                                         "vlan number doesn't match");
6078                                                 return I40E_ERR_PARAM;
6079                                         }
6080                                         (void)rte_memcpy(&mv_f[i].macaddr,
6081                                                         addr, ETH_ADDR_LEN);
6082                                         mv_f[i].vlan_id =
6083                                                 j * I40E_UINT32_BIT_SIZE + k;
6084                                         i++;
6085                                 }
6086                         }
6087                 }
6088         }
6089         return I40E_SUCCESS;
6090 }
6091
6092 static inline int
6093 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6094                            struct i40e_macvlan_filter *mv_f,
6095                            int num,
6096                            uint16_t vlan)
6097 {
6098         int i = 0;
6099         struct i40e_mac_filter *f;
6100
6101         if (num < vsi->mac_num)
6102                 return I40E_ERR_PARAM;
6103
6104         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6105                 if (i > num - 1) {
6106                         PMD_DRV_LOG(ERR, "buffer number not match");
6107                         return I40E_ERR_PARAM;
6108                 }
6109                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6110                                 ETH_ADDR_LEN);
6111                 mv_f[i].vlan_id = vlan;
6112                 mv_f[i].filter_type = f->mac_info.filter_type;
6113                 i++;
6114         }
6115
6116         return I40E_SUCCESS;
6117 }
6118
6119 static int
6120 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6121 {
6122         int i, j, num;
6123         struct i40e_mac_filter *f;
6124         struct i40e_macvlan_filter *mv_f;
6125         int ret = I40E_SUCCESS;
6126
6127         if (vsi == NULL || vsi->mac_num == 0)
6128                 return I40E_ERR_PARAM;
6129
6130         /* Case that no vlan is set */
6131         if (vsi->vlan_num == 0)
6132                 num = vsi->mac_num;
6133         else
6134                 num = vsi->mac_num * vsi->vlan_num;
6135
6136         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6137         if (mv_f == NULL) {
6138                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6139                 return I40E_ERR_NO_MEMORY;
6140         }
6141
6142         i = 0;
6143         if (vsi->vlan_num == 0) {
6144                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6145                         (void)rte_memcpy(&mv_f[i].macaddr,
6146                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6147                         mv_f[i].filter_type = f->mac_info.filter_type;
6148                         mv_f[i].vlan_id = 0;
6149                         i++;
6150                 }
6151         } else {
6152                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6153                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6154                                         vsi->vlan_num, &f->mac_info.mac_addr);
6155                         if (ret != I40E_SUCCESS)
6156                                 goto DONE;
6157                         for (j = i; j < i + vsi->vlan_num; j++)
6158                                 mv_f[j].filter_type = f->mac_info.filter_type;
6159                         i += vsi->vlan_num;
6160                 }
6161         }
6162
6163         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6164 DONE:
6165         rte_free(mv_f);
6166
6167         return ret;
6168 }
6169
6170 int
6171 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6172 {
6173         struct i40e_macvlan_filter *mv_f;
6174         int mac_num;
6175         int ret = I40E_SUCCESS;
6176
6177         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6178                 return I40E_ERR_PARAM;
6179
6180         /* If it's already set, just return */
6181         if (i40e_find_vlan_filter(vsi,vlan))
6182                 return I40E_SUCCESS;
6183
6184         mac_num = vsi->mac_num;
6185
6186         if (mac_num == 0) {
6187                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6188                 return I40E_ERR_PARAM;
6189         }
6190
6191         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6192
6193         if (mv_f == NULL) {
6194                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6195                 return I40E_ERR_NO_MEMORY;
6196         }
6197
6198         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6199
6200         if (ret != I40E_SUCCESS)
6201                 goto DONE;
6202
6203         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6204
6205         if (ret != I40E_SUCCESS)
6206                 goto DONE;
6207
6208         i40e_set_vlan_filter(vsi, vlan, 1);
6209
6210         vsi->vlan_num++;
6211         ret = I40E_SUCCESS;
6212 DONE:
6213         rte_free(mv_f);
6214         return ret;
6215 }
6216
6217 int
6218 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6219 {
6220         struct i40e_macvlan_filter *mv_f;
6221         int mac_num;
6222         int ret = I40E_SUCCESS;
6223
6224         /**
6225          * Vlan 0 is the generic filter for untagged packets
6226          * and can't be removed.
6227          */
6228         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6229                 return I40E_ERR_PARAM;
6230
6231         /* If can't find it, just return */
6232         if (!i40e_find_vlan_filter(vsi, vlan))
6233                 return I40E_ERR_PARAM;
6234
6235         mac_num = vsi->mac_num;
6236
6237         if (mac_num == 0) {
6238                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6239                 return I40E_ERR_PARAM;
6240         }
6241
6242         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6243
6244         if (mv_f == NULL) {
6245                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6246                 return I40E_ERR_NO_MEMORY;
6247         }
6248
6249         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6250
6251         if (ret != I40E_SUCCESS)
6252                 goto DONE;
6253
6254         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6255
6256         if (ret != I40E_SUCCESS)
6257                 goto DONE;
6258
6259         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6260         if (vsi->vlan_num == 1) {
6261                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6262                 if (ret != I40E_SUCCESS)
6263                         goto DONE;
6264
6265                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6266                 if (ret != I40E_SUCCESS)
6267                         goto DONE;
6268         }
6269
6270         i40e_set_vlan_filter(vsi, vlan, 0);
6271
6272         vsi->vlan_num--;
6273         ret = I40E_SUCCESS;
6274 DONE:
6275         rte_free(mv_f);
6276         return ret;
6277 }
6278
6279 int
6280 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6281 {
6282         struct i40e_mac_filter *f;
6283         struct i40e_macvlan_filter *mv_f;
6284         int i, vlan_num = 0;
6285         int ret = I40E_SUCCESS;
6286
6287         /* If it's add and we've config it, return */
6288         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6289         if (f != NULL)
6290                 return I40E_SUCCESS;
6291         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6292                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6293
6294                 /**
6295                  * If vlan_num is 0, that's the first time to add mac,
6296                  * set mask for vlan_id 0.
6297                  */
6298                 if (vsi->vlan_num == 0) {
6299                         i40e_set_vlan_filter(vsi, 0, 1);
6300                         vsi->vlan_num = 1;
6301                 }
6302                 vlan_num = vsi->vlan_num;
6303         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6304                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6305                 vlan_num = 1;
6306
6307         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6308         if (mv_f == NULL) {
6309                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6310                 return I40E_ERR_NO_MEMORY;
6311         }
6312
6313         for (i = 0; i < vlan_num; i++) {
6314                 mv_f[i].filter_type = mac_filter->filter_type;
6315                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6316                                 ETH_ADDR_LEN);
6317         }
6318
6319         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6320                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6321                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6322                                         &mac_filter->mac_addr);
6323                 if (ret != I40E_SUCCESS)
6324                         goto DONE;
6325         }
6326
6327         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6328         if (ret != I40E_SUCCESS)
6329                 goto DONE;
6330
6331         /* Add the mac addr into mac list */
6332         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6333         if (f == NULL) {
6334                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6335                 ret = I40E_ERR_NO_MEMORY;
6336                 goto DONE;
6337         }
6338         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6339                         ETH_ADDR_LEN);
6340         f->mac_info.filter_type = mac_filter->filter_type;
6341         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6342         vsi->mac_num++;
6343
6344         ret = I40E_SUCCESS;
6345 DONE:
6346         rte_free(mv_f);
6347
6348         return ret;
6349 }
6350
6351 int
6352 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6353 {
6354         struct i40e_mac_filter *f;
6355         struct i40e_macvlan_filter *mv_f;
6356         int i, vlan_num;
6357         enum rte_mac_filter_type filter_type;
6358         int ret = I40E_SUCCESS;
6359
6360         /* Can't find it, return an error */
6361         f = i40e_find_mac_filter(vsi, addr);
6362         if (f == NULL)
6363                 return I40E_ERR_PARAM;
6364
6365         vlan_num = vsi->vlan_num;
6366         filter_type = f->mac_info.filter_type;
6367         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6368                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6369                 if (vlan_num == 0) {
6370                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6371                         return I40E_ERR_PARAM;
6372                 }
6373         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6374                         filter_type == RTE_MAC_HASH_MATCH)
6375                 vlan_num = 1;
6376
6377         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6378         if (mv_f == NULL) {
6379                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6380                 return I40E_ERR_NO_MEMORY;
6381         }
6382
6383         for (i = 0; i < vlan_num; i++) {
6384                 mv_f[i].filter_type = filter_type;
6385                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6386                                 ETH_ADDR_LEN);
6387         }
6388         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6389                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6390                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6391                 if (ret != I40E_SUCCESS)
6392                         goto DONE;
6393         }
6394
6395         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6396         if (ret != I40E_SUCCESS)
6397                 goto DONE;
6398
6399         /* Remove the mac addr into mac list */
6400         TAILQ_REMOVE(&vsi->mac_list, f, next);
6401         rte_free(f);
6402         vsi->mac_num--;
6403
6404         ret = I40E_SUCCESS;
6405 DONE:
6406         rte_free(mv_f);
6407         return ret;
6408 }
6409
6410 /* Configure hash enable flags for RSS */
6411 uint64_t
6412 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6413 {
6414         uint64_t hena = 0;
6415
6416         if (!flags)
6417                 return hena;
6418
6419         if (flags & ETH_RSS_FRAG_IPV4)
6420                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6421         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6422                 if (type == I40E_MAC_X722) {
6423                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6424                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6425                 } else
6426                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6427         }
6428         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6429                 if (type == I40E_MAC_X722) {
6430                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6431                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6432                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6433                 } else
6434                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6435         }
6436         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6437                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6438         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6439                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6440         if (flags & ETH_RSS_FRAG_IPV6)
6441                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6442         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6443                 if (type == I40E_MAC_X722) {
6444                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6445                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6446                 } else
6447                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6448         }
6449         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6450                 if (type == I40E_MAC_X722) {
6451                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6452                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6453                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6454                 } else
6455                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6456         }
6457         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6458                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6459         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6460                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6461         if (flags & ETH_RSS_L2_PAYLOAD)
6462                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6463
6464         return hena;
6465 }
6466
6467 /* Parse the hash enable flags */
6468 uint64_t
6469 i40e_parse_hena(uint64_t flags)
6470 {
6471         uint64_t rss_hf = 0;
6472
6473         if (!flags)
6474                 return rss_hf;
6475         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6476                 rss_hf |= ETH_RSS_FRAG_IPV4;
6477         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6478                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6479         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6480                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6481         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6482                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6483         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6484                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6485         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6486                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6487         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6488                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6489         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6490                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6491         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6492                 rss_hf |= ETH_RSS_FRAG_IPV6;
6493         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6494                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6495         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6496                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6497         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6498                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6499         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6500                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6501         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6502                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6506                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6507         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6508                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6509
6510         return rss_hf;
6511 }
6512
6513 /* Disable RSS */
6514 static void
6515 i40e_pf_disable_rss(struct i40e_pf *pf)
6516 {
6517         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6518         uint64_t hena;
6519
6520         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6521         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6522         if (hw->mac.type == I40E_MAC_X722)
6523                 hena &= ~I40E_RSS_HENA_ALL_X722;
6524         else
6525                 hena &= ~I40E_RSS_HENA_ALL;
6526         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6527         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6528         I40E_WRITE_FLUSH(hw);
6529 }
6530
6531 static int
6532 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6533 {
6534         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6535         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6536         int ret = 0;
6537
6538         if (!key || key_len == 0) {
6539                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6540                 return 0;
6541         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6542                 sizeof(uint32_t)) {
6543                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6544                 return -EINVAL;
6545         }
6546
6547         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6548                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6549                         (struct i40e_aqc_get_set_rss_key_data *)key;
6550
6551                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6552                 if (ret)
6553                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6554         } else {
6555                 uint32_t *hash_key = (uint32_t *)key;
6556                 uint16_t i;
6557
6558                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6559                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6560                 I40E_WRITE_FLUSH(hw);
6561         }
6562
6563         return ret;
6564 }
6565
6566 static int
6567 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6568 {
6569         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6570         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6571         int ret;
6572
6573         if (!key || !key_len)
6574                 return -EINVAL;
6575
6576         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6577                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6578                         (struct i40e_aqc_get_set_rss_key_data *)key);
6579                 if (ret) {
6580                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6581                         return ret;
6582                 }
6583         } else {
6584                 uint32_t *key_dw = (uint32_t *)key;
6585                 uint16_t i;
6586
6587                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6588                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6589         }
6590         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6591
6592         return 0;
6593 }
6594
6595 static int
6596 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6597 {
6598         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6599         uint64_t rss_hf;
6600         uint64_t hena;
6601         int ret;
6602
6603         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6604                                rss_conf->rss_key_len);
6605         if (ret)
6606                 return ret;
6607
6608         rss_hf = rss_conf->rss_hf;
6609         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6610         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6611         if (hw->mac.type == I40E_MAC_X722)
6612                 hena &= ~I40E_RSS_HENA_ALL_X722;
6613         else
6614                 hena &= ~I40E_RSS_HENA_ALL;
6615         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6616         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6617         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6618         I40E_WRITE_FLUSH(hw);
6619
6620         return 0;
6621 }
6622
6623 static int
6624 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6625                          struct rte_eth_rss_conf *rss_conf)
6626 {
6627         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6629         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6630         uint64_t hena;
6631
6632         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6633         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6634         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6635                  ? I40E_RSS_HENA_ALL_X722
6636                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6637                 if (rss_hf != 0) /* Enable RSS */
6638                         return -EINVAL;
6639                 return 0; /* Nothing to do */
6640         }
6641         /* RSS enabled */
6642         if (rss_hf == 0) /* Disable RSS */
6643                 return -EINVAL;
6644
6645         return i40e_hw_rss_hash_set(pf, rss_conf);
6646 }
6647
6648 static int
6649 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6650                            struct rte_eth_rss_conf *rss_conf)
6651 {
6652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6654         uint64_t hena;
6655
6656         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6657                          &rss_conf->rss_key_len);
6658
6659         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6660         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6661         rss_conf->rss_hf = i40e_parse_hena(hena);
6662
6663         return 0;
6664 }
6665
6666 static int
6667 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6668 {
6669         switch (filter_type) {
6670         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6671                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6672                 break;
6673         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6674                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6675                 break;
6676         case RTE_TUNNEL_FILTER_IMAC_TENID:
6677                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6678                 break;
6679         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6680                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6681                 break;
6682         case ETH_TUNNEL_FILTER_IMAC:
6683                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6684                 break;
6685         case ETH_TUNNEL_FILTER_OIP:
6686                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6687                 break;
6688         case ETH_TUNNEL_FILTER_IIP:
6689                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6690                 break;
6691         default:
6692                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6693                 return -EINVAL;
6694         }
6695
6696         return 0;
6697 }
6698
6699 /* Convert tunnel filter structure */
6700 static int
6701 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6702                            *cld_filter,
6703                            struct i40e_tunnel_filter *tunnel_filter)
6704 {
6705         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6706                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6707         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6708                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6709         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6710         if ((rte_le_to_cpu_16(cld_filter->flags) &
6711              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6712             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6713                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6714         else
6715                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6716         tunnel_filter->input.flags = cld_filter->flags;
6717         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6718         tunnel_filter->queue = cld_filter->queue_number;
6719
6720         return 0;
6721 }
6722
6723 /* Check if there exists the tunnel filter */
6724 struct i40e_tunnel_filter *
6725 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6726                              const struct i40e_tunnel_filter_input *input)
6727 {
6728         int ret;
6729
6730         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6731         if (ret < 0)
6732                 return NULL;
6733
6734         return tunnel_rule->hash_map[ret];
6735 }
6736
6737 /* Add a tunnel filter into the SW list */
6738 static int
6739 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6740                              struct i40e_tunnel_filter *tunnel_filter)
6741 {
6742         struct i40e_tunnel_rule *rule = &pf->tunnel;
6743         int ret;
6744
6745         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6746         if (ret < 0) {
6747                 PMD_DRV_LOG(ERR,
6748                             "Failed to insert tunnel filter to hash table %d!",
6749                             ret);
6750                 return ret;
6751         }
6752         rule->hash_map[ret] = tunnel_filter;
6753
6754         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6755
6756         return 0;
6757 }
6758
6759 /* Delete a tunnel filter from the SW list */
6760 int
6761 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6762                           struct i40e_tunnel_filter_input *input)
6763 {
6764         struct i40e_tunnel_rule *rule = &pf->tunnel;
6765         struct i40e_tunnel_filter *tunnel_filter;
6766         int ret;
6767
6768         ret = rte_hash_del_key(rule->hash_table, input);
6769         if (ret < 0) {
6770                 PMD_DRV_LOG(ERR,
6771                             "Failed to delete tunnel filter to hash table %d!",
6772                             ret);
6773                 return ret;
6774         }
6775         tunnel_filter = rule->hash_map[ret];
6776         rule->hash_map[ret] = NULL;
6777
6778         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6779         rte_free(tunnel_filter);
6780
6781         return 0;
6782 }
6783
6784 int
6785 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6786                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6787                         uint8_t add)
6788 {
6789         uint16_t ip_type;
6790         uint32_t ipv4_addr;
6791         uint8_t i, tun_type = 0;
6792         /* internal varialbe to convert ipv6 byte order */
6793         uint32_t convert_ipv6[4];
6794         int val, ret = 0;
6795         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6796         struct i40e_vsi *vsi = pf->main_vsi;
6797         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6798         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6799         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6800         struct i40e_tunnel_filter *tunnel, *node;
6801         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6802
6803         cld_filter = rte_zmalloc("tunnel_filter",
6804                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6805                 0);
6806
6807         if (NULL == cld_filter) {
6808                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6809                 return -EINVAL;
6810         }
6811         pfilter = cld_filter;
6812
6813         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6814         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6815
6816         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6817         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6818                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6819                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6820                 rte_memcpy(&pfilter->ipaddr.v4.data,
6821                                 &rte_cpu_to_le_32(ipv4_addr),
6822                                 sizeof(pfilter->ipaddr.v4.data));
6823         } else {
6824                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6825                 for (i = 0; i < 4; i++) {
6826                         convert_ipv6[i] =
6827                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6828                 }
6829                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6830                                 sizeof(pfilter->ipaddr.v6.data));
6831         }
6832
6833         /* check tunneled type */
6834         switch (tunnel_filter->tunnel_type) {
6835         case RTE_TUNNEL_TYPE_VXLAN:
6836                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6837                 break;
6838         case RTE_TUNNEL_TYPE_NVGRE:
6839                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6840                 break;
6841         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6842                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6843                 break;
6844         default:
6845                 /* Other tunnel types is not supported. */
6846                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6847                 rte_free(cld_filter);
6848                 return -EINVAL;
6849         }
6850
6851         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6852                                                 &pfilter->flags);
6853         if (val < 0) {
6854                 rte_free(cld_filter);
6855                 return -EINVAL;
6856         }
6857
6858         pfilter->flags |= rte_cpu_to_le_16(
6859                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6860                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6861         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6862         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6863
6864         /* Check if there is the filter in SW list */
6865         memset(&check_filter, 0, sizeof(check_filter));
6866         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6867         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6868         if (add && node) {
6869                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6870                 return -EINVAL;
6871         }
6872
6873         if (!add && !node) {
6874                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6875                 return -EINVAL;
6876         }
6877
6878         if (add) {
6879                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6880                 if (ret < 0) {
6881                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6882                         return ret;
6883                 }
6884                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6885                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6886                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6887         } else {
6888                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6889                                                    cld_filter, 1);
6890                 if (ret < 0) {
6891                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6892                         return ret;
6893                 }
6894                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6895         }
6896
6897         rte_free(cld_filter);
6898         return ret;
6899 }
6900
6901 static int
6902 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6903 {
6904         uint8_t i;
6905
6906         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6907                 if (pf->vxlan_ports[i] == port)
6908                         return i;
6909         }
6910
6911         return -1;
6912 }
6913
6914 static int
6915 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6916 {
6917         int  idx, ret;
6918         uint8_t filter_idx;
6919         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6920
6921         idx = i40e_get_vxlan_port_idx(pf, port);
6922
6923         /* Check if port already exists */
6924         if (idx >= 0) {
6925                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6926                 return -EINVAL;
6927         }
6928
6929         /* Now check if there is space to add the new port */
6930         idx = i40e_get_vxlan_port_idx(pf, 0);
6931         if (idx < 0) {
6932                 PMD_DRV_LOG(ERR,
6933                         "Maximum number of UDP ports reached, not adding port %d",
6934                         port);
6935                 return -ENOSPC;
6936         }
6937
6938         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6939                                         &filter_idx, NULL);
6940         if (ret < 0) {
6941                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6942                 return -1;
6943         }
6944
6945         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6946                          port,  filter_idx);
6947
6948         /* New port: add it and mark its index in the bitmap */
6949         pf->vxlan_ports[idx] = port;
6950         pf->vxlan_bitmap |= (1 << idx);
6951
6952         if (!(pf->flags & I40E_FLAG_VXLAN))
6953                 pf->flags |= I40E_FLAG_VXLAN;
6954
6955         return 0;
6956 }
6957
6958 static int
6959 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6960 {
6961         int idx;
6962         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6963
6964         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6965                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6966                 return -EINVAL;
6967         }
6968
6969         idx = i40e_get_vxlan_port_idx(pf, port);
6970
6971         if (idx < 0) {
6972                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6973                 return -EINVAL;
6974         }
6975
6976         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6977                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6978                 return -1;
6979         }
6980
6981         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6982                         port, idx);
6983
6984         pf->vxlan_ports[idx] = 0;
6985         pf->vxlan_bitmap &= ~(1 << idx);
6986
6987         if (!pf->vxlan_bitmap)
6988                 pf->flags &= ~I40E_FLAG_VXLAN;
6989
6990         return 0;
6991 }
6992
6993 /* Add UDP tunneling port */
6994 static int
6995 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6996                              struct rte_eth_udp_tunnel *udp_tunnel)
6997 {
6998         int ret = 0;
6999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7000
7001         if (udp_tunnel == NULL)
7002                 return -EINVAL;
7003
7004         switch (udp_tunnel->prot_type) {
7005         case RTE_TUNNEL_TYPE_VXLAN:
7006                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7007                 break;
7008
7009         case RTE_TUNNEL_TYPE_GENEVE:
7010         case RTE_TUNNEL_TYPE_TEREDO:
7011                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7012                 ret = -1;
7013                 break;
7014
7015         default:
7016                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7017                 ret = -1;
7018                 break;
7019         }
7020
7021         return ret;
7022 }
7023
7024 /* Remove UDP tunneling port */
7025 static int
7026 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7027                              struct rte_eth_udp_tunnel *udp_tunnel)
7028 {
7029         int ret = 0;
7030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7031
7032         if (udp_tunnel == NULL)
7033                 return -EINVAL;
7034
7035         switch (udp_tunnel->prot_type) {
7036         case RTE_TUNNEL_TYPE_VXLAN:
7037                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7038                 break;
7039         case RTE_TUNNEL_TYPE_GENEVE:
7040         case RTE_TUNNEL_TYPE_TEREDO:
7041                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7042                 ret = -1;
7043                 break;
7044         default:
7045                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7046                 ret = -1;
7047                 break;
7048         }
7049
7050         return ret;
7051 }
7052
7053 /* Calculate the maximum number of contiguous PF queues that are configured */
7054 static int
7055 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7056 {
7057         struct rte_eth_dev_data *data = pf->dev_data;
7058         int i, num;
7059         struct i40e_rx_queue *rxq;
7060
7061         num = 0;
7062         for (i = 0; i < pf->lan_nb_qps; i++) {
7063                 rxq = data->rx_queues[i];
7064                 if (rxq && rxq->q_set)
7065                         num++;
7066                 else
7067                         break;
7068         }
7069
7070         return num;
7071 }
7072
7073 /* Configure RSS */
7074 static int
7075 i40e_pf_config_rss(struct i40e_pf *pf)
7076 {
7077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7078         struct rte_eth_rss_conf rss_conf;
7079         uint32_t i, lut = 0;
7080         uint16_t j, num;
7081
7082         /*
7083          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7084          * It's necessary to calulate the actual PF queues that are configured.
7085          */
7086         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7087                 num = i40e_pf_calc_configured_queues_num(pf);
7088         else
7089                 num = pf->dev_data->nb_rx_queues;
7090
7091         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7092         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7093                         num);
7094
7095         if (num == 0) {
7096                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7097                 return -ENOTSUP;
7098         }
7099
7100         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7101                 if (j == num)
7102                         j = 0;
7103                 lut = (lut << 8) | (j & ((0x1 <<
7104                         hw->func_caps.rss_table_entry_width) - 1));
7105                 if ((i & 3) == 3)
7106                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7107         }
7108
7109         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7110         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7111                 i40e_pf_disable_rss(pf);
7112                 return 0;
7113         }
7114         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7115                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7116                 /* Random default keys */
7117                 static uint32_t rss_key_default[] = {0x6b793944,
7118                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7119                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7120                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7121
7122                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7123                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7124                                                         sizeof(uint32_t);
7125         }
7126
7127         return i40e_hw_rss_hash_set(pf, &rss_conf);
7128 }
7129
7130 static int
7131 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7132                                struct rte_eth_tunnel_filter_conf *filter)
7133 {
7134         if (pf == NULL || filter == NULL) {
7135                 PMD_DRV_LOG(ERR, "Invalid parameter");
7136                 return -EINVAL;
7137         }
7138
7139         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7140                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7141                 return -EINVAL;
7142         }
7143
7144         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7145                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7146                 return -EINVAL;
7147         }
7148
7149         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7150                 (is_zero_ether_addr(&filter->outer_mac))) {
7151                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7152                 return -EINVAL;
7153         }
7154
7155         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7156                 (is_zero_ether_addr(&filter->inner_mac))) {
7157                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7158                 return -EINVAL;
7159         }
7160
7161         return 0;
7162 }
7163
7164 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7165 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7166 static int
7167 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7168 {
7169         uint32_t val, reg;
7170         int ret = -EINVAL;
7171
7172         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7173         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7174
7175         if (len == 3) {
7176                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7177         } else if (len == 4) {
7178                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7179         } else {
7180                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7181                 return ret;
7182         }
7183
7184         if (reg != val) {
7185                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7186                                                    reg, NULL);
7187                 if (ret != 0)
7188                         return ret;
7189         } else {
7190                 ret = 0;
7191         }
7192         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7193                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7194
7195         return ret;
7196 }
7197
7198 static int
7199 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7200 {
7201         int ret = -EINVAL;
7202
7203         if (!hw || !cfg)
7204                 return -EINVAL;
7205
7206         switch (cfg->cfg_type) {
7207         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7208                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7209                 break;
7210         default:
7211                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7212                 break;
7213         }
7214
7215         return ret;
7216 }
7217
7218 static int
7219 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7220                                enum rte_filter_op filter_op,
7221                                void *arg)
7222 {
7223         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224         int ret = I40E_ERR_PARAM;
7225
7226         switch (filter_op) {
7227         case RTE_ETH_FILTER_SET:
7228                 ret = i40e_dev_global_config_set(hw,
7229                         (struct rte_eth_global_cfg *)arg);
7230                 break;
7231         default:
7232                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7233                 break;
7234         }
7235
7236         return ret;
7237 }
7238
7239 static int
7240 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7241                           enum rte_filter_op filter_op,
7242                           void *arg)
7243 {
7244         struct rte_eth_tunnel_filter_conf *filter;
7245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7246         int ret = I40E_SUCCESS;
7247
7248         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7249
7250         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7251                 return I40E_ERR_PARAM;
7252
7253         switch (filter_op) {
7254         case RTE_ETH_FILTER_NOP:
7255                 if (!(pf->flags & I40E_FLAG_VXLAN))
7256                         ret = I40E_NOT_SUPPORTED;
7257                 break;
7258         case RTE_ETH_FILTER_ADD:
7259                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7260                 break;
7261         case RTE_ETH_FILTER_DELETE:
7262                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7263                 break;
7264         default:
7265                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7266                 ret = I40E_ERR_PARAM;
7267                 break;
7268         }
7269
7270         return ret;
7271 }
7272
7273 static int
7274 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7275 {
7276         int ret = 0;
7277         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7278
7279         /* RSS setup */
7280         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7281                 ret = i40e_pf_config_rss(pf);
7282         else
7283                 i40e_pf_disable_rss(pf);
7284
7285         return ret;
7286 }
7287
7288 /* Get the symmetric hash enable configurations per port */
7289 static void
7290 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7291 {
7292         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7293
7294         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7295 }
7296
7297 /* Set the symmetric hash enable configurations per port */
7298 static void
7299 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7300 {
7301         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7302
7303         if (enable > 0) {
7304                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7305                         PMD_DRV_LOG(INFO,
7306                                 "Symmetric hash has already been enabled");
7307                         return;
7308                 }
7309                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7310         } else {
7311                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7312                         PMD_DRV_LOG(INFO,
7313                                 "Symmetric hash has already been disabled");
7314                         return;
7315                 }
7316                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7317         }
7318         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7319         I40E_WRITE_FLUSH(hw);
7320 }
7321
7322 /*
7323  * Get global configurations of hash function type and symmetric hash enable
7324  * per flow type (pctype). Note that global configuration means it affects all
7325  * the ports on the same NIC.
7326  */
7327 static int
7328 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7329                                    struct rte_eth_hash_global_conf *g_cfg)
7330 {
7331         uint32_t reg, mask = I40E_FLOW_TYPES;
7332         uint16_t i;
7333         enum i40e_filter_pctype pctype;
7334
7335         memset(g_cfg, 0, sizeof(*g_cfg));
7336         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7337         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7338                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7339         else
7340                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7341         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7342                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7343
7344         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7345                 if (!(mask & (1UL << i)))
7346                         continue;
7347                 mask &= ~(1UL << i);
7348                 /* Bit set indicats the coresponding flow type is supported */
7349                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7350                 /* if flowtype is invalid, continue */
7351                 if (!I40E_VALID_FLOW(i))
7352                         continue;
7353                 pctype = i40e_flowtype_to_pctype(i);
7354                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7355                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7356                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7357         }
7358
7359         return 0;
7360 }
7361
7362 static int
7363 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7364 {
7365         uint32_t i;
7366         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7367
7368         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7369                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7370                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7371                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7372                                                 g_cfg->hash_func);
7373                 return -EINVAL;
7374         }
7375
7376         /*
7377          * As i40e supports less than 32 flow types, only first 32 bits need to
7378          * be checked.
7379          */
7380         mask0 = g_cfg->valid_bit_mask[0];
7381         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7382                 if (i == 0) {
7383                         /* Check if any unsupported flow type configured */
7384                         if ((mask0 | i40e_mask) ^ i40e_mask)
7385                                 goto mask_err;
7386                 } else {
7387                         if (g_cfg->valid_bit_mask[i])
7388                                 goto mask_err;
7389                 }
7390         }
7391
7392         return 0;
7393
7394 mask_err:
7395         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7396
7397         return -EINVAL;
7398 }
7399
7400 /*
7401  * Set global configurations of hash function type and symmetric hash enable
7402  * per flow type (pctype). Note any modifying global configuration will affect
7403  * all the ports on the same NIC.
7404  */
7405 static int
7406 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7407                                    struct rte_eth_hash_global_conf *g_cfg)
7408 {
7409         int ret;
7410         uint16_t i;
7411         uint32_t reg;
7412         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7413         enum i40e_filter_pctype pctype;
7414
7415         /* Check the input parameters */
7416         ret = i40e_hash_global_config_check(g_cfg);
7417         if (ret < 0)
7418                 return ret;
7419
7420         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7421                 if (!(mask0 & (1UL << i)))
7422                         continue;
7423                 mask0 &= ~(1UL << i);
7424                 /* if flowtype is invalid, continue */
7425                 if (!I40E_VALID_FLOW(i))
7426                         continue;
7427                 pctype = i40e_flowtype_to_pctype(i);
7428                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7429                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7430                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7431         }
7432
7433         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7434         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7435                 /* Toeplitz */
7436                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7437                         PMD_DRV_LOG(DEBUG,
7438                                 "Hash function already set to Toeplitz");
7439                         goto out;
7440                 }
7441                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7442         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7443                 /* Simple XOR */
7444                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7445                         PMD_DRV_LOG(DEBUG,
7446                                 "Hash function already set to Simple XOR");
7447                         goto out;
7448                 }
7449                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7450         } else
7451                 /* Use the default, and keep it as it is */
7452                 goto out;
7453
7454         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7455
7456 out:
7457         I40E_WRITE_FLUSH(hw);
7458
7459         return 0;
7460 }
7461
7462 /**
7463  * Valid input sets for hash and flow director filters per PCTYPE
7464  */
7465 static uint64_t
7466 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7467                 enum rte_filter_type filter)
7468 {
7469         uint64_t valid;
7470
7471         static const uint64_t valid_hash_inset_table[] = {
7472                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7473                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7474                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7475                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7476                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7477                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7478                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7479                         I40E_INSET_FLEX_PAYLOAD,
7480                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7481                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7482                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7483                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7484                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7485                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7486                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7487                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7488                         I40E_INSET_FLEX_PAYLOAD,
7489                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7490                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7491                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7492                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7493                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7494                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7495                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7496                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7497                         I40E_INSET_FLEX_PAYLOAD,
7498                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7499                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7500                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7501                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7502                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7503                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7504                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7505                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7506                         I40E_INSET_FLEX_PAYLOAD,
7507                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7508                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7509                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7510                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7511                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7512                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7513                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7514                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7515                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7516                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7517                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7518                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7519                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7520                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7521                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7522                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7523                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7524                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7525                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7526                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7527                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7528                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7529                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7530                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7531                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7532                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7533                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7534                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7535                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7536                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7537                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7538                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7539                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7540                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7541                         I40E_INSET_FLEX_PAYLOAD,
7542                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7543                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7544                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7545                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7546                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7547                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7548                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7549                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7550                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7551                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7552                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7553                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7554                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7555                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7556                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7557                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7558                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7559                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7560                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7561                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7562                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7563                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7564                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7565                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7566                         I40E_INSET_FLEX_PAYLOAD,
7567                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7568                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7569                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7570                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7571                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7572                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7573                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7574                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7575                         I40E_INSET_FLEX_PAYLOAD,
7576                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7577                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7578                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7579                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7580                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7581                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7582                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7583                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7584                         I40E_INSET_FLEX_PAYLOAD,
7585                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7586                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7587                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7588                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7589                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7590                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7591                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7592                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7593                         I40E_INSET_FLEX_PAYLOAD,
7594                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7595                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7596                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7597                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7598                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7599                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7600                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7601                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7602                         I40E_INSET_FLEX_PAYLOAD,
7603                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7604                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7605                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7606                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7607                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7608                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7609                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7610                         I40E_INSET_FLEX_PAYLOAD,
7611                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7612                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7613                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7614                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7615                         I40E_INSET_FLEX_PAYLOAD,
7616         };
7617
7618         /**
7619          * Flow director supports only fields defined in
7620          * union rte_eth_fdir_flow.
7621          */
7622         static const uint64_t valid_fdir_inset_table[] = {
7623                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7624                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7625                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7626                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7627                 I40E_INSET_IPV4_TTL,
7628                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7629                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7630                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7631                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7632                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7633                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7634                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7635                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7636                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7637                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7638                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7639                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7640                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7641                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7642                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7643                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7644                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7645                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7646                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7647                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7648                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7649                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7650                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7651                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7652                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7653                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7654                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7655                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7656                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7657                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7658                 I40E_INSET_SCTP_VT,
7659                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7660                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7661                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7662                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7663                 I40E_INSET_IPV4_TTL,
7664                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7665                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7666                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7667                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7668                 I40E_INSET_IPV6_HOP_LIMIT,
7669                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7670                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7671                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7672                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7673                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7674                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7675                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7676                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7677                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7678                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7679                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7680                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7681                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7682                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7683                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7684                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7685                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7686                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7687                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7688                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7689                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7690                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7691                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7692                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7693                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7694                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7695                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7696                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7697                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7698                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7699                 I40E_INSET_SCTP_VT,
7700                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7701                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7702                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7703                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7704                 I40E_INSET_IPV6_HOP_LIMIT,
7705                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7706                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7707                 I40E_INSET_LAST_ETHER_TYPE,
7708         };
7709
7710         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7711                 return 0;
7712         if (filter == RTE_ETH_FILTER_HASH)
7713                 valid = valid_hash_inset_table[pctype];
7714         else
7715                 valid = valid_fdir_inset_table[pctype];
7716
7717         return valid;
7718 }
7719
7720 /**
7721  * Validate if the input set is allowed for a specific PCTYPE
7722  */
7723 static int
7724 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7725                 enum rte_filter_type filter, uint64_t inset)
7726 {
7727         uint64_t valid;
7728
7729         valid = i40e_get_valid_input_set(pctype, filter);
7730         if (inset & (~valid))
7731                 return -EINVAL;
7732
7733         return 0;
7734 }
7735
7736 /* default input set fields combination per pctype */
7737 uint64_t
7738 i40e_get_default_input_set(uint16_t pctype)
7739 {
7740         static const uint64_t default_inset_table[] = {
7741                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7742                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7743                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7744                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7745                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7746                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7747                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7748                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7749                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7750                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7751                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7752                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7753                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7754                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7755                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7756                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7757                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7758                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7759                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7760                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7761                         I40E_INSET_SCTP_VT,
7762                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7763                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7764                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7765                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7766                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7767                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7768                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7769                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7770                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7771                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7772                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7773                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7774                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7775                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7776                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7777                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7778                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7779                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7780                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7781                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7782                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7783                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7784                         I40E_INSET_SCTP_VT,
7785                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7786                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7787                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7788                         I40E_INSET_LAST_ETHER_TYPE,
7789         };
7790
7791         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7792                 return 0;
7793
7794         return default_inset_table[pctype];
7795 }
7796
7797 /**
7798  * Parse the input set from index to logical bit masks
7799  */
7800 static int
7801 i40e_parse_input_set(uint64_t *inset,
7802                      enum i40e_filter_pctype pctype,
7803                      enum rte_eth_input_set_field *field,
7804                      uint16_t size)
7805 {
7806         uint16_t i, j;
7807         int ret = -EINVAL;
7808
7809         static const struct {
7810                 enum rte_eth_input_set_field field;
7811                 uint64_t inset;
7812         } inset_convert_table[] = {
7813                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7814                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7815                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7816                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7817                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7818                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7819                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7820                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7821                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7822                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7823                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7824                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7825                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7826                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7827                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7828                         I40E_INSET_IPV6_NEXT_HDR},
7829                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7830                         I40E_INSET_IPV6_HOP_LIMIT},
7831                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7832                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7833                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7834                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7835                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7836                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7837                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7838                         I40E_INSET_SCTP_VT},
7839                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7840                         I40E_INSET_TUNNEL_DMAC},
7841                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7842                         I40E_INSET_VLAN_TUNNEL},
7843                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7844                         I40E_INSET_TUNNEL_ID},
7845                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7846                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7847                         I40E_INSET_FLEX_PAYLOAD_W1},
7848                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7849                         I40E_INSET_FLEX_PAYLOAD_W2},
7850                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7851                         I40E_INSET_FLEX_PAYLOAD_W3},
7852                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7853                         I40E_INSET_FLEX_PAYLOAD_W4},
7854                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7855                         I40E_INSET_FLEX_PAYLOAD_W5},
7856                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7857                         I40E_INSET_FLEX_PAYLOAD_W6},
7858                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7859                         I40E_INSET_FLEX_PAYLOAD_W7},
7860                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7861                         I40E_INSET_FLEX_PAYLOAD_W8},
7862         };
7863
7864         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7865                 return ret;
7866
7867         /* Only one item allowed for default or all */
7868         if (size == 1) {
7869                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7870                         *inset = i40e_get_default_input_set(pctype);
7871                         return 0;
7872                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7873                         *inset = I40E_INSET_NONE;
7874                         return 0;
7875                 }
7876         }
7877
7878         for (i = 0, *inset = 0; i < size; i++) {
7879                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7880                         if (field[i] == inset_convert_table[j].field) {
7881                                 *inset |= inset_convert_table[j].inset;
7882                                 break;
7883                         }
7884                 }
7885
7886                 /* It contains unsupported input set, return immediately */
7887                 if (j == RTE_DIM(inset_convert_table))
7888                         return ret;
7889         }
7890
7891         return 0;
7892 }
7893
7894 /**
7895  * Translate the input set from bit masks to register aware bit masks
7896  * and vice versa
7897  */
7898 static uint64_t
7899 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7900 {
7901         uint64_t val = 0;
7902         uint16_t i;
7903
7904         struct inset_map {
7905                 uint64_t inset;
7906                 uint64_t inset_reg;
7907         };
7908
7909         static const struct inset_map inset_map_common[] = {
7910                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7911                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7912                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7913                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7914                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7915                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7916                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7917                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7918                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7919                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7920                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7921                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7922                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7923                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7924                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7925                 {I40E_INSET_TUNNEL_DMAC,
7926                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7927                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7928                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7929                 {I40E_INSET_TUNNEL_SRC_PORT,
7930                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7931                 {I40E_INSET_TUNNEL_DST_PORT,
7932                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7933                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7934                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7935                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7936                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7937                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7938                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7939                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7940                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7941                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7942         };
7943
7944     /* some different registers map in x722*/
7945         static const struct inset_map inset_map_diff_x722[] = {
7946                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7947                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7948                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7949                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7950         };
7951
7952         static const struct inset_map inset_map_diff_not_x722[] = {
7953                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7954                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7955                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7956                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7957         };
7958
7959         if (input == 0)
7960                 return val;
7961
7962         /* Translate input set to register aware inset */
7963         if (type == I40E_MAC_X722) {
7964                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7965                         if (input & inset_map_diff_x722[i].inset)
7966                                 val |= inset_map_diff_x722[i].inset_reg;
7967                 }
7968         } else {
7969                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7970                         if (input & inset_map_diff_not_x722[i].inset)
7971                                 val |= inset_map_diff_not_x722[i].inset_reg;
7972                 }
7973         }
7974
7975         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7976                 if (input & inset_map_common[i].inset)
7977                         val |= inset_map_common[i].inset_reg;
7978         }
7979
7980         return val;
7981 }
7982
7983 static int
7984 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7985 {
7986         uint8_t i, idx = 0;
7987         uint64_t inset_need_mask = inset;
7988
7989         static const struct {
7990                 uint64_t inset;
7991                 uint32_t mask;
7992         } inset_mask_map[] = {
7993                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7994                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7995                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7996                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7997                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7998                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7999                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8000                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8001         };
8002
8003         if (!inset || !mask || !nb_elem)
8004                 return 0;
8005
8006         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8007                 /* Clear the inset bit, if no MASK is required,
8008                  * for example proto + ttl
8009                  */
8010                 if ((inset & inset_mask_map[i].inset) ==
8011                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8012                         inset_need_mask &= ~inset_mask_map[i].inset;
8013                 if (!inset_need_mask)
8014                         return 0;
8015         }
8016         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8017                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8018                     inset_mask_map[i].inset) {
8019                         if (idx >= nb_elem) {
8020                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8021                                 return -EINVAL;
8022                         }
8023                         mask[idx] = inset_mask_map[i].mask;
8024                         idx++;
8025                 }
8026         }
8027
8028         return idx;
8029 }
8030
8031 static void
8032 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8033 {
8034         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8035
8036         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8037         if (reg != val)
8038                 i40e_write_rx_ctl(hw, addr, val);
8039         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8040                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8041 }
8042
8043 static void
8044 i40e_filter_input_set_init(struct i40e_pf *pf)
8045 {
8046         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8047         enum i40e_filter_pctype pctype;
8048         uint64_t input_set, inset_reg;
8049         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8050         int num, i;
8051
8052         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8053              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8054                 if (hw->mac.type == I40E_MAC_X722) {
8055                         if (!I40E_VALID_PCTYPE_X722(pctype))
8056                                 continue;
8057                 } else {
8058                         if (!I40E_VALID_PCTYPE(pctype))
8059                                 continue;
8060                 }
8061
8062                 input_set = i40e_get_default_input_set(pctype);
8063
8064                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8065                                                    I40E_INSET_MASK_NUM_REG);
8066                 if (num < 0)
8067                         return;
8068                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8069                                         input_set);
8070
8071                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8072                                       (uint32_t)(inset_reg & UINT32_MAX));
8073                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8074                                      (uint32_t)((inset_reg >>
8075                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8076                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8077                                       (uint32_t)(inset_reg & UINT32_MAX));
8078                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8079                                      (uint32_t)((inset_reg >>
8080                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8081
8082                 for (i = 0; i < num; i++) {
8083                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8084                                              mask_reg[i]);
8085                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8086                                              mask_reg[i]);
8087                 }
8088                 /*clear unused mask registers of the pctype */
8089                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8090                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8091                                              0);
8092                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8093                                              0);
8094                 }
8095                 I40E_WRITE_FLUSH(hw);
8096
8097                 /* store the default input set */
8098                 pf->hash_input_set[pctype] = input_set;
8099                 pf->fdir.input_set[pctype] = input_set;
8100         }
8101 }
8102
8103 int
8104 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8105                          struct rte_eth_input_set_conf *conf)
8106 {
8107         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8108         enum i40e_filter_pctype pctype;
8109         uint64_t input_set, inset_reg = 0;
8110         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8111         int ret, i, num;
8112
8113         if (!conf) {
8114                 PMD_DRV_LOG(ERR, "Invalid pointer");
8115                 return -EFAULT;
8116         }
8117         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8118             conf->op != RTE_ETH_INPUT_SET_ADD) {
8119                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8120                 return -EINVAL;
8121         }
8122
8123         if (!I40E_VALID_FLOW(conf->flow_type)) {
8124                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8125                 return -EINVAL;
8126         }
8127
8128         if (hw->mac.type == I40E_MAC_X722) {
8129                 /* get translated pctype value in fd pctype register */
8130                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8131                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8132                         conf->flow_type)));
8133         } else
8134                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8135
8136         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8137                                    conf->inset_size);
8138         if (ret) {
8139                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8140                 return -EINVAL;
8141         }
8142         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8143                                     input_set) != 0) {
8144                 PMD_DRV_LOG(ERR, "Invalid input set");
8145                 return -EINVAL;
8146         }
8147         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8148                 /* get inset value in register */
8149                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8150                 inset_reg <<= I40E_32_BIT_WIDTH;
8151                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8152                 input_set |= pf->hash_input_set[pctype];
8153         }
8154         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8155                                            I40E_INSET_MASK_NUM_REG);
8156         if (num < 0)
8157                 return -EINVAL;
8158
8159         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8160
8161         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8162                               (uint32_t)(inset_reg & UINT32_MAX));
8163         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8164                              (uint32_t)((inset_reg >>
8165                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8166
8167         for (i = 0; i < num; i++)
8168                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8169                                      mask_reg[i]);
8170         /*clear unused mask registers of the pctype */
8171         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8172                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8173                                      0);
8174         I40E_WRITE_FLUSH(hw);
8175
8176         pf->hash_input_set[pctype] = input_set;
8177         return 0;
8178 }
8179
8180 int
8181 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8182                          struct rte_eth_input_set_conf *conf)
8183 {
8184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8185         enum i40e_filter_pctype pctype;
8186         uint64_t input_set, inset_reg = 0;
8187         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8188         int ret, i, num;
8189
8190         if (!hw || !conf) {
8191                 PMD_DRV_LOG(ERR, "Invalid pointer");
8192                 return -EFAULT;
8193         }
8194         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8195             conf->op != RTE_ETH_INPUT_SET_ADD) {
8196                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8197                 return -EINVAL;
8198         }
8199
8200         if (!I40E_VALID_FLOW(conf->flow_type)) {
8201                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8202                 return -EINVAL;
8203         }
8204
8205         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8206
8207         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8208                                    conf->inset_size);
8209         if (ret) {
8210                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8211                 return -EINVAL;
8212         }
8213         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8214                                     input_set) != 0) {
8215                 PMD_DRV_LOG(ERR, "Invalid input set");
8216                 return -EINVAL;
8217         }
8218
8219         /* get inset value in register */
8220         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8221         inset_reg <<= I40E_32_BIT_WIDTH;
8222         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8223
8224         /* Can not change the inset reg for flex payload for fdir,
8225          * it is done by writing I40E_PRTQF_FD_FLXINSET
8226          * in i40e_set_flex_mask_on_pctype.
8227          */
8228         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8229                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8230         else
8231                 input_set |= pf->fdir.input_set[pctype];
8232         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8233                                            I40E_INSET_MASK_NUM_REG);
8234         if (num < 0)
8235                 return -EINVAL;
8236
8237         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8238
8239         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8240                               (uint32_t)(inset_reg & UINT32_MAX));
8241         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8242                              (uint32_t)((inset_reg >>
8243                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8244
8245         for (i = 0; i < num; i++)
8246                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8247                                      mask_reg[i]);
8248         /*clear unused mask registers of the pctype */
8249         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8250                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8251                                      0);
8252         I40E_WRITE_FLUSH(hw);
8253
8254         pf->fdir.input_set[pctype] = input_set;
8255         return 0;
8256 }
8257
8258 static int
8259 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8260 {
8261         int ret = 0;
8262
8263         if (!hw || !info) {
8264                 PMD_DRV_LOG(ERR, "Invalid pointer");
8265                 return -EFAULT;
8266         }
8267
8268         switch (info->info_type) {
8269         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8270                 i40e_get_symmetric_hash_enable_per_port(hw,
8271                                         &(info->info.enable));
8272                 break;
8273         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8274                 ret = i40e_get_hash_filter_global_config(hw,
8275                                 &(info->info.global_conf));
8276                 break;
8277         default:
8278                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8279                                                         info->info_type);
8280                 ret = -EINVAL;
8281                 break;
8282         }
8283
8284         return ret;
8285 }
8286
8287 static int
8288 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8289 {
8290         int ret = 0;
8291
8292         if (!hw || !info) {
8293                 PMD_DRV_LOG(ERR, "Invalid pointer");
8294                 return -EFAULT;
8295         }
8296
8297         switch (info->info_type) {
8298         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8299                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8300                 break;
8301         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8302                 ret = i40e_set_hash_filter_global_config(hw,
8303                                 &(info->info.global_conf));
8304                 break;
8305         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8306                 ret = i40e_hash_filter_inset_select(hw,
8307                                                &(info->info.input_set_conf));
8308                 break;
8309
8310         default:
8311                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8312                                                         info->info_type);
8313                 ret = -EINVAL;
8314                 break;
8315         }
8316
8317         return ret;
8318 }
8319
8320 /* Operations for hash function */
8321 static int
8322 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8323                       enum rte_filter_op filter_op,
8324                       void *arg)
8325 {
8326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8327         int ret = 0;
8328
8329         switch (filter_op) {
8330         case RTE_ETH_FILTER_NOP:
8331                 break;
8332         case RTE_ETH_FILTER_GET:
8333                 ret = i40e_hash_filter_get(hw,
8334                         (struct rte_eth_hash_filter_info *)arg);
8335                 break;
8336         case RTE_ETH_FILTER_SET:
8337                 ret = i40e_hash_filter_set(hw,
8338                         (struct rte_eth_hash_filter_info *)arg);
8339                 break;
8340         default:
8341                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8342                                                                 filter_op);
8343                 ret = -ENOTSUP;
8344                 break;
8345         }
8346
8347         return ret;
8348 }
8349
8350 /* Convert ethertype filter structure */
8351 static int
8352 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8353                               struct i40e_ethertype_filter *filter)
8354 {
8355         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8356         filter->input.ether_type = input->ether_type;
8357         filter->flags = input->flags;
8358         filter->queue = input->queue;
8359
8360         return 0;
8361 }
8362
8363 /* Check if there exists the ehtertype filter */
8364 struct i40e_ethertype_filter *
8365 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8366                                 const struct i40e_ethertype_filter_input *input)
8367 {
8368         int ret;
8369
8370         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8371         if (ret < 0)
8372                 return NULL;
8373
8374         return ethertype_rule->hash_map[ret];
8375 }
8376
8377 /* Add ethertype filter in SW list */
8378 static int
8379 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8380                                 struct i40e_ethertype_filter *filter)
8381 {
8382         struct i40e_ethertype_rule *rule = &pf->ethertype;
8383         int ret;
8384
8385         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8386         if (ret < 0) {
8387                 PMD_DRV_LOG(ERR,
8388                             "Failed to insert ethertype filter"
8389                             " to hash table %d!",
8390                             ret);
8391                 return ret;
8392         }
8393         rule->hash_map[ret] = filter;
8394
8395         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8396
8397         return 0;
8398 }
8399
8400 /* Delete ethertype filter in SW list */
8401 int
8402 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8403                              struct i40e_ethertype_filter_input *input)
8404 {
8405         struct i40e_ethertype_rule *rule = &pf->ethertype;
8406         struct i40e_ethertype_filter *filter;
8407         int ret;
8408
8409         ret = rte_hash_del_key(rule->hash_table, input);
8410         if (ret < 0) {
8411                 PMD_DRV_LOG(ERR,
8412                             "Failed to delete ethertype filter"
8413                             " to hash table %d!",
8414                             ret);
8415                 return ret;
8416         }
8417         filter = rule->hash_map[ret];
8418         rule->hash_map[ret] = NULL;
8419
8420         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8421         rte_free(filter);
8422
8423         return 0;
8424 }
8425
8426 /*
8427  * Configure ethertype filter, which can director packet by filtering
8428  * with mac address and ether_type or only ether_type
8429  */
8430 int
8431 i40e_ethertype_filter_set(struct i40e_pf *pf,
8432                         struct rte_eth_ethertype_filter *filter,
8433                         bool add)
8434 {
8435         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8436         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8437         struct i40e_ethertype_filter *ethertype_filter, *node;
8438         struct i40e_ethertype_filter check_filter;
8439         struct i40e_control_filter_stats stats;
8440         uint16_t flags = 0;
8441         int ret;
8442
8443         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8444                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8445                 return -EINVAL;
8446         }
8447         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8448                 filter->ether_type == ETHER_TYPE_IPv6) {
8449                 PMD_DRV_LOG(ERR,
8450                         "unsupported ether_type(0x%04x) in control packet filter.",
8451                         filter->ether_type);
8452                 return -EINVAL;
8453         }
8454         if (filter->ether_type == ETHER_TYPE_VLAN)
8455                 PMD_DRV_LOG(WARNING,
8456                         "filter vlan ether_type in first tag is not supported.");
8457
8458         /* Check if there is the filter in SW list */
8459         memset(&check_filter, 0, sizeof(check_filter));
8460         i40e_ethertype_filter_convert(filter, &check_filter);
8461         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8462                                                &check_filter.input);
8463         if (add && node) {
8464                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8465                 return -EINVAL;
8466         }
8467
8468         if (!add && !node) {
8469                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8470                 return -EINVAL;
8471         }
8472
8473         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8474                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8475         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8476                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8477         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8478
8479         memset(&stats, 0, sizeof(stats));
8480         ret = i40e_aq_add_rem_control_packet_filter(hw,
8481                         filter->mac_addr.addr_bytes,
8482                         filter->ether_type, flags,
8483                         pf->main_vsi->seid,
8484                         filter->queue, add, &stats, NULL);
8485
8486         PMD_DRV_LOG(INFO,
8487                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8488                 ret, stats.mac_etype_used, stats.etype_used,
8489                 stats.mac_etype_free, stats.etype_free);
8490         if (ret < 0)
8491                 return -ENOSYS;
8492
8493         /* Add or delete a filter in SW list */
8494         if (add) {
8495                 ethertype_filter = rte_zmalloc("ethertype_filter",
8496                                        sizeof(*ethertype_filter), 0);
8497                 rte_memcpy(ethertype_filter, &check_filter,
8498                            sizeof(check_filter));
8499                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8500         } else {
8501                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8502         }
8503
8504         return ret;
8505 }
8506
8507 /*
8508  * Handle operations for ethertype filter.
8509  */
8510 static int
8511 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8512                                 enum rte_filter_op filter_op,
8513                                 void *arg)
8514 {
8515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8516         int ret = 0;
8517
8518         if (filter_op == RTE_ETH_FILTER_NOP)
8519                 return ret;
8520
8521         if (arg == NULL) {
8522                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8523                             filter_op);
8524                 return -EINVAL;
8525         }
8526
8527         switch (filter_op) {
8528         case RTE_ETH_FILTER_ADD:
8529                 ret = i40e_ethertype_filter_set(pf,
8530                         (struct rte_eth_ethertype_filter *)arg,
8531                         TRUE);
8532                 break;
8533         case RTE_ETH_FILTER_DELETE:
8534                 ret = i40e_ethertype_filter_set(pf,
8535                         (struct rte_eth_ethertype_filter *)arg,
8536                         FALSE);
8537                 break;
8538         default:
8539                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8540                 ret = -ENOSYS;
8541                 break;
8542         }
8543         return ret;
8544 }
8545
8546 static int
8547 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8548                      enum rte_filter_type filter_type,
8549                      enum rte_filter_op filter_op,
8550                      void *arg)
8551 {
8552         int ret = 0;
8553
8554         if (dev == NULL)
8555                 return -EINVAL;
8556
8557         switch (filter_type) {
8558         case RTE_ETH_FILTER_NONE:
8559                 /* For global configuration */
8560                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8561                 break;
8562         case RTE_ETH_FILTER_HASH:
8563                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8564                 break;
8565         case RTE_ETH_FILTER_MACVLAN:
8566                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8567                 break;
8568         case RTE_ETH_FILTER_ETHERTYPE:
8569                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8570                 break;
8571         case RTE_ETH_FILTER_TUNNEL:
8572                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8573                 break;
8574         case RTE_ETH_FILTER_FDIR:
8575                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8576                 break;
8577         case RTE_ETH_FILTER_GENERIC:
8578                 if (filter_op != RTE_ETH_FILTER_GET)
8579                         return -EINVAL;
8580                 *(const void **)arg = &i40e_flow_ops;
8581                 break;
8582         default:
8583                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8584                                                         filter_type);
8585                 ret = -EINVAL;
8586                 break;
8587         }
8588
8589         return ret;
8590 }
8591
8592 /*
8593  * Check and enable Extended Tag.
8594  * Enabling Extended Tag is important for 40G performance.
8595  */
8596 static void
8597 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8598 {
8599         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8600         uint32_t buf = 0;
8601         int ret;
8602
8603         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8604                                       PCI_DEV_CAP_REG);
8605         if (ret < 0) {
8606                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8607                             PCI_DEV_CAP_REG);
8608                 return;
8609         }
8610         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8611                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8612                 return;
8613         }
8614
8615         buf = 0;
8616         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8617                                       PCI_DEV_CTRL_REG);
8618         if (ret < 0) {
8619                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8620                             PCI_DEV_CTRL_REG);
8621                 return;
8622         }
8623         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8624                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8625                 return;
8626         }
8627         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8628         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8629                                        PCI_DEV_CTRL_REG);
8630         if (ret < 0) {
8631                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8632                             PCI_DEV_CTRL_REG);
8633                 return;
8634         }
8635 }
8636
8637 /*
8638  * As some registers wouldn't be reset unless a global hardware reset,
8639  * hardware initialization is needed to put those registers into an
8640  * expected initial state.
8641  */
8642 static void
8643 i40e_hw_init(struct rte_eth_dev *dev)
8644 {
8645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8646
8647         i40e_enable_extended_tag(dev);
8648
8649         /* clear the PF Queue Filter control register */
8650         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8651
8652         /* Disable symmetric hash per port */
8653         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8654 }
8655
8656 enum i40e_filter_pctype
8657 i40e_flowtype_to_pctype(uint16_t flow_type)
8658 {
8659         static const enum i40e_filter_pctype pctype_table[] = {
8660                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8661                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8662                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8663                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8664                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8665                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8666                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8667                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8668                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8669                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8670                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8671                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8672                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8673                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8674                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8675                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8676                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8677                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8678                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8679         };
8680
8681         return pctype_table[flow_type];
8682 }
8683
8684 uint16_t
8685 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8686 {
8687         static const uint16_t flowtype_table[] = {
8688                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8689                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8690                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8691                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8692                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8693                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8694                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8695                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8696                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8697                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8698                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8699                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8700                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8701                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8702                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8703                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8704                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8705                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8706                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8707                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8708                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8709                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8710                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8711                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8712                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8713                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8714                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8715                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8716                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8717                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8718                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8719         };
8720
8721         return flowtype_table[pctype];
8722 }
8723
8724 /*
8725  * On X710, performance number is far from the expectation on recent firmware
8726  * versions; on XL710, performance number is also far from the expectation on
8727  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8728  * mode is enabled and port MAC address is equal to the packet destination MAC
8729  * address. The fix for this issue may not be integrated in the following
8730  * firmware version. So the workaround in software driver is needed. It needs
8731  * to modify the initial values of 3 internal only registers for both X710 and
8732  * XL710. Note that the values for X710 or XL710 could be different, and the
8733  * workaround can be removed when it is fixed in firmware in the future.
8734  */
8735
8736 /* For both X710 and XL710 */
8737 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8738 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8739
8740 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8741 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8742
8743 /* For X722 */
8744 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8745 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8746
8747 /* For X710 */
8748 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8749 /* For XL710 */
8750 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8751 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8752
8753 static int
8754 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8755 {
8756         enum i40e_status_code status;
8757         struct i40e_aq_get_phy_abilities_resp phy_ab;
8758         int ret = -ENOTSUP;
8759
8760         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8761                                               NULL);
8762
8763         if (status)
8764                 return ret;
8765
8766         return 0;
8767 }
8768
8769 static void
8770 i40e_configure_registers(struct i40e_hw *hw)
8771 {
8772         static struct {
8773                 uint32_t addr;
8774                 uint64_t val;
8775         } reg_table[] = {
8776                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8777                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8778                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8779         };
8780         uint64_t reg;
8781         uint32_t i;
8782         int ret;
8783
8784         for (i = 0; i < RTE_DIM(reg_table); i++) {
8785                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8786                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8787                                 reg_table[i].val =
8788                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8789                         else /* For X710/XL710/XXV710 */
8790                                 reg_table[i].val =
8791                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8792                 }
8793
8794                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8795                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8796                                 reg_table[i].val =
8797                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8798                         else /* For X710/XL710/XXV710 */
8799                                 reg_table[i].val =
8800                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8801                 }
8802
8803                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8804                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8805                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8806                                 reg_table[i].val =
8807                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8808                         else /* For X710 */
8809                                 reg_table[i].val =
8810                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8811                 }
8812
8813                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8814                                                         &reg, NULL);
8815                 if (ret < 0) {
8816                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8817                                                         reg_table[i].addr);
8818                         break;
8819                 }
8820                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8821                                                 reg_table[i].addr, reg);
8822                 if (reg == reg_table[i].val)
8823                         continue;
8824
8825                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8826                                                 reg_table[i].val, NULL);
8827                 if (ret < 0) {
8828                         PMD_DRV_LOG(ERR,
8829                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8830                                 reg_table[i].val, reg_table[i].addr);
8831                         break;
8832                 }
8833                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8834                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8835         }
8836 }
8837
8838 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8839 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8840 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8841 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8842 static int
8843 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8844 {
8845         uint32_t reg;
8846         int ret;
8847
8848         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8849                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8850                 return -EINVAL;
8851         }
8852
8853         /* Configure for double VLAN RX stripping */
8854         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8855         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8856                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8857                 ret = i40e_aq_debug_write_register(hw,
8858                                                    I40E_VSI_TSR(vsi->vsi_id),
8859                                                    reg, NULL);
8860                 if (ret < 0) {
8861                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8862                                     vsi->vsi_id);
8863                         return I40E_ERR_CONFIG;
8864                 }
8865         }
8866
8867         /* Configure for double VLAN TX insertion */
8868         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8869         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8870                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8871                 ret = i40e_aq_debug_write_register(hw,
8872                                                    I40E_VSI_L2TAGSTXVALID(
8873                                                    vsi->vsi_id), reg, NULL);
8874                 if (ret < 0) {
8875                         PMD_DRV_LOG(ERR,
8876                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8877                                 vsi->vsi_id);
8878                         return I40E_ERR_CONFIG;
8879                 }
8880         }
8881
8882         return 0;
8883 }
8884
8885 /**
8886  * i40e_aq_add_mirror_rule
8887  * @hw: pointer to the hardware structure
8888  * @seid: VEB seid to add mirror rule to
8889  * @dst_id: destination vsi seid
8890  * @entries: Buffer which contains the entities to be mirrored
8891  * @count: number of entities contained in the buffer
8892  * @rule_id:the rule_id of the rule to be added
8893  *
8894  * Add a mirror rule for a given veb.
8895  *
8896  **/
8897 static enum i40e_status_code
8898 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8899                         uint16_t seid, uint16_t dst_id,
8900                         uint16_t rule_type, uint16_t *entries,
8901                         uint16_t count, uint16_t *rule_id)
8902 {
8903         struct i40e_aq_desc desc;
8904         struct i40e_aqc_add_delete_mirror_rule cmd;
8905         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8906                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8907                 &desc.params.raw;
8908         uint16_t buff_len;
8909         enum i40e_status_code status;
8910
8911         i40e_fill_default_direct_cmd_desc(&desc,
8912                                           i40e_aqc_opc_add_mirror_rule);
8913         memset(&cmd, 0, sizeof(cmd));
8914
8915         buff_len = sizeof(uint16_t) * count;
8916         desc.datalen = rte_cpu_to_le_16(buff_len);
8917         if (buff_len > 0)
8918                 desc.flags |= rte_cpu_to_le_16(
8919                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8920         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8921                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8922         cmd.num_entries = rte_cpu_to_le_16(count);
8923         cmd.seid = rte_cpu_to_le_16(seid);
8924         cmd.destination = rte_cpu_to_le_16(dst_id);
8925
8926         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8927         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8928         PMD_DRV_LOG(INFO,
8929                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8930                 hw->aq.asq_last_status, resp->rule_id,
8931                 resp->mirror_rules_used, resp->mirror_rules_free);
8932         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8933
8934         return status;
8935 }
8936
8937 /**
8938  * i40e_aq_del_mirror_rule
8939  * @hw: pointer to the hardware structure
8940  * @seid: VEB seid to add mirror rule to
8941  * @entries: Buffer which contains the entities to be mirrored
8942  * @count: number of entities contained in the buffer
8943  * @rule_id:the rule_id of the rule to be delete
8944  *
8945  * Delete a mirror rule for a given veb.
8946  *
8947  **/
8948 static enum i40e_status_code
8949 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8950                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8951                 uint16_t count, uint16_t rule_id)
8952 {
8953         struct i40e_aq_desc desc;
8954         struct i40e_aqc_add_delete_mirror_rule cmd;
8955         uint16_t buff_len = 0;
8956         enum i40e_status_code status;
8957         void *buff = NULL;
8958
8959         i40e_fill_default_direct_cmd_desc(&desc,
8960                                           i40e_aqc_opc_delete_mirror_rule);
8961         memset(&cmd, 0, sizeof(cmd));
8962         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8963                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8964                                                           I40E_AQ_FLAG_RD));
8965                 cmd.num_entries = count;
8966                 buff_len = sizeof(uint16_t) * count;
8967                 desc.datalen = rte_cpu_to_le_16(buff_len);
8968                 buff = (void *)entries;
8969         } else
8970                 /* rule id is filled in destination field for deleting mirror rule */
8971                 cmd.destination = rte_cpu_to_le_16(rule_id);
8972
8973         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8974                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8975         cmd.seid = rte_cpu_to_le_16(seid);
8976
8977         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8978         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8979
8980         return status;
8981 }
8982
8983 /**
8984  * i40e_mirror_rule_set
8985  * @dev: pointer to the hardware structure
8986  * @mirror_conf: mirror rule info
8987  * @sw_id: mirror rule's sw_id
8988  * @on: enable/disable
8989  *
8990  * set a mirror rule.
8991  *
8992  **/
8993 static int
8994 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8995                         struct rte_eth_mirror_conf *mirror_conf,
8996                         uint8_t sw_id, uint8_t on)
8997 {
8998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8999         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9000         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9001         struct i40e_mirror_rule *parent = NULL;
9002         uint16_t seid, dst_seid, rule_id;
9003         uint16_t i, j = 0;
9004         int ret;
9005
9006         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9007
9008         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9009                 PMD_DRV_LOG(ERR,
9010                         "mirror rule can not be configured without veb or vfs.");
9011                 return -ENOSYS;
9012         }
9013         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9014                 PMD_DRV_LOG(ERR, "mirror table is full.");
9015                 return -ENOSPC;
9016         }
9017         if (mirror_conf->dst_pool > pf->vf_num) {
9018                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9019                                  mirror_conf->dst_pool);
9020                 return -EINVAL;
9021         }
9022
9023         seid = pf->main_vsi->veb->seid;
9024
9025         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9026                 if (sw_id <= it->index) {
9027                         mirr_rule = it;
9028                         break;
9029                 }
9030                 parent = it;
9031         }
9032         if (mirr_rule && sw_id == mirr_rule->index) {
9033                 if (on) {
9034                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9035                         return -EEXIST;
9036                 } else {
9037                         ret = i40e_aq_del_mirror_rule(hw, seid,
9038                                         mirr_rule->rule_type,
9039                                         mirr_rule->entries,
9040                                         mirr_rule->num_entries, mirr_rule->id);
9041                         if (ret < 0) {
9042                                 PMD_DRV_LOG(ERR,
9043                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9044                                         ret, hw->aq.asq_last_status);
9045                                 return -ENOSYS;
9046                         }
9047                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9048                         rte_free(mirr_rule);
9049                         pf->nb_mirror_rule--;
9050                         return 0;
9051                 }
9052         } else if (!on) {
9053                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9054                 return -ENOENT;
9055         }
9056
9057         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9058                                 sizeof(struct i40e_mirror_rule) , 0);
9059         if (!mirr_rule) {
9060                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9061                 return I40E_ERR_NO_MEMORY;
9062         }
9063         switch (mirror_conf->rule_type) {
9064         case ETH_MIRROR_VLAN:
9065                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9066                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9067                                 mirr_rule->entries[j] =
9068                                         mirror_conf->vlan.vlan_id[i];
9069                                 j++;
9070                         }
9071                 }
9072                 if (j == 0) {
9073                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9074                         rte_free(mirr_rule);
9075                         return -EINVAL;
9076                 }
9077                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9078                 break;
9079         case ETH_MIRROR_VIRTUAL_POOL_UP:
9080         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9081                 /* check if the specified pool bit is out of range */
9082                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9083                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9084                         rte_free(mirr_rule);
9085                         return -EINVAL;
9086                 }
9087                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9088                         if (mirror_conf->pool_mask & (1ULL << i)) {
9089                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9090                                 j++;
9091                         }
9092                 }
9093                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9094                         /* add pf vsi to entries */
9095                         mirr_rule->entries[j] = pf->main_vsi_seid;
9096                         j++;
9097                 }
9098                 if (j == 0) {
9099                         PMD_DRV_LOG(ERR, "pool is not specified.");
9100                         rte_free(mirr_rule);
9101                         return -EINVAL;
9102                 }
9103                 /* egress and ingress in aq commands means from switch but not port */
9104                 mirr_rule->rule_type =
9105                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9106                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9107                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9108                 break;
9109         case ETH_MIRROR_UPLINK_PORT:
9110                 /* egress and ingress in aq commands means from switch but not port*/
9111                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9112                 break;
9113         case ETH_MIRROR_DOWNLINK_PORT:
9114                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9115                 break;
9116         default:
9117                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9118                         mirror_conf->rule_type);
9119                 rte_free(mirr_rule);
9120                 return -EINVAL;
9121         }
9122
9123         /* If the dst_pool is equal to vf_num, consider it as PF */
9124         if (mirror_conf->dst_pool == pf->vf_num)
9125                 dst_seid = pf->main_vsi_seid;
9126         else
9127                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9128
9129         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9130                                       mirr_rule->rule_type, mirr_rule->entries,
9131                                       j, &rule_id);
9132         if (ret < 0) {
9133                 PMD_DRV_LOG(ERR,
9134                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9135                         ret, hw->aq.asq_last_status);
9136                 rte_free(mirr_rule);
9137                 return -ENOSYS;
9138         }
9139
9140         mirr_rule->index = sw_id;
9141         mirr_rule->num_entries = j;
9142         mirr_rule->id = rule_id;
9143         mirr_rule->dst_vsi_seid = dst_seid;
9144
9145         if (parent)
9146                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9147         else
9148                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9149
9150         pf->nb_mirror_rule++;
9151         return 0;
9152 }
9153
9154 /**
9155  * i40e_mirror_rule_reset
9156  * @dev: pointer to the device
9157  * @sw_id: mirror rule's sw_id
9158  *
9159  * reset a mirror rule.
9160  *
9161  **/
9162 static int
9163 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9164 {
9165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9167         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9168         uint16_t seid;
9169         int ret;
9170
9171         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9172
9173         seid = pf->main_vsi->veb->seid;
9174
9175         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9176                 if (sw_id == it->index) {
9177                         mirr_rule = it;
9178                         break;
9179                 }
9180         }
9181         if (mirr_rule) {
9182                 ret = i40e_aq_del_mirror_rule(hw, seid,
9183                                 mirr_rule->rule_type,
9184                                 mirr_rule->entries,
9185                                 mirr_rule->num_entries, mirr_rule->id);
9186                 if (ret < 0) {
9187                         PMD_DRV_LOG(ERR,
9188                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9189                                 ret, hw->aq.asq_last_status);
9190                         return -ENOSYS;
9191                 }
9192                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9193                 rte_free(mirr_rule);
9194                 pf->nb_mirror_rule--;
9195         } else {
9196                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9197                 return -ENOENT;
9198         }
9199         return 0;
9200 }
9201
9202 static uint64_t
9203 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9204 {
9205         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9206         uint64_t systim_cycles;
9207
9208         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9209         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9210                         << 32;
9211
9212         return systim_cycles;
9213 }
9214
9215 static uint64_t
9216 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9217 {
9218         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9219         uint64_t rx_tstamp;
9220
9221         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9222         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9223                         << 32;
9224
9225         return rx_tstamp;
9226 }
9227
9228 static uint64_t
9229 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9230 {
9231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9232         uint64_t tx_tstamp;
9233
9234         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9235         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9236                         << 32;
9237
9238         return tx_tstamp;
9239 }
9240
9241 static void
9242 i40e_start_timecounters(struct rte_eth_dev *dev)
9243 {
9244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9245         struct i40e_adapter *adapter =
9246                         (struct i40e_adapter *)dev->data->dev_private;
9247         struct rte_eth_link link;
9248         uint32_t tsync_inc_l;
9249         uint32_t tsync_inc_h;
9250
9251         /* Get current link speed. */
9252         memset(&link, 0, sizeof(link));
9253         i40e_dev_link_update(dev, 1);
9254         rte_i40e_dev_atomic_read_link_status(dev, &link);
9255
9256         switch (link.link_speed) {
9257         case ETH_SPEED_NUM_40G:
9258                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9259                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9260                 break;
9261         case ETH_SPEED_NUM_10G:
9262                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9263                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9264                 break;
9265         case ETH_SPEED_NUM_1G:
9266                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9267                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9268                 break;
9269         default:
9270                 tsync_inc_l = 0x0;
9271                 tsync_inc_h = 0x0;
9272         }
9273
9274         /* Set the timesync increment value. */
9275         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9276         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9277
9278         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9279         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9280         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9281
9282         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9283         adapter->systime_tc.cc_shift = 0;
9284         adapter->systime_tc.nsec_mask = 0;
9285
9286         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9287         adapter->rx_tstamp_tc.cc_shift = 0;
9288         adapter->rx_tstamp_tc.nsec_mask = 0;
9289
9290         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9291         adapter->tx_tstamp_tc.cc_shift = 0;
9292         adapter->tx_tstamp_tc.nsec_mask = 0;
9293 }
9294
9295 static int
9296 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9297 {
9298         struct i40e_adapter *adapter =
9299                         (struct i40e_adapter *)dev->data->dev_private;
9300
9301         adapter->systime_tc.nsec += delta;
9302         adapter->rx_tstamp_tc.nsec += delta;
9303         adapter->tx_tstamp_tc.nsec += delta;
9304
9305         return 0;
9306 }
9307
9308 static int
9309 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9310 {
9311         uint64_t ns;
9312         struct i40e_adapter *adapter =
9313                         (struct i40e_adapter *)dev->data->dev_private;
9314
9315         ns = rte_timespec_to_ns(ts);
9316
9317         /* Set the timecounters to a new value. */
9318         adapter->systime_tc.nsec = ns;
9319         adapter->rx_tstamp_tc.nsec = ns;
9320         adapter->tx_tstamp_tc.nsec = ns;
9321
9322         return 0;
9323 }
9324
9325 static int
9326 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9327 {
9328         uint64_t ns, systime_cycles;
9329         struct i40e_adapter *adapter =
9330                         (struct i40e_adapter *)dev->data->dev_private;
9331
9332         systime_cycles = i40e_read_systime_cyclecounter(dev);
9333         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9334         *ts = rte_ns_to_timespec(ns);
9335
9336         return 0;
9337 }
9338
9339 static int
9340 i40e_timesync_enable(struct rte_eth_dev *dev)
9341 {
9342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9343         uint32_t tsync_ctl_l;
9344         uint32_t tsync_ctl_h;
9345
9346         /* Stop the timesync system time. */
9347         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9348         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9349         /* Reset the timesync system time value. */
9350         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9351         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9352
9353         i40e_start_timecounters(dev);
9354
9355         /* Clear timesync registers. */
9356         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9357         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9358         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9359         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9360         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9361         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9362
9363         /* Enable timestamping of PTP packets. */
9364         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9365         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9366
9367         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9368         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9369         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9370
9371         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9372         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9373
9374         return 0;
9375 }
9376
9377 static int
9378 i40e_timesync_disable(struct rte_eth_dev *dev)
9379 {
9380         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9381         uint32_t tsync_ctl_l;
9382         uint32_t tsync_ctl_h;
9383
9384         /* Disable timestamping of transmitted PTP packets. */
9385         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9386         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9387
9388         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9389         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9390
9391         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9392         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9393
9394         /* Reset the timesync increment value. */
9395         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9396         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9397
9398         return 0;
9399 }
9400
9401 static int
9402 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9403                                 struct timespec *timestamp, uint32_t flags)
9404 {
9405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9406         struct i40e_adapter *adapter =
9407                 (struct i40e_adapter *)dev->data->dev_private;
9408
9409         uint32_t sync_status;
9410         uint32_t index = flags & 0x03;
9411         uint64_t rx_tstamp_cycles;
9412         uint64_t ns;
9413
9414         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9415         if ((sync_status & (1 << index)) == 0)
9416                 return -EINVAL;
9417
9418         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9419         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9420         *timestamp = rte_ns_to_timespec(ns);
9421
9422         return 0;
9423 }
9424
9425 static int
9426 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9427                                 struct timespec *timestamp)
9428 {
9429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9430         struct i40e_adapter *adapter =
9431                 (struct i40e_adapter *)dev->data->dev_private;
9432
9433         uint32_t sync_status;
9434         uint64_t tx_tstamp_cycles;
9435         uint64_t ns;
9436
9437         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9438         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9439                 return -EINVAL;
9440
9441         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9442         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9443         *timestamp = rte_ns_to_timespec(ns);
9444
9445         return 0;
9446 }
9447
9448 /*
9449  * i40e_parse_dcb_configure - parse dcb configure from user
9450  * @dev: the device being configured
9451  * @dcb_cfg: pointer of the result of parse
9452  * @*tc_map: bit map of enabled traffic classes
9453  *
9454  * Returns 0 on success, negative value on failure
9455  */
9456 static int
9457 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9458                          struct i40e_dcbx_config *dcb_cfg,
9459                          uint8_t *tc_map)
9460 {
9461         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9462         uint8_t i, tc_bw, bw_lf;
9463
9464         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9465
9466         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9467         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9468                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9469                 return -EINVAL;
9470         }
9471
9472         /* assume each tc has the same bw */
9473         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9474         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9475                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9476         /* to ensure the sum of tcbw is equal to 100 */
9477         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9478         for (i = 0; i < bw_lf; i++)
9479                 dcb_cfg->etscfg.tcbwtable[i]++;
9480
9481         /* assume each tc has the same Transmission Selection Algorithm */
9482         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9483                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9484
9485         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9486                 dcb_cfg->etscfg.prioritytable[i] =
9487                                 dcb_rx_conf->dcb_tc[i];
9488
9489         /* FW needs one App to configure HW */
9490         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9491         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9492         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9493         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9494
9495         if (dcb_rx_conf->nb_tcs == 0)
9496                 *tc_map = 1; /* tc0 only */
9497         else
9498                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9499
9500         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9501                 dcb_cfg->pfc.willing = 0;
9502                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9503                 dcb_cfg->pfc.pfcenable = *tc_map;
9504         }
9505         return 0;
9506 }
9507
9508
9509 static enum i40e_status_code
9510 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9511                               struct i40e_aqc_vsi_properties_data *info,
9512                               uint8_t enabled_tcmap)
9513 {
9514         enum i40e_status_code ret;
9515         int i, total_tc = 0;
9516         uint16_t qpnum_per_tc, bsf, qp_idx;
9517         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9518         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9519         uint16_t used_queues;
9520
9521         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9522         if (ret != I40E_SUCCESS)
9523                 return ret;
9524
9525         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9526                 if (enabled_tcmap & (1 << i))
9527                         total_tc++;
9528         }
9529         if (total_tc == 0)
9530                 total_tc = 1;
9531         vsi->enabled_tc = enabled_tcmap;
9532
9533         /* different VSI has different queues assigned */
9534         if (vsi->type == I40E_VSI_MAIN)
9535                 used_queues = dev_data->nb_rx_queues -
9536                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9537         else if (vsi->type == I40E_VSI_VMDQ2)
9538                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9539         else {
9540                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9541                 return I40E_ERR_NO_AVAILABLE_VSI;
9542         }
9543
9544         qpnum_per_tc = used_queues / total_tc;
9545         /* Number of queues per enabled TC */
9546         if (qpnum_per_tc == 0) {
9547                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9548                 return I40E_ERR_INVALID_QP_ID;
9549         }
9550         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9551                                 I40E_MAX_Q_PER_TC);
9552         bsf = rte_bsf32(qpnum_per_tc);
9553
9554         /**
9555          * Configure TC and queue mapping parameters, for enabled TC,
9556          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9557          * default queue will serve it.
9558          */
9559         qp_idx = 0;
9560         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9561                 if (vsi->enabled_tc & (1 << i)) {
9562                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9563                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9564                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9565                         qp_idx += qpnum_per_tc;
9566                 } else
9567                         info->tc_mapping[i] = 0;
9568         }
9569
9570         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9571         if (vsi->type == I40E_VSI_SRIOV) {
9572                 info->mapping_flags |=
9573                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9574                 for (i = 0; i < vsi->nb_qps; i++)
9575                         info->queue_mapping[i] =
9576                                 rte_cpu_to_le_16(vsi->base_queue + i);
9577         } else {
9578                 info->mapping_flags |=
9579                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9580                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9581         }
9582         info->valid_sections |=
9583                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9584
9585         return I40E_SUCCESS;
9586 }
9587
9588 /*
9589  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9590  * @veb: VEB to be configured
9591  * @tc_map: enabled TC bitmap
9592  *
9593  * Returns 0 on success, negative value on failure
9594  */
9595 static enum i40e_status_code
9596 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9597 {
9598         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9599         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9600         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9601         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9602         enum i40e_status_code ret = I40E_SUCCESS;
9603         int i;
9604         uint32_t bw_max;
9605
9606         /* Check if enabled_tc is same as existing or new TCs */
9607         if (veb->enabled_tc == tc_map)
9608                 return ret;
9609
9610         /* configure tc bandwidth */
9611         memset(&veb_bw, 0, sizeof(veb_bw));
9612         veb_bw.tc_valid_bits = tc_map;
9613         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9614         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9615                 if (tc_map & BIT_ULL(i))
9616                         veb_bw.tc_bw_share_credits[i] = 1;
9617         }
9618         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9619                                                    &veb_bw, NULL);
9620         if (ret) {
9621                 PMD_INIT_LOG(ERR,
9622                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9623                         hw->aq.asq_last_status);
9624                 return ret;
9625         }
9626
9627         memset(&ets_query, 0, sizeof(ets_query));
9628         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9629                                                    &ets_query, NULL);
9630         if (ret != I40E_SUCCESS) {
9631                 PMD_DRV_LOG(ERR,
9632                         "Failed to get switch_comp ETS configuration %u",
9633                         hw->aq.asq_last_status);
9634                 return ret;
9635         }
9636         memset(&bw_query, 0, sizeof(bw_query));
9637         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9638                                                   &bw_query, NULL);
9639         if (ret != I40E_SUCCESS) {
9640                 PMD_DRV_LOG(ERR,
9641                         "Failed to get switch_comp bandwidth configuration %u",
9642                         hw->aq.asq_last_status);
9643                 return ret;
9644         }
9645
9646         /* store and print out BW info */
9647         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9648         veb->bw_info.bw_max = ets_query.tc_bw_max;
9649         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9650         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9651         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9652                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9653                      I40E_16_BIT_WIDTH);
9654         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9655                 veb->bw_info.bw_ets_share_credits[i] =
9656                                 bw_query.tc_bw_share_credits[i];
9657                 veb->bw_info.bw_ets_credits[i] =
9658                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9659                 /* 4 bits per TC, 4th bit is reserved */
9660                 veb->bw_info.bw_ets_max[i] =
9661                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9662                                   RTE_LEN2MASK(3, uint8_t));
9663                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9664                             veb->bw_info.bw_ets_share_credits[i]);
9665                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9666                             veb->bw_info.bw_ets_credits[i]);
9667                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9668                             veb->bw_info.bw_ets_max[i]);
9669         }
9670
9671         veb->enabled_tc = tc_map;
9672
9673         return ret;
9674 }
9675
9676
9677 /*
9678  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9679  * @vsi: VSI to be configured
9680  * @tc_map: enabled TC bitmap
9681  *
9682  * Returns 0 on success, negative value on failure
9683  */
9684 static enum i40e_status_code
9685 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9686 {
9687         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9688         struct i40e_vsi_context ctxt;
9689         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9690         enum i40e_status_code ret = I40E_SUCCESS;
9691         int i;
9692
9693         /* Check if enabled_tc is same as existing or new TCs */
9694         if (vsi->enabled_tc == tc_map)
9695                 return ret;
9696
9697         /* configure tc bandwidth */
9698         memset(&bw_data, 0, sizeof(bw_data));
9699         bw_data.tc_valid_bits = tc_map;
9700         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9701         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9702                 if (tc_map & BIT_ULL(i))
9703                         bw_data.tc_bw_credits[i] = 1;
9704         }
9705         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9706         if (ret) {
9707                 PMD_INIT_LOG(ERR,
9708                         "AQ command Config VSI BW allocation per TC failed = %d",
9709                         hw->aq.asq_last_status);
9710                 goto out;
9711         }
9712         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9713                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9714
9715         /* Update Queue Pairs Mapping for currently enabled UPs */
9716         ctxt.seid = vsi->seid;
9717         ctxt.pf_num = hw->pf_id;
9718         ctxt.vf_num = 0;
9719         ctxt.uplink_seid = vsi->uplink_seid;
9720         ctxt.info = vsi->info;
9721         i40e_get_cap(hw);
9722         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9723         if (ret)
9724                 goto out;
9725
9726         /* Update the VSI after updating the VSI queue-mapping information */
9727         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9728         if (ret) {
9729                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9730                         hw->aq.asq_last_status);
9731                 goto out;
9732         }
9733         /* update the local VSI info with updated queue map */
9734         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9735                                         sizeof(vsi->info.tc_mapping));
9736         (void)rte_memcpy(&vsi->info.queue_mapping,
9737                         &ctxt.info.queue_mapping,
9738                 sizeof(vsi->info.queue_mapping));
9739         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9740         vsi->info.valid_sections = 0;
9741
9742         /* query and update current VSI BW information */
9743         ret = i40e_vsi_get_bw_config(vsi);
9744         if (ret) {
9745                 PMD_INIT_LOG(ERR,
9746                          "Failed updating vsi bw info, err %s aq_err %s",
9747                          i40e_stat_str(hw, ret),
9748                          i40e_aq_str(hw, hw->aq.asq_last_status));
9749                 goto out;
9750         }
9751
9752         vsi->enabled_tc = tc_map;
9753
9754 out:
9755         return ret;
9756 }
9757
9758 /*
9759  * i40e_dcb_hw_configure - program the dcb setting to hw
9760  * @pf: pf the configuration is taken on
9761  * @new_cfg: new configuration
9762  * @tc_map: enabled TC bitmap
9763  *
9764  * Returns 0 on success, negative value on failure
9765  */
9766 static enum i40e_status_code
9767 i40e_dcb_hw_configure(struct i40e_pf *pf,
9768                       struct i40e_dcbx_config *new_cfg,
9769                       uint8_t tc_map)
9770 {
9771         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9772         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9773         struct i40e_vsi *main_vsi = pf->main_vsi;
9774         struct i40e_vsi_list *vsi_list;
9775         enum i40e_status_code ret;
9776         int i;
9777         uint32_t val;
9778
9779         /* Use the FW API if FW > v4.4*/
9780         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9781               (hw->aq.fw_maj_ver >= 5))) {
9782                 PMD_INIT_LOG(ERR,
9783                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9784                 return I40E_ERR_FIRMWARE_API_VERSION;
9785         }
9786
9787         /* Check if need reconfiguration */
9788         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9789                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9790                 return I40E_SUCCESS;
9791         }
9792
9793         /* Copy the new config to the current config */
9794         *old_cfg = *new_cfg;
9795         old_cfg->etsrec = old_cfg->etscfg;
9796         ret = i40e_set_dcb_config(hw);
9797         if (ret) {
9798                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9799                          i40e_stat_str(hw, ret),
9800                          i40e_aq_str(hw, hw->aq.asq_last_status));
9801                 return ret;
9802         }
9803         /* set receive Arbiter to RR mode and ETS scheme by default */
9804         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9805                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9806                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9807                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9808                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9809                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9810                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9811                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9812                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9813                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9814                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9815                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9816                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9817         }
9818         /* get local mib to check whether it is configured correctly */
9819         /* IEEE mode */
9820         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9821         /* Get Local DCB Config */
9822         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9823                                      &hw->local_dcbx_config);
9824
9825         /* if Veb is created, need to update TC of it at first */
9826         if (main_vsi->veb) {
9827                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9828                 if (ret)
9829                         PMD_INIT_LOG(WARNING,
9830                                  "Failed configuring TC for VEB seid=%d",
9831                                  main_vsi->veb->seid);
9832         }
9833         /* Update each VSI */
9834         i40e_vsi_config_tc(main_vsi, tc_map);
9835         if (main_vsi->veb) {
9836                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9837                         /* Beside main VSI and VMDQ VSIs, only enable default
9838                          * TC for other VSIs
9839                          */
9840                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9841                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9842                                                          tc_map);
9843                         else
9844                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9845                                                          I40E_DEFAULT_TCMAP);
9846                         if (ret)
9847                                 PMD_INIT_LOG(WARNING,
9848                                         "Failed configuring TC for VSI seid=%d",
9849                                         vsi_list->vsi->seid);
9850                         /* continue */
9851                 }
9852         }
9853         return I40E_SUCCESS;
9854 }
9855
9856 /*
9857  * i40e_dcb_init_configure - initial dcb config
9858  * @dev: device being configured
9859  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9860  *
9861  * Returns 0 on success, negative value on failure
9862  */
9863 static int
9864 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9865 {
9866         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9868         int ret = 0;
9869
9870         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9871                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9872                 return -ENOTSUP;
9873         }
9874
9875         /* DCB initialization:
9876          * Update DCB configuration from the Firmware and configure
9877          * LLDP MIB change event.
9878          */
9879         if (sw_dcb == TRUE) {
9880                 ret = i40e_init_dcb(hw);
9881                 /* If lldp agent is stopped, the return value from
9882                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9883                  * adminq status. Otherwise, it should return success.
9884                  */
9885                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9886                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9887                         memset(&hw->local_dcbx_config, 0,
9888                                 sizeof(struct i40e_dcbx_config));
9889                         /* set dcb default configuration */
9890                         hw->local_dcbx_config.etscfg.willing = 0;
9891                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9892                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9893                         hw->local_dcbx_config.etscfg.tsatable[0] =
9894                                                 I40E_IEEE_TSA_ETS;
9895                         hw->local_dcbx_config.etsrec =
9896                                 hw->local_dcbx_config.etscfg;
9897                         hw->local_dcbx_config.pfc.willing = 0;
9898                         hw->local_dcbx_config.pfc.pfccap =
9899                                                 I40E_MAX_TRAFFIC_CLASS;
9900                         /* FW needs one App to configure HW */
9901                         hw->local_dcbx_config.numapps = 1;
9902                         hw->local_dcbx_config.app[0].selector =
9903                                                 I40E_APP_SEL_ETHTYPE;
9904                         hw->local_dcbx_config.app[0].priority = 3;
9905                         hw->local_dcbx_config.app[0].protocolid =
9906                                                 I40E_APP_PROTOID_FCOE;
9907                         ret = i40e_set_dcb_config(hw);
9908                         if (ret) {
9909                                 PMD_INIT_LOG(ERR,
9910                                         "default dcb config fails. err = %d, aq_err = %d.",
9911                                         ret, hw->aq.asq_last_status);
9912                                 return -ENOSYS;
9913                         }
9914                 } else {
9915                         PMD_INIT_LOG(ERR,
9916                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9917                                 ret, hw->aq.asq_last_status);
9918                         return -ENOTSUP;
9919                 }
9920         } else {
9921                 ret = i40e_aq_start_lldp(hw, NULL);
9922                 if (ret != I40E_SUCCESS)
9923                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9924
9925                 ret = i40e_init_dcb(hw);
9926                 if (!ret) {
9927                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9928                                 PMD_INIT_LOG(ERR,
9929                                         "HW doesn't support DCBX offload.");
9930                                 return -ENOTSUP;
9931                         }
9932                 } else {
9933                         PMD_INIT_LOG(ERR,
9934                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9935                                 ret, hw->aq.asq_last_status);
9936                         return -ENOTSUP;
9937                 }
9938         }
9939         return 0;
9940 }
9941
9942 /*
9943  * i40e_dcb_setup - setup dcb related config
9944  * @dev: device being configured
9945  *
9946  * Returns 0 on success, negative value on failure
9947  */
9948 static int
9949 i40e_dcb_setup(struct rte_eth_dev *dev)
9950 {
9951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9952         struct i40e_dcbx_config dcb_cfg;
9953         uint8_t tc_map = 0;
9954         int ret = 0;
9955
9956         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9957                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9958                 return -ENOTSUP;
9959         }
9960
9961         if (pf->vf_num != 0)
9962                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9963
9964         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9965         if (ret) {
9966                 PMD_INIT_LOG(ERR, "invalid dcb config");
9967                 return -EINVAL;
9968         }
9969         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9970         if (ret) {
9971                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9972                 return -ENOSYS;
9973         }
9974
9975         return 0;
9976 }
9977
9978 static int
9979 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9980                       struct rte_eth_dcb_info *dcb_info)
9981 {
9982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9984         struct i40e_vsi *vsi = pf->main_vsi;
9985         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9986         uint16_t bsf, tc_mapping;
9987         int i, j = 0;
9988
9989         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9990                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9991         else
9992                 dcb_info->nb_tcs = 1;
9993         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9994                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9995         for (i = 0; i < dcb_info->nb_tcs; i++)
9996                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9997
9998         /* get queue mapping if vmdq is disabled */
9999         if (!pf->nb_cfg_vmdq_vsi) {
10000                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10001                         if (!(vsi->enabled_tc & (1 << i)))
10002                                 continue;
10003                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10004                         dcb_info->tc_queue.tc_rxq[j][i].base =
10005                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10006                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10007                         dcb_info->tc_queue.tc_txq[j][i].base =
10008                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10009                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10010                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10011                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10012                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10013                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10014                 }
10015                 return 0;
10016         }
10017
10018         /* get queue mapping if vmdq is enabled */
10019         do {
10020                 vsi = pf->vmdq[j].vsi;
10021                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10022                         if (!(vsi->enabled_tc & (1 << i)))
10023                                 continue;
10024                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10025                         dcb_info->tc_queue.tc_rxq[j][i].base =
10026                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10027                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10028                         dcb_info->tc_queue.tc_txq[j][i].base =
10029                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10030                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10031                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10032                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10033                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10034                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10035                 }
10036                 j++;
10037         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10038         return 0;
10039 }
10040
10041 static int
10042 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10043 {
10044         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10045         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10046         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10047         uint16_t interval =
10048                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10049         uint16_t msix_intr;
10050
10051         msix_intr = intr_handle->intr_vec[queue_id];
10052         if (msix_intr == I40E_MISC_VEC_ID)
10053                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10054                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10055                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10056                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10057                                (interval <<
10058                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10059         else
10060                 I40E_WRITE_REG(hw,
10061                                I40E_PFINT_DYN_CTLN(msix_intr -
10062                                                    I40E_RX_VEC_START),
10063                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10064                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10065                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10066                                (interval <<
10067                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10068
10069         I40E_WRITE_FLUSH(hw);
10070         rte_intr_enable(&pci_dev->intr_handle);
10071
10072         return 0;
10073 }
10074
10075 static int
10076 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10077 {
10078         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10079         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10081         uint16_t msix_intr;
10082
10083         msix_intr = intr_handle->intr_vec[queue_id];
10084         if (msix_intr == I40E_MISC_VEC_ID)
10085                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10086         else
10087                 I40E_WRITE_REG(hw,
10088                                I40E_PFINT_DYN_CTLN(msix_intr -
10089                                                    I40E_RX_VEC_START),
10090                                0);
10091         I40E_WRITE_FLUSH(hw);
10092
10093         return 0;
10094 }
10095
10096 static int i40e_get_regs(struct rte_eth_dev *dev,
10097                          struct rte_dev_reg_info *regs)
10098 {
10099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10100         uint32_t *ptr_data = regs->data;
10101         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10102         const struct i40e_reg_info *reg_info;
10103
10104         if (ptr_data == NULL) {
10105                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10106                 regs->width = sizeof(uint32_t);
10107                 return 0;
10108         }
10109
10110         /* The first few registers have to be read using AQ operations */
10111         reg_idx = 0;
10112         while (i40e_regs_adminq[reg_idx].name) {
10113                 reg_info = &i40e_regs_adminq[reg_idx++];
10114                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10115                         for (arr_idx2 = 0;
10116                                         arr_idx2 <= reg_info->count2;
10117                                         arr_idx2++) {
10118                                 reg_offset = arr_idx * reg_info->stride1 +
10119                                         arr_idx2 * reg_info->stride2;
10120                                 reg_offset += reg_info->base_addr;
10121                                 ptr_data[reg_offset >> 2] =
10122                                         i40e_read_rx_ctl(hw, reg_offset);
10123                         }
10124         }
10125
10126         /* The remaining registers can be read using primitives */
10127         reg_idx = 0;
10128         while (i40e_regs_others[reg_idx].name) {
10129                 reg_info = &i40e_regs_others[reg_idx++];
10130                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10131                         for (arr_idx2 = 0;
10132                                         arr_idx2 <= reg_info->count2;
10133                                         arr_idx2++) {
10134                                 reg_offset = arr_idx * reg_info->stride1 +
10135                                         arr_idx2 * reg_info->stride2;
10136                                 reg_offset += reg_info->base_addr;
10137                                 ptr_data[reg_offset >> 2] =
10138                                         I40E_READ_REG(hw, reg_offset);
10139                         }
10140         }
10141
10142         return 0;
10143 }
10144
10145 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10146 {
10147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10148
10149         /* Convert word count to byte count */
10150         return hw->nvm.sr_size << 1;
10151 }
10152
10153 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10154                            struct rte_dev_eeprom_info *eeprom)
10155 {
10156         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10157         uint16_t *data = eeprom->data;
10158         uint16_t offset, length, cnt_words;
10159         int ret_code;
10160
10161         offset = eeprom->offset >> 1;
10162         length = eeprom->length >> 1;
10163         cnt_words = length;
10164
10165         if (offset > hw->nvm.sr_size ||
10166                 offset + length > hw->nvm.sr_size) {
10167                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10168                 return -EINVAL;
10169         }
10170
10171         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10172
10173         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10174         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10175                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10176                 return -EIO;
10177         }
10178
10179         return 0;
10180 }
10181
10182 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10183                                       struct ether_addr *mac_addr)
10184 {
10185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10186
10187         if (!is_valid_assigned_ether_addr(mac_addr)) {
10188                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10189                 return;
10190         }
10191
10192         /* Flags: 0x3 updates port address */
10193         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10194 }
10195
10196 static int
10197 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10198 {
10199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10200         struct rte_eth_dev_data *dev_data = pf->dev_data;
10201         uint32_t frame_size = mtu + ETHER_HDR_LEN
10202                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10203         int ret = 0;
10204
10205         /* check if mtu is within the allowed range */
10206         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10207                 return -EINVAL;
10208
10209         /* mtu setting is forbidden if port is start */
10210         if (dev_data->dev_started) {
10211                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10212                             dev_data->port_id);
10213                 return -EBUSY;
10214         }
10215
10216         if (frame_size > ETHER_MAX_LEN)
10217                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10218         else
10219                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10220
10221         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10222
10223         return ret;
10224 }
10225
10226 /* Restore ethertype filter */
10227 static void
10228 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10229 {
10230         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10231         struct i40e_ethertype_filter_list
10232                 *ethertype_list = &pf->ethertype.ethertype_list;
10233         struct i40e_ethertype_filter *f;
10234         struct i40e_control_filter_stats stats;
10235         uint16_t flags;
10236
10237         TAILQ_FOREACH(f, ethertype_list, rules) {
10238                 flags = 0;
10239                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10240                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10241                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10242                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10243                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10244
10245                 memset(&stats, 0, sizeof(stats));
10246                 i40e_aq_add_rem_control_packet_filter(hw,
10247                                             f->input.mac_addr.addr_bytes,
10248                                             f->input.ether_type,
10249                                             flags, pf->main_vsi->seid,
10250                                             f->queue, 1, &stats, NULL);
10251         }
10252         PMD_DRV_LOG(INFO, "Ethertype filter:"
10253                     " mac_etype_used = %u, etype_used = %u,"
10254                     " mac_etype_free = %u, etype_free = %u",
10255                     stats.mac_etype_used, stats.etype_used,
10256                     stats.mac_etype_free, stats.etype_free);
10257 }
10258
10259 /* Restore tunnel filter */
10260 static void
10261 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10262 {
10263         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10264         struct i40e_vsi *vsi = pf->main_vsi;
10265         struct i40e_tunnel_filter_list
10266                 *tunnel_list = &pf->tunnel.tunnel_list;
10267         struct i40e_tunnel_filter *f;
10268         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10269
10270         TAILQ_FOREACH(f, tunnel_list, rules) {
10271                 memset(&cld_filter, 0, sizeof(cld_filter));
10272                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10273                 cld_filter.queue_number = f->queue;
10274                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10275         }
10276 }
10277
10278 static void
10279 i40e_filter_restore(struct i40e_pf *pf)
10280 {
10281         i40e_ethertype_filter_restore(pf);
10282         i40e_tunnel_filter_restore(pf);
10283         i40e_fdir_filter_restore(pf);
10284 }
10285
10286 static bool
10287 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10288 {
10289         if (strcmp(dev->driver->pci_drv.driver.name,
10290                    drv->pci_drv.driver.name))
10291                 return false;
10292
10293         return true;
10294 }
10295
10296 int
10297 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10298 {
10299         struct rte_eth_dev *dev;
10300         struct i40e_pf *pf;
10301
10302         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10303
10304         dev = &rte_eth_devices[port];
10305
10306         if (!is_device_supported(dev, &rte_i40e_pmd))
10307                 return -ENOTSUP;
10308
10309         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10310
10311         if (vf >= pf->vf_num || !pf->vfs) {
10312                 PMD_DRV_LOG(ERR, "Invalid argument.");
10313                 return -EINVAL;
10314         }
10315
10316         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10317
10318         return 0;
10319 }
10320
10321 int
10322 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10323 {
10324         struct rte_eth_dev *dev;
10325         struct i40e_pf *pf;
10326         struct i40e_vsi *vsi;
10327         struct i40e_hw *hw;
10328         struct i40e_vsi_context ctxt;
10329         int ret;
10330
10331         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10332
10333         dev = &rte_eth_devices[port];
10334
10335         if (!is_device_supported(dev, &rte_i40e_pmd))
10336                 return -ENOTSUP;
10337
10338         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10339
10340         if (vf_id >= pf->vf_num || !pf->vfs) {
10341                 PMD_DRV_LOG(ERR, "Invalid argument.");
10342                 return -EINVAL;
10343         }
10344
10345         vsi = pf->vfs[vf_id].vsi;
10346         if (!vsi) {
10347                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10348                 return -EINVAL;
10349         }
10350
10351         /* Check if it has been already on or off */
10352         if (vsi->info.valid_sections &
10353                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10354                 if (on) {
10355                         if ((vsi->info.sec_flags &
10356                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10357                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10358                                 return 0; /* already on */
10359                 } else {
10360                         if ((vsi->info.sec_flags &
10361                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10362                                 return 0; /* already off */
10363                 }
10364         }
10365
10366         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10367         if (on)
10368                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10369         else
10370                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10371
10372         memset(&ctxt, 0, sizeof(ctxt));
10373         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10374         ctxt.seid = vsi->seid;
10375
10376         hw = I40E_VSI_TO_HW(vsi);
10377         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10378         if (ret != I40E_SUCCESS) {
10379                 ret = -ENOTSUP;
10380                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10381         }
10382
10383         return ret;
10384 }
10385
10386 static int
10387 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10388 {
10389         uint32_t j, k;
10390         uint16_t vlan_id;
10391         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10392         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10393         int ret;
10394
10395         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10396                 if (!vsi->vfta[j])
10397                         continue;
10398
10399                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10400                         if (!(vsi->vfta[j] & (1 << k)))
10401                                 continue;
10402
10403                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10404                         if (!vlan_id)
10405                                 continue;
10406
10407                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10408                         if (add)
10409                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10410                                                        &vlan_data, 1, NULL);
10411                         else
10412                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10413                                                           &vlan_data, 1, NULL);
10414                         if (ret != I40E_SUCCESS) {
10415                                 PMD_DRV_LOG(ERR,
10416                                             "Failed to add/rm vlan filter");
10417                                 return ret;
10418                         }
10419                 }
10420         }
10421
10422         return I40E_SUCCESS;
10423 }
10424
10425 int
10426 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10427 {
10428         struct rte_eth_dev *dev;
10429         struct i40e_pf *pf;
10430         struct i40e_vsi *vsi;
10431         struct i40e_hw *hw;
10432         struct i40e_vsi_context ctxt;
10433         int ret;
10434
10435         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10436
10437         dev = &rte_eth_devices[port];
10438
10439         if (!is_device_supported(dev, &rte_i40e_pmd))
10440                 return -ENOTSUP;
10441
10442         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10443
10444         if (vf_id >= pf->vf_num || !pf->vfs) {
10445                 PMD_DRV_LOG(ERR, "Invalid argument.");
10446                 return -EINVAL;
10447         }
10448
10449         vsi = pf->vfs[vf_id].vsi;
10450         if (!vsi) {
10451                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10452                 return -EINVAL;
10453         }
10454
10455         /* Check if it has been already on or off */
10456         if (vsi->vlan_anti_spoof_on == on)
10457                 return 0; /* already on or off */
10458
10459         vsi->vlan_anti_spoof_on = on;
10460         ret = i40e_add_rm_all_vlan_filter(vsi, on);
10461         if (ret) {
10462                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10463                 return -ENOTSUP;
10464         }
10465
10466         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10467         if (on)
10468                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10469         else
10470                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10471
10472         memset(&ctxt, 0, sizeof(ctxt));
10473         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10474         ctxt.seid = vsi->seid;
10475
10476         hw = I40E_VSI_TO_HW(vsi);
10477         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10478         if (ret != I40E_SUCCESS) {
10479                 ret = -ENOTSUP;
10480                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10481         }
10482
10483         return ret;
10484 }
10485
10486 static int
10487 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10488 {
10489         struct i40e_mac_filter *f;
10490         struct i40e_macvlan_filter *mv_f;
10491         int i, vlan_num;
10492         enum rte_mac_filter_type filter_type;
10493         int ret = I40E_SUCCESS;
10494         void *temp;
10495
10496         /* remove all the MACs */
10497         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10498                 vlan_num = vsi->vlan_num;
10499                 filter_type = f->mac_info.filter_type;
10500                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10501                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10502                         if (vlan_num == 0) {
10503                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10504                                 return I40E_ERR_PARAM;
10505                         }
10506                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10507                            filter_type == RTE_MAC_HASH_MATCH)
10508                         vlan_num = 1;
10509
10510                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10511                 if (!mv_f) {
10512                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10513                         return I40E_ERR_NO_MEMORY;
10514                 }
10515
10516                 for (i = 0; i < vlan_num; i++) {
10517                         mv_f[i].filter_type = filter_type;
10518                         (void)rte_memcpy(&mv_f[i].macaddr,
10519                                          &f->mac_info.mac_addr,
10520                                          ETH_ADDR_LEN);
10521                 }
10522                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10523                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10524                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10525                                                          &f->mac_info.mac_addr);
10526                         if (ret != I40E_SUCCESS) {
10527                                 rte_free(mv_f);
10528                                 return ret;
10529                         }
10530                 }
10531
10532                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10533                 if (ret != I40E_SUCCESS) {
10534                         rte_free(mv_f);
10535                         return ret;
10536                 }
10537
10538                 rte_free(mv_f);
10539                 ret = I40E_SUCCESS;
10540         }
10541
10542         return ret;
10543 }
10544
10545 static int
10546 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10547 {
10548         struct i40e_mac_filter *f;
10549         struct i40e_macvlan_filter *mv_f;
10550         int i, vlan_num = 0;
10551         int ret = I40E_SUCCESS;
10552         void *temp;
10553
10554         /* restore all the MACs */
10555         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10556                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10557                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10558                         /**
10559                          * If vlan_num is 0, that's the first time to add mac,
10560                          * set mask for vlan_id 0.
10561                          */
10562                         if (vsi->vlan_num == 0) {
10563                                 i40e_set_vlan_filter(vsi, 0, 1);
10564                                 vsi->vlan_num = 1;
10565                         }
10566                         vlan_num = vsi->vlan_num;
10567                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10568                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10569                         vlan_num = 1;
10570
10571                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10572                 if (!mv_f) {
10573                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10574                         return I40E_ERR_NO_MEMORY;
10575                 }
10576
10577                 for (i = 0; i < vlan_num; i++) {
10578                         mv_f[i].filter_type = f->mac_info.filter_type;
10579                         (void)rte_memcpy(&mv_f[i].macaddr,
10580                                          &f->mac_info.mac_addr,
10581                                          ETH_ADDR_LEN);
10582                 }
10583
10584                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10585                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10586                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10587                                                          &f->mac_info.mac_addr);
10588                         if (ret != I40E_SUCCESS) {
10589                                 rte_free(mv_f);
10590                                 return ret;
10591                         }
10592                 }
10593
10594                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10595                 if (ret != I40E_SUCCESS) {
10596                         rte_free(mv_f);
10597                         return ret;
10598                 }
10599
10600                 rte_free(mv_f);
10601                 ret = I40E_SUCCESS;
10602         }
10603
10604         return ret;
10605 }
10606
10607 static int
10608 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10609 {
10610         struct i40e_vsi_context ctxt;
10611         struct i40e_hw *hw;
10612         int ret;
10613
10614         if (!vsi)
10615                 return -EINVAL;
10616
10617         hw = I40E_VSI_TO_HW(vsi);
10618
10619         /* Use the FW API if FW >= v5.0 */
10620         if (hw->aq.fw_maj_ver < 5) {
10621                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10622                 return -ENOTSUP;
10623         }
10624
10625         /* Check if it has been already on or off */
10626         if (vsi->info.valid_sections &
10627                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10628                 if (on) {
10629                         if ((vsi->info.switch_id &
10630                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10631                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10632                                 return 0; /* already on */
10633                 } else {
10634                         if ((vsi->info.switch_id &
10635                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10636                                 return 0; /* already off */
10637                 }
10638         }
10639
10640         /* remove all the MAC and VLAN first */
10641         ret = i40e_vsi_rm_mac_filter(vsi);
10642         if (ret) {
10643                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10644                 return ret;
10645         }
10646         if (vsi->vlan_anti_spoof_on) {
10647                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10648                 if (ret) {
10649                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10650                         return ret;
10651                 }
10652         }
10653
10654         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10655         if (on)
10656                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10657         else
10658                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10659
10660         memset(&ctxt, 0, sizeof(ctxt));
10661         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10662         ctxt.seid = vsi->seid;
10663
10664         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10665         if (ret != I40E_SUCCESS) {
10666                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10667                 return ret;
10668         }
10669
10670         /* add all the MAC and VLAN back */
10671         ret = i40e_vsi_restore_mac_filter(vsi);
10672         if (ret)
10673                 return ret;
10674         if (vsi->vlan_anti_spoof_on) {
10675                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10676                 if (ret)
10677                         return ret;
10678         }
10679
10680         return ret;
10681 }
10682
10683 int
10684 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10685 {
10686         struct rte_eth_dev *dev;
10687         struct i40e_pf *pf;
10688         struct i40e_pf_vf *vf;
10689         struct i40e_vsi *vsi;
10690         uint16_t vf_id;
10691         int ret;
10692
10693         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10694
10695         dev = &rte_eth_devices[port];
10696
10697         if (!is_device_supported(dev, &rte_i40e_pmd))
10698                 return -ENOTSUP;
10699
10700         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10701
10702         /* setup PF TX loopback */
10703         vsi = pf->main_vsi;
10704         ret = i40e_vsi_set_tx_loopback(vsi, on);
10705         if (ret)
10706                 return -ENOTSUP;
10707
10708         /* setup TX loopback for all the VFs */
10709         if (!pf->vfs) {
10710                 /* if no VF, do nothing. */
10711                 return 0;
10712         }
10713
10714         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10715                 vf = &pf->vfs[vf_id];
10716                 vsi = vf->vsi;
10717
10718                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10719                 if (ret)
10720                         return -ENOTSUP;
10721         }
10722
10723         return ret;
10724 }
10725
10726 int
10727 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10728 {
10729         struct rte_eth_dev *dev;
10730         struct i40e_pf *pf;
10731         struct i40e_vsi *vsi;
10732         struct i40e_hw *hw;
10733         int ret;
10734
10735         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10736
10737         dev = &rte_eth_devices[port];
10738
10739         if (!is_device_supported(dev, &rte_i40e_pmd))
10740                 return -ENOTSUP;
10741
10742         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10743
10744         if (vf_id >= pf->vf_num || !pf->vfs) {
10745                 PMD_DRV_LOG(ERR, "Invalid argument.");
10746                 return -EINVAL;
10747         }
10748
10749         vsi = pf->vfs[vf_id].vsi;
10750         if (!vsi) {
10751                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10752                 return -EINVAL;
10753         }
10754
10755         hw = I40E_VSI_TO_HW(vsi);
10756
10757         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10758                                                   on, NULL, true);
10759         if (ret != I40E_SUCCESS) {
10760                 ret = -ENOTSUP;
10761                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10762         }
10763
10764         return ret;
10765 }
10766
10767 int
10768 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10769 {
10770         struct rte_eth_dev *dev;
10771         struct i40e_pf *pf;
10772         struct i40e_vsi *vsi;
10773         struct i40e_hw *hw;
10774         int ret;
10775
10776         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10777
10778         dev = &rte_eth_devices[port];
10779
10780         if (!is_device_supported(dev, &rte_i40e_pmd))
10781                 return -ENOTSUP;
10782
10783         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10784
10785         if (vf_id >= pf->vf_num || !pf->vfs) {
10786                 PMD_DRV_LOG(ERR, "Invalid argument.");
10787                 return -EINVAL;
10788         }
10789
10790         vsi = pf->vfs[vf_id].vsi;
10791         if (!vsi) {
10792                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10793                 return -EINVAL;
10794         }
10795
10796         hw = I40E_VSI_TO_HW(vsi);
10797
10798         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10799                                                     on, NULL);
10800         if (ret != I40E_SUCCESS) {
10801                 ret = -ENOTSUP;
10802                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10803         }
10804
10805         return ret;
10806 }
10807
10808 int
10809 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10810                              struct ether_addr *mac_addr)
10811 {
10812         struct i40e_mac_filter *f;
10813         struct rte_eth_dev *dev;
10814         struct i40e_pf_vf *vf;
10815         struct i40e_vsi *vsi;
10816         struct i40e_pf *pf;
10817         void *temp;
10818
10819         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10820                 return -EINVAL;
10821
10822         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10823
10824         dev = &rte_eth_devices[port];
10825
10826         if (!is_device_supported(dev, &rte_i40e_pmd))
10827                 return -ENOTSUP;
10828
10829         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10830
10831         if (vf_id >= pf->vf_num || !pf->vfs)
10832                 return -EINVAL;
10833
10834         vf = &pf->vfs[vf_id];
10835         vsi = vf->vsi;
10836         if (!vsi) {
10837                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10838                 return -EINVAL;
10839         }
10840
10841         ether_addr_copy(mac_addr, &vf->mac_addr);
10842
10843         /* Remove all existing mac */
10844         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10845                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10846
10847         return 0;
10848 }
10849
10850 /* Set vlan strip on/off for specific VF from host */
10851 int
10852 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10853 {
10854         struct rte_eth_dev *dev;
10855         struct i40e_pf *pf;
10856         struct i40e_vsi *vsi;
10857         int ret;
10858
10859         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10860
10861         dev = &rte_eth_devices[port];
10862
10863         if (!is_device_supported(dev, &rte_i40e_pmd))
10864                 return -ENOTSUP;
10865
10866         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10867
10868         if (vf_id >= pf->vf_num || !pf->vfs) {
10869                 PMD_DRV_LOG(ERR, "Invalid argument.");
10870                 return -EINVAL;
10871         }
10872
10873         vsi = pf->vfs[vf_id].vsi;
10874
10875         if (!vsi)
10876                 return -EINVAL;
10877
10878         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10879         if (ret != I40E_SUCCESS) {
10880                 ret = -ENOTSUP;
10881                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10882         }
10883
10884         return ret;
10885 }
10886
10887 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10888                                     uint16_t vlan_id)
10889 {
10890         struct rte_eth_dev *dev;
10891         struct i40e_pf *pf;
10892         struct i40e_hw *hw;
10893         struct i40e_vsi *vsi;
10894         struct i40e_vsi_context ctxt;
10895         int ret;
10896
10897         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10898
10899         if (vlan_id > ETHER_MAX_VLAN_ID) {
10900                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10901                 return -EINVAL;
10902         }
10903
10904         dev = &rte_eth_devices[port];
10905
10906         if (!is_device_supported(dev, &rte_i40e_pmd))
10907                 return -ENOTSUP;
10908
10909         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10910         hw = I40E_PF_TO_HW(pf);
10911
10912         /**
10913          * return -ENODEV if SRIOV not enabled, VF number not configured
10914          * or no queue assigned.
10915          */
10916         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10917             pf->vf_nb_qps == 0)
10918                 return -ENODEV;
10919
10920         if (vf_id >= pf->vf_num || !pf->vfs) {
10921                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10922                 return -EINVAL;
10923         }
10924
10925         vsi = pf->vfs[vf_id].vsi;
10926         if (!vsi) {
10927                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10928                 return -EINVAL;
10929         }
10930
10931         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10932         vsi->info.pvid = vlan_id;
10933         if (vlan_id > 0)
10934                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10935         else
10936                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10937
10938         memset(&ctxt, 0, sizeof(ctxt));
10939         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10940         ctxt.seid = vsi->seid;
10941
10942         hw = I40E_VSI_TO_HW(vsi);
10943         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10944         if (ret != I40E_SUCCESS) {
10945                 ret = -ENOTSUP;
10946                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10947         }
10948
10949         return ret;
10950 }
10951
10952 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10953                                   uint8_t on)
10954 {
10955         struct rte_eth_dev *dev;
10956         struct i40e_pf *pf;
10957         struct i40e_vsi *vsi;
10958         struct i40e_hw *hw;
10959         int ret;
10960
10961         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10962
10963         if (on > 1) {
10964                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10965                 return -EINVAL;
10966         }
10967
10968         dev = &rte_eth_devices[port];
10969
10970         if (!is_device_supported(dev, &rte_i40e_pmd))
10971                 return -ENOTSUP;
10972
10973         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10974         hw = I40E_PF_TO_HW(pf);
10975
10976         if (vf_id >= pf->vf_num || !pf->vfs) {
10977                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10978                 return -EINVAL;
10979         }
10980
10981         /**
10982          * return -ENODEV if SRIOV not enabled, VF number not configured
10983          * or no queue assigned.
10984          */
10985         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10986             pf->vf_nb_qps == 0) {
10987                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
10988                 return -ENODEV;
10989         }
10990
10991         vsi = pf->vfs[vf_id].vsi;
10992         if (!vsi) {
10993                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10994                 return -EINVAL;
10995         }
10996
10997         hw = I40E_VSI_TO_HW(vsi);
10998
10999         ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, on, NULL);
11000         if (ret != I40E_SUCCESS) {
11001                 ret = -ENOTSUP;
11002                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11003         }
11004
11005         return ret;
11006 }
11007
11008 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11009 {
11010         struct rte_eth_dev *dev;
11011         struct i40e_pf *pf;
11012         struct i40e_hw *hw;
11013         struct i40e_vsi *vsi;
11014         struct i40e_vsi_context ctxt;
11015         int ret;
11016
11017         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11018
11019         if (on > 1) {
11020                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11021                 return -EINVAL;
11022         }
11023
11024         dev = &rte_eth_devices[port];
11025
11026         if (!is_device_supported(dev, &rte_i40e_pmd))
11027                 return -ENOTSUP;
11028
11029         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11030         hw = I40E_PF_TO_HW(pf);
11031
11032         /**
11033          * return -ENODEV if SRIOV not enabled, VF number not configured
11034          * or no queue assigned.
11035          */
11036         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11037             pf->vf_nb_qps == 0) {
11038                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11039                 return -ENODEV;
11040         }
11041
11042         if (vf_id >= pf->vf_num || !pf->vfs) {
11043                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11044                 return -EINVAL;
11045         }
11046
11047         vsi = pf->vfs[vf_id].vsi;
11048         if (!vsi) {
11049                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11050                 return -EINVAL;
11051         }
11052
11053         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11054         if (on) {
11055                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11056                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11057         } else {
11058                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11059                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11060         }
11061
11062         memset(&ctxt, 0, sizeof(ctxt));
11063         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11064         ctxt.seid = vsi->seid;
11065
11066         hw = I40E_VSI_TO_HW(vsi);
11067         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11068         if (ret != I40E_SUCCESS) {
11069                 ret = -ENOTSUP;
11070                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11071         }
11072
11073         return ret;
11074 }
11075
11076 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11077                                     uint64_t vf_mask, uint8_t on)
11078 {
11079         struct rte_eth_dev *dev;
11080         struct i40e_pf *pf;
11081         struct i40e_hw *hw;
11082         uint16_t vf_idx;
11083         int ret = I40E_SUCCESS;
11084
11085         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11086
11087         dev = &rte_eth_devices[port];
11088
11089         if (!is_device_supported(dev, &rte_i40e_pmd))
11090                 return -ENOTSUP;
11091
11092         if (vlan_id > ETHER_MAX_VLAN_ID) {
11093                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11094                 return -EINVAL;
11095         }
11096
11097         if (vf_mask == 0) {
11098                 PMD_DRV_LOG(ERR, "No VF.");
11099                 return -EINVAL;
11100         }
11101
11102         if (on > 1) {
11103                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11104                 return -EINVAL;
11105         }
11106
11107         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11108         hw = I40E_PF_TO_HW(pf);
11109
11110         /**
11111          * return -ENODEV if SRIOV not enabled, VF number not configured
11112          * or no queue assigned.
11113          */
11114         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11115             pf->vf_nb_qps == 0) {
11116                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11117                 return -ENODEV;
11118         }
11119
11120         for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11121                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11122                         if (on)
11123                                 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11124                                                         vlan_id);
11125                         else
11126                                 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11127                                                            vlan_id);
11128                 }
11129         }
11130
11131         if (ret != I40E_SUCCESS) {
11132                 ret = -ENOTSUP;
11133                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11134         }
11135
11136         return ret;
11137 }
11138
11139 int
11140 rte_pmd_i40e_get_vf_stats(uint8_t port,
11141                           uint16_t vf_id,
11142                           struct rte_eth_stats *stats)
11143 {
11144         struct rte_eth_dev *dev;
11145         struct i40e_pf *pf;
11146         struct i40e_vsi *vsi;
11147
11148         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11149
11150         dev = &rte_eth_devices[port];
11151
11152         if (!is_device_supported(dev, &rte_i40e_pmd))
11153                 return -ENOTSUP;
11154
11155         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11156
11157         if (vf_id >= pf->vf_num || !pf->vfs) {
11158                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11159                 return -EINVAL;
11160         }
11161
11162         vsi = pf->vfs[vf_id].vsi;
11163         if (!vsi) {
11164                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11165                 return -EINVAL;
11166         }
11167
11168         i40e_update_vsi_stats(vsi);
11169
11170         stats->ipackets = vsi->eth_stats.rx_unicast +
11171                         vsi->eth_stats.rx_multicast +
11172                         vsi->eth_stats.rx_broadcast;
11173         stats->opackets = vsi->eth_stats.tx_unicast +
11174                         vsi->eth_stats.tx_multicast +
11175                         vsi->eth_stats.tx_broadcast;
11176         stats->ibytes   = vsi->eth_stats.rx_bytes;
11177         stats->obytes   = vsi->eth_stats.tx_bytes;
11178         stats->ierrors  = vsi->eth_stats.rx_discards;
11179         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11180
11181         return 0;
11182 }
11183
11184 int
11185 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11186                             uint16_t vf_id)
11187 {
11188         struct rte_eth_dev *dev;
11189         struct i40e_pf *pf;
11190         struct i40e_vsi *vsi;
11191
11192         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11193
11194         dev = &rte_eth_devices[port];
11195
11196         if (!is_device_supported(dev, &rte_i40e_pmd))
11197                 return -ENOTSUP;
11198
11199         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11200
11201         if (vf_id >= pf->vf_num || !pf->vfs) {
11202                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11203                 return -EINVAL;
11204         }
11205
11206         vsi = pf->vfs[vf_id].vsi;
11207         if (!vsi) {
11208                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11209                 return -EINVAL;
11210         }
11211
11212         vsi->offset_loaded = false;
11213         i40e_update_vsi_stats(vsi);
11214
11215         return 0;
11216 }