net/i40e: implement descriptor status API
authorOlivier Matz <olivier.matz@6wind.com>
Wed, 29 Mar 2017 08:36:33 +0000 (10:36 +0200)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Thu, 30 Mar 2017 13:27:42 +0000 (15:27 +0200)
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
doc/guides/nics/features/i40e.ini
doc/guides/nics/features/i40e_vec.ini
doc/guides/nics/features/i40e_vf.ini
doc/guides/nics/features/i40e_vf_vec.ini
drivers/net/i40e/i40e_ethdev.c
drivers/net/i40e/i40e_ethdev_vf.c
drivers/net/i40e/i40e_rxtx.c
drivers/net/i40e/i40e_rxtx.h

index 6d11cce..c8bfdc5 100644 (file)
@@ -38,6 +38,8 @@ Inner L3 checksum    = Y
 Inner L4 checksum    = Y
 Packet type parsing  = Y
 Timesync             = Y
+Rx descriptor status = Y
+Tx descriptor status = Y
 Basic stats          = Y
 Extended stats       = Y
 FW version           = Y
index edd6b71..6fe62df 100644 (file)
@@ -29,6 +29,8 @@ Flow director        = Y
 Flow control         = Y
 Traffic mirroring    = Y
 Timesync             = Y
+Rx descriptor status = Y
+Tx descriptor status = Y
 Basic stats          = Y
 Extended stats       = Y
 Multiprocess aware   = Y
index 2f82c6b..46e0d9f 100644 (file)
@@ -26,6 +26,8 @@ L4 checksum offload  = Y
 Inner L3 checksum    = Y
 Inner L4 checksum    = Y
 Packet type parsing  = Y
+Rx descriptor status = Y
+Tx descriptor status = Y
 Basic stats          = Y
 Extended stats       = Y
 Multiprocess aware   = Y
index d6674f7..c2c6c19 100644 (file)
@@ -18,6 +18,8 @@ RSS key update       = Y
 RSS reta update      = Y
 VLAN filter          = Y
 Hash filter          = Y
+Rx descriptor status = Y
+Tx descriptor status = Y
 Basic stats          = Y
 Extended stats       = Y
 Multiprocess aware   = Y
index 303027b..8b5fd54 100644 (file)
@@ -479,6 +479,8 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
        .rx_queue_release             = i40e_dev_rx_queue_release,
        .rx_queue_count               = i40e_dev_rx_queue_count,
        .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
+       .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
+       .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
        .tx_queue_setup               = i40e_dev_tx_queue_setup,
        .tx_queue_release             = i40e_dev_tx_queue_release,
        .dev_led_on                   = i40e_dev_led_on,
index 55fd344..d3659c9 100644 (file)
@@ -217,6 +217,8 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = {
        .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
        .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
        .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
+       .rx_descriptor_status = i40e_dev_rx_descriptor_status,
+       .tx_descriptor_status = i40e_dev_tx_descriptor_status,
        .tx_queue_setup       = i40e_dev_tx_queue_setup,
        .tx_queue_release     = i40e_dev_tx_queue_release,
        .rx_queue_count       = i40e_dev_rx_queue_count,
index ec64a20..9ccc354 100644 (file)
@@ -1923,6 +1923,64 @@ i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
        return ret;
 }
 
+int
+i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
+{
+       struct i40e_rx_queue *rxq = rx_queue;
+       volatile uint64_t *status;
+       uint64_t mask;
+       uint32_t desc;
+
+       if (unlikely(offset >= rxq->nb_rx_desc))
+               return -EINVAL;
+
+       if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
+               return RTE_ETH_RX_DESC_UNAVAIL;
+
+       desc = rxq->rx_tail + offset;
+       if (desc >= rxq->nb_rx_desc)
+               desc -= rxq->nb_rx_desc;
+
+       status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
+       mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
+               << I40E_RXD_QW1_STATUS_SHIFT);
+       if (*status & mask)
+               return RTE_ETH_RX_DESC_DONE;
+
+       return RTE_ETH_RX_DESC_AVAIL;
+}
+
+int
+i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
+{
+       struct i40e_tx_queue *txq = tx_queue;
+       volatile uint64_t *status;
+       uint64_t mask, expect;
+       uint32_t desc;
+
+       if (unlikely(offset >= txq->nb_tx_desc))
+               return -EINVAL;
+
+       desc = txq->tx_tail + offset;
+       /* go to next desc that has the RS bit */
+       desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
+               txq->tx_rs_thresh;
+       if (desc >= txq->nb_tx_desc) {
+               desc -= txq->nb_tx_desc;
+               if (desc >= txq->nb_tx_desc)
+                       desc -= txq->nb_tx_desc;
+       }
+
+       status = &txq->tx_ring[desc].cmd_type_offset_bsz;
+       mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
+       expect = rte_cpu_to_le_64(
+               I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
+       if ((*status & mask) == expect)
+               return RTE_ETH_TX_DESC_DONE;
+
+       return RTE_ETH_TX_DESC_FULL;
+}
+
 int
 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
                        uint16_t queue_idx,
index 9df8a56..7f63328 100644 (file)
@@ -246,6 +246,8 @@ void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
 uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
                                 uint16_t rx_queue_id);
 int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
+int i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
+int i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
 
 uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
                            uint16_t nb_pkts);