drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 #ifdef RTE_LIBRTE_IEEE1588
  46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  47 #else
  48 #define I40E_TX_IEEE1588_TMST 0
  49 #endif
  50
  51 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  52                 PKT_TX_IP_CKSUM |                \
  53                 PKT_TX_L4_MASK |                 \
  54                 PKT_TX_TCP_SEG |                 \
  55                 PKT_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (  \
  58                 PKT_TX_OUTER_IPV4 |     \
  59                 PKT_TX_OUTER_IPV6 |     \
  60                 PKT_TX_IPV4 |           \
  61                 PKT_TX_IPV6 |           \
  62                 PKT_TX_IP_CKSUM |       \
  63                 PKT_TX_L4_MASK |        \
  64                 PKT_TX_OUTER_IP_CKSUM | \
  65                 PKT_TX_TCP_SEG |        \
  66                 PKT_TX_QINQ_PKT |       \
  67                 PKT_TX_VLAN_PKT |       \
  68                 PKT_TX_TUNNEL_MASK |    \
  69                 I40E_TX_IEEE1588_TMST)
  70
  71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  72                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  73
  74 static inline void
  75 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  76 {
  77         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  78                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  79                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  80                 mb->vlan_tci =
  81                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  82                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  83                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  84         } else {
  85                 mb->vlan_tci = 0;
  86         }
  87 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  88         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  89                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  90                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
  91                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
  92                 mb->vlan_tci_outer = mb->vlan_tci;
  93                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  96                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  97         } else {
  98                 mb->vlan_tci_outer = 0;
  99         }
 100 #endif
 101         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 102                    mb->vlan_tci, mb->vlan_tci_outer);
 103 }
 104
 105 /* Translate the rx descriptor status to pkt flags */
 106 static inline uint64_t
 107 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 108 {
 109         uint64_t flags;
 110
 111         /* Check if RSS_HASH */
 112         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 113                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 114                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 115
 116         /* Check if FDIR Match */
 117         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 118                                                         PKT_RX_FDIR : 0);
 119
 120         return flags;
 121 }
 122
 123 static inline uint64_t
 124 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 125 {
 126         uint64_t flags = 0;
 127         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 128
 129 #define I40E_RX_ERR_BITS 0x3f
 130         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 131                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 132                 return flags;
 133         }
 134
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 136                 flags |= PKT_RX_IP_CKSUM_BAD;
 137         else
 138                 flags |= PKT_RX_IP_CKSUM_GOOD;
 139
 140         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 141                 flags |= PKT_RX_L4_CKSUM_BAD;
 142         else
 143                 flags |= PKT_RX_L4_CKSUM_GOOD;
 144
 145         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 146                 flags |= PKT_RX_EIP_CKSUM_BAD;
 147
 148         return flags;
 149 }
 150
 151 /* Function to check and set the ieee1588 timesync index and get the
 152  * appropriate flags.
 153  */
 154 #ifdef RTE_LIBRTE_IEEE1588
 155 static inline uint64_t
 156 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 157 {
 158         uint64_t pkt_flags = 0;
 159         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 160                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 161                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 162
 163         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 164                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 165                 pkt_flags = PKT_RX_IEEE1588_PTP;
 166         if (tsyn & 0x04) {
 167                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 168                 mb->timesync = tsyn & 0x03;
 169         }
 170
 171         return pkt_flags;
 172 }
 173 #endif
 174
 175 static inline uint64_t
 176 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 177 {
 178         uint64_t flags = 0;
 179 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 180         uint16_t flexbh, flexbl;
 181
 182         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 183                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 184                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 185         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 186                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 187                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 188
 189
 190         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 191                 mb->hash.fdir.hi =
 192                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 193                 flags |= PKT_RX_FDIR_ID;
 194         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 195                 mb->hash.fdir.hi =
 196                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 197                 flags |= PKT_RX_FDIR_FLX;
 198         }
 199         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 200                 mb->hash.fdir.lo =
 201                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 202                 flags |= PKT_RX_FDIR_FLX;
 203         }
 204 #else
 205         mb->hash.fdir.hi =
 206                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 207         flags |= PKT_RX_FDIR_ID;
 208 #endif
 209         return flags;
 210 }
 211
 212 static inline void
 213 i40e_parse_tunneling_params(uint64_t ol_flags,
 214                             union i40e_tx_offload tx_offload,
 215                             uint32_t *cd_tunneling)
 216 {
 217         /* EIPT: External (outer) IP header type */
 218         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 219                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 220         else if (ol_flags & PKT_TX_OUTER_IPV4)
 221                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 222         else if (ol_flags & PKT_TX_OUTER_IPV6)
 223                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 224
 225         /* EIPLEN: External (outer) IP header length, in DWords */
 226         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 227                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 228
 229         /* L4TUNT: L4 Tunneling Type */
 230         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 231         case PKT_TX_TUNNEL_IPIP:
 232                 /* for non UDP / GRE tunneling, set to 00b */
 233                 break;
 234         case PKT_TX_TUNNEL_VXLAN:
 235         case PKT_TX_TUNNEL_GENEVE:
 236                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 237                 break;
 238         case PKT_TX_TUNNEL_GRE:
 239                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 240                 break;
 241         default:
 242                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 243                 return;
 244         }
 245
 246         /* L4TUNLEN: L4 Tunneling Length, in Words
 247          *
 248          * We depend on app to set rte_mbuf.l2_len correctly.
 249          * For IP in GRE it should be set to the length of the GRE
 250          * header;
 251          * for MAC in GRE or MAC in UDP it should be set to the length
 252          * of the GRE or UDP headers plus the inner MAC up to including
 253          * its last Ethertype.
 254          */
 255         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 256                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 257 }
 258
 259 static inline void
 260 i40e_txd_enable_checksum(uint64_t ol_flags,
 261                         uint32_t *td_cmd,
 262                         uint32_t *td_offset,
 263                         union i40e_tx_offload tx_offload)
 264 {
 265         /* Set MACLEN */
 266         if (ol_flags & PKT_TX_TUNNEL_MASK)
 267                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 268                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 269         else
 270                 *td_offset |= (tx_offload.l2_len >> 1)
 271                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 272
 273         /* Enable L3 checksum offloads */
 274         if (ol_flags & PKT_TX_IP_CKSUM) {
 275                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 276                 *td_offset |= (tx_offload.l3_len >> 2)
 277                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 278         } else if (ol_flags & PKT_TX_IPV4) {
 279                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 280                 *td_offset |= (tx_offload.l3_len >> 2)
 281                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 282         } else if (ol_flags & PKT_TX_IPV6) {
 283                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 284                 *td_offset |= (tx_offload.l3_len >> 2)
 285                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 286         }
 287
 288         if (ol_flags & PKT_TX_TCP_SEG) {
 289                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 290                 *td_offset |= (tx_offload.l4_len >> 2)
 291                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 292                 return;
 293         }
 294
 295         /* Enable L4 checksum offloads */
 296         switch (ol_flags & PKT_TX_L4_MASK) {
 297         case PKT_TX_TCP_CKSUM:
 298                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 299                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 300                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 301                 break;
 302         case PKT_TX_SCTP_CKSUM:
 303                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 304                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 305                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 306                 break;
 307         case PKT_TX_UDP_CKSUM:
 308                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 309                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 310                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 311                 break;
 312         default:
 313                 break;
 314         }
 315 }
 316
 317 /* Construct the tx flags */
 318 static inline uint64_t
 319 i40e_build_ctob(uint32_t td_cmd,
 320                 uint32_t td_offset,
 321                 unsigned int size,
 322                 uint32_t td_tag)
 323 {
 324         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 325                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 326                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 327                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 328                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 329 }
 330
 331 static inline int
 332 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 333 {
 334         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 335         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 336         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 337         uint16_t nb_tx_desc = txq->nb_tx_desc;
 338         uint16_t desc_to_clean_to;
 339         uint16_t nb_tx_to_clean;
 340
 341         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 342         if (desc_to_clean_to >= nb_tx_desc)
 343                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 344
 345         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 346         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 347                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 348                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 349                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 350                         "(port=%d queue=%d)", desc_to_clean_to,
 351                                 txq->port_id, txq->queue_id);
 352                 return -1;
 353         }
 354
 355         if (last_desc_cleaned > desc_to_clean_to)
 356                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 357                                                         desc_to_clean_to);
 358         else
 359                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 360                                         last_desc_cleaned);
 361
 362         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 363
 364         txq->last_desc_cleaned = desc_to_clean_to;
 365         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 366
 367         return 0;
 368 }
 369
 370 static inline int
 371 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 372 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 373 #else
 374 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 375 #endif
 376 {
 377         int ret = 0;
 378
 379 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 380         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 381                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 382                              "rxq->rx_free_thresh=%d, "
 383                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 384                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 385                 ret = -EINVAL;
 386         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 387                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 388                              "rxq->rx_free_thresh=%d, "
 389                              "rxq->nb_rx_desc=%d",
 390                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 391                 ret = -EINVAL;
 392         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 393                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 394                              "rxq->nb_rx_desc=%d, "
 395                              "rxq->rx_free_thresh=%d",
 396                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 397                 ret = -EINVAL;
 398         }
 399 #else
 400         ret = -EINVAL;
 401 #endif
 402
 403         return ret;
 404 }
 405
 406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 407 #define I40E_LOOK_AHEAD 8
 408 #if (I40E_LOOK_AHEAD != 8)
 409 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 410 #endif
 411 static inline int
 412 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 413 {
 414         volatile union i40e_rx_desc *rxdp;
 415         struct i40e_rx_entry *rxep;
 416         struct rte_mbuf *mb;
 417         uint16_t pkt_len;
 418         uint64_t qword1;
 419         uint32_t rx_status;
 420         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 421         int32_t i, j, nb_rx = 0;
 422         uint64_t pkt_flags;
 423         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 424
 425         rxdp = &rxq->rx_ring[rxq->rx_tail];
 426         rxep = &rxq->sw_ring[rxq->rx_tail];
 427
 428         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 429         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 430                                 I40E_RXD_QW1_STATUS_SHIFT;
 431
 432         /* Make sure there is at least 1 packet to receive */
 433         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 434                 return 0;
 435
 436         /**
 437          * Scan LOOK_AHEAD descriptors at a time to determine which
 438          * descriptors reference packets that are ready to be received.
 439          */
 440         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 441                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 442                 /* Read desc statuses backwards to avoid race condition */
 443                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 444                         qword1 = rte_le_to_cpu_64(\
 445                                 rxdp[j].wb.qword1.status_error_len);
 446                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 447                                         I40E_RXD_QW1_STATUS_SHIFT;
 448                 }
 449
 450                 rte_smp_rmb();
 451
 452                 /* Compute how many status bits were set */
 453                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 454                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 455
 456                 nb_rx += nb_dd;
 457
 458                 /* Translate descriptor info to mbuf parameters */
 459                 for (j = 0; j < nb_dd; j++) {
 460                         mb = rxep[j].mbuf;
 461                         qword1 = rte_le_to_cpu_64(\
 462                                 rxdp[j].wb.qword1.status_error_len);
 463                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 464                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 465                         mb->data_len = pkt_len;
 466                         mb->pkt_len = pkt_len;
 467                         mb->ol_flags = 0;
 468                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 469                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 470                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 471                         mb->packet_type =
 472                                 ptype_tbl[(uint8_t)((qword1 &
 473                                 I40E_RXD_QW1_PTYPE_MASK) >>
 474                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 475                         if (pkt_flags & PKT_RX_RSS_HASH)
 476                                 mb->hash.rss = rte_le_to_cpu_32(\
 477                                         rxdp[j].wb.qword0.hi_dword.rss);
 478                         if (pkt_flags & PKT_RX_FDIR)
 479                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 480
 481 #ifdef RTE_LIBRTE_IEEE1588
 482                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 483 #endif
 484                         mb->ol_flags |= pkt_flags;
 485
 486                 }
 487
 488                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 489                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 490
 491                 if (nb_dd != I40E_LOOK_AHEAD)
 492                         break;
 493         }
 494
 495         /* Clear software ring entries */
 496         for (i = 0; i < nb_rx; i++)
 497                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 498
 499         return nb_rx;
 500 }
 501
 502 static inline uint16_t
 503 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 504                         struct rte_mbuf **rx_pkts,
 505                         uint16_t nb_pkts)
 506 {
 507         uint16_t i;
 508         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 509
 510         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 511
 512         for (i = 0; i < nb_pkts; i++)
 513                 rx_pkts[i] = stage[i];
 514
 515         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 516         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 517
 518         return nb_pkts;
 519 }
 520
 521 static inline int
 522 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 523 {
 524         volatile union i40e_rx_desc *rxdp;
 525         struct i40e_rx_entry *rxep;
 526         struct rte_mbuf *mb;
 527         uint16_t alloc_idx, i;
 528         uint64_t dma_addr;
 529         int diag;
 530
 531         /* Allocate buffers in bulk */
 532         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 533                                 (rxq->rx_free_thresh - 1));
 534         rxep = &(rxq->sw_ring[alloc_idx]);
 535         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 536                                         rxq->rx_free_thresh);
 537         if (unlikely(diag != 0)) {
 538                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 539                 return -ENOMEM;
 540         }
 541
 542         rxdp = &rxq->rx_ring[alloc_idx];
 543         for (i = 0; i < rxq->rx_free_thresh; i++) {
 544                 if (likely(i < (rxq->rx_free_thresh - 1)))
 545                         /* Prefetch next mbuf */
 546                         rte_prefetch0(rxep[i + 1].mbuf);
 547
 548                 mb = rxep[i].mbuf;
 549                 rte_mbuf_refcnt_set(mb, 1);
 550                 mb->next = NULL;
 551                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 552                 mb->nb_segs = 1;
 553                 mb->port = rxq->port_id;
 554                 dma_addr = rte_cpu_to_le_64(\
 555                         rte_mbuf_data_iova_default(mb));
 556                 rxdp[i].read.hdr_addr = 0;
 557                 rxdp[i].read.pkt_addr = dma_addr;
 558         }
 559
 560         /* Update rx tail regsiter */
 561         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 562
 563         rxq->rx_free_trigger =
 564                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 565         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 566                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 567
 568         return 0;
 569 }
 570
 571 static inline uint16_t
 572 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 573 {
 574         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 575         struct rte_eth_dev *dev;
 576         uint16_t nb_rx = 0;
 577
 578         if (!nb_pkts)
 579                 return 0;
 580
 581         if (rxq->rx_nb_avail)
 582                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 583
 584         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 585         rxq->rx_next_avail = 0;
 586         rxq->rx_nb_avail = nb_rx;
 587         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 588
 589         if (rxq->rx_tail > rxq->rx_free_trigger) {
 590                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 591                         uint16_t i, j;
 592
 593                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 594                         dev->data->rx_mbuf_alloc_failed +=
 595                                 rxq->rx_free_thresh;
 596
 597                         rxq->rx_nb_avail = 0;
 598                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 599                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 600                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 601
 602                         return 0;
 603                 }
 604         }
 605
 606         if (rxq->rx_tail >= rxq->nb_rx_desc)
 607                 rxq->rx_tail = 0;
 608
 609         if (rxq->rx_nb_avail)
 610                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 611
 612         return 0;
 613 }
 614
 615 static uint16_t
 616 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 617                           struct rte_mbuf **rx_pkts,
 618                           uint16_t nb_pkts)
 619 {
 620         uint16_t nb_rx = 0, n, count;
 621
 622         if (unlikely(nb_pkts == 0))
 623                 return 0;
 624
 625         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 626                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 627
 628         while (nb_pkts) {
 629                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 630                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 631                 nb_rx = (uint16_t)(nb_rx + count);
 632                 nb_pkts = (uint16_t)(nb_pkts - count);
 633                 if (count < n)
 634                         break;
 635         }
 636
 637         return nb_rx;
 638 }
 639 #else
 640 static uint16_t
 641 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 642                           struct rte_mbuf __rte_unused **rx_pkts,
 643                           uint16_t __rte_unused nb_pkts)
 644 {
 645         return 0;
 646 }
 647 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 648
 649 uint16_t
 650 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 651 {
 652         struct i40e_rx_queue *rxq;
 653         volatile union i40e_rx_desc *rx_ring;
 654         volatile union i40e_rx_desc *rxdp;
 655         union i40e_rx_desc rxd;
 656         struct i40e_rx_entry *sw_ring;
 657         struct i40e_rx_entry *rxe;
 658         struct rte_eth_dev *dev;
 659         struct rte_mbuf *rxm;
 660         struct rte_mbuf *nmb;
 661         uint16_t nb_rx;
 662         uint32_t rx_status;
 663         uint64_t qword1;
 664         uint16_t rx_packet_len;
 665         uint16_t rx_id, nb_hold;
 666         uint64_t dma_addr;
 667         uint64_t pkt_flags;
 668         uint32_t *ptype_tbl;
 669
 670         nb_rx = 0;
 671         nb_hold = 0;
 672         rxq = rx_queue;
 673         rx_id = rxq->rx_tail;
 674         rx_ring = rxq->rx_ring;
 675         sw_ring = rxq->sw_ring;
 676         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 677
 678         while (nb_rx < nb_pkts) {
 679                 rxdp = &rx_ring[rx_id];
 680                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 681                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 682                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 683
 684                 /* Check the DD bit first */
 685                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 686                         break;
 687
 688                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 689                 if (unlikely(!nmb)) {
 690                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 691                         dev->data->rx_mbuf_alloc_failed++;
 692                         break;
 693                 }
 694
 695                 rxd = *rxdp;
 696                 nb_hold++;
 697                 rxe = &sw_ring[rx_id];
 698                 rx_id++;
 699                 if (unlikely(rx_id == rxq->nb_rx_desc))
 700                         rx_id = 0;
 701
 702                 /* Prefetch next mbuf */
 703                 rte_prefetch0(sw_ring[rx_id].mbuf);
 704
 705                 /**
 706                  * When next RX descriptor is on a cache line boundary,
 707                  * prefetch the next 4 RX descriptors and next 8 pointers
 708                  * to mbufs.
 709                  */
 710                 if ((rx_id & 0x3) == 0) {
 711                         rte_prefetch0(&rx_ring[rx_id]);
 712                         rte_prefetch0(&sw_ring[rx_id]);
 713                 }
 714                 rxm = rxe->mbuf;
 715                 rxe->mbuf = nmb;
 716                 dma_addr =
 717                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 718                 rxdp->read.hdr_addr = 0;
 719                 rxdp->read.pkt_addr = dma_addr;
 720
 721                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 722                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 723
 724                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 725                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 726                 rxm->nb_segs = 1;
 727                 rxm->next = NULL;
 728                 rxm->pkt_len = rx_packet_len;
 729                 rxm->data_len = rx_packet_len;
 730                 rxm->port = rxq->port_id;
 731                 rxm->ol_flags = 0;
 732                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 733                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 734                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 735                 rxm->packet_type =
 736                         ptype_tbl[(uint8_t)((qword1 &
 737                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 738                 if (pkt_flags & PKT_RX_RSS_HASH)
 739                         rxm->hash.rss =
 740                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 741                 if (pkt_flags & PKT_RX_FDIR)
 742                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 743
 744 #ifdef RTE_LIBRTE_IEEE1588
 745                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 746 #endif
 747                 rxm->ol_flags |= pkt_flags;
 748
 749                 rx_pkts[nb_rx++] = rxm;
 750         }
 751         rxq->rx_tail = rx_id;
 752
 753         /**
 754          * If the number of free RX descriptors is greater than the RX free
 755          * threshold of the queue, advance the receive tail register of queue.
 756          * Update that register with the value of the last processed RX
 757          * descriptor minus 1.
 758          */
 759         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 760         if (nb_hold > rxq->rx_free_thresh) {
 761                 rx_id = (uint16_t) ((rx_id == 0) ?
 762                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 763                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 764                 nb_hold = 0;
 765         }
 766         rxq->nb_rx_hold = nb_hold;
 767
 768         return nb_rx;
 769 }
 770
 771 uint16_t
 772 i40e_recv_scattered_pkts(void *rx_queue,
 773                          struct rte_mbuf **rx_pkts,
 774                          uint16_t nb_pkts)
 775 {
 776         struct i40e_rx_queue *rxq = rx_queue;
 777         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 778         volatile union i40e_rx_desc *rxdp;
 779         union i40e_rx_desc rxd;
 780         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 781         struct i40e_rx_entry *rxe;
 782         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 783         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 784         struct rte_mbuf *nmb, *rxm;
 785         uint16_t rx_id = rxq->rx_tail;
 786         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 787         struct rte_eth_dev *dev;
 788         uint32_t rx_status;
 789         uint64_t qword1;
 790         uint64_t dma_addr;
 791         uint64_t pkt_flags;
 792         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 793
 794         while (nb_rx < nb_pkts) {
 795                 rxdp = &rx_ring[rx_id];
 796                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 797                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 798                                         I40E_RXD_QW1_STATUS_SHIFT;
 799
 800                 /* Check the DD bit */
 801                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 802                         break;
 803
 804                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 805                 if (unlikely(!nmb)) {
 806                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 807                         dev->data->rx_mbuf_alloc_failed++;
 808                         break;
 809                 }
 810
 811                 rxd = *rxdp;
 812                 nb_hold++;
 813                 rxe = &sw_ring[rx_id];
 814                 rx_id++;
 815                 if (rx_id == rxq->nb_rx_desc)
 816                         rx_id = 0;
 817
 818                 /* Prefetch next mbuf */
 819                 rte_prefetch0(sw_ring[rx_id].mbuf);
 820
 821                 /**
 822                  * When next RX descriptor is on a cache line boundary,
 823                  * prefetch the next 4 RX descriptors and next 8 pointers
 824                  * to mbufs.
 825                  */
 826                 if ((rx_id & 0x3) == 0) {
 827                         rte_prefetch0(&rx_ring[rx_id]);
 828                         rte_prefetch0(&sw_ring[rx_id]);
 829                 }
 830
 831                 rxm = rxe->mbuf;
 832                 rxe->mbuf = nmb;
 833                 dma_addr =
 834                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 835
 836                 /* Set data buffer address and data length of the mbuf */
 837                 rxdp->read.hdr_addr = 0;
 838                 rxdp->read.pkt_addr = dma_addr;
 839                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 840                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 841                 rxm->data_len = rx_packet_len;
 842                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 843
 844                 /**
 845                  * If this is the first buffer of the received packet, set the
 846                  * pointer to the first mbuf of the packet and initialize its
 847                  * context. Otherwise, update the total length and the number
 848                  * of segments of the current scattered packet, and update the
 849                  * pointer to the last mbuf of the current packet.
 850                  */
 851                 if (!first_seg) {
 852                         first_seg = rxm;
 853                         first_seg->nb_segs = 1;
 854                         first_seg->pkt_len = rx_packet_len;
 855                 } else {
 856                         first_seg->pkt_len =
 857                                 (uint16_t)(first_seg->pkt_len +
 858                                                 rx_packet_len);
 859                         first_seg->nb_segs++;
 860                         last_seg->next = rxm;
 861                 }
 862
 863                 /**
 864                  * If this is not the last buffer of the received packet,
 865                  * update the pointer to the last mbuf of the current scattered
 866                  * packet and continue to parse the RX ring.
 867                  */
 868                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 869                         last_seg = rxm;
 870                         continue;
 871                 }
 872
 873                 /**
 874                  * This is the last buffer of the received packet. If the CRC
 875                  * is not stripped by the hardware:
 876                  *  - Subtract the CRC length from the total packet length.
 877                  *  - If the last buffer only contains the whole CRC or a part
 878                  *  of it, free the mbuf associated to the last buffer. If part
 879                  *  of the CRC is also contained in the previous mbuf, subtract
 880                  *  the length of that CRC part from the data length of the
 881                  *  previous mbuf.
 882                  */
 883                 rxm->next = NULL;
 884                 if (unlikely(rxq->crc_len > 0)) {
 885                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 886                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 887                                 rte_pktmbuf_free_seg(rxm);
 888                                 first_seg->nb_segs--;
 889                                 last_seg->data_len =
 890                                         (uint16_t)(last_seg->data_len -
 891                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 892                                 last_seg->next = NULL;
 893                         } else
 894                                 rxm->data_len = (uint16_t)(rx_packet_len -
 895                                                         RTE_ETHER_CRC_LEN);
 896                 }
 897
 898                 first_seg->port = rxq->port_id;
 899                 first_seg->ol_flags = 0;
 900                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 901                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 902                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 903                 first_seg->packet_type =
 904                         ptype_tbl[(uint8_t)((qword1 &
 905                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 906                 if (pkt_flags & PKT_RX_RSS_HASH)
 907                         first_seg->hash.rss =
 908                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 909                 if (pkt_flags & PKT_RX_FDIR)
 910                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 911
 912 #ifdef RTE_LIBRTE_IEEE1588
 913                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 914 #endif
 915                 first_seg->ol_flags |= pkt_flags;
 916
 917                 /* Prefetch data of first segment, if configured to do so. */
 918                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 919                         first_seg->data_off));
 920                 rx_pkts[nb_rx++] = first_seg;
 921                 first_seg = NULL;
 922         }
 923
 924         /* Record index of the next RX descriptor to probe. */
 925         rxq->rx_tail = rx_id;
 926         rxq->pkt_first_seg = first_seg;
 927         rxq->pkt_last_seg = last_seg;
 928
 929         /**
 930          * If the number of free RX descriptors is greater than the RX free
 931          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 932          * register. Update the RDT with the value of the last processed RX
 933          * descriptor minus 1, to guarantee that the RDT register is never
 934          * equal to the RDH register, which creates a "full" ring situtation
 935          * from the hardware point of view.
 936          */
 937         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 938         if (nb_hold > rxq->rx_free_thresh) {
 939                 rx_id = (uint16_t)(rx_id == 0 ?
 940                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 941                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 942                 nb_hold = 0;
 943         }
 944         rxq->nb_rx_hold = nb_hold;
 945
 946         return nb_rx;
 947 }
 948
 949 /* Check if the context descriptor is needed for TX offloading */
 950 static inline uint16_t
 951 i40e_calc_context_desc(uint64_t flags)
 952 {
 953         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 954                 PKT_TX_TCP_SEG |
 955                 PKT_TX_QINQ_PKT |
 956                 PKT_TX_TUNNEL_MASK;
 957
 958 #ifdef RTE_LIBRTE_IEEE1588
 959         mask |= PKT_TX_IEEE1588_TMST;
 960 #endif
 961
 962         return (flags & mask) ? 1 : 0;
 963 }
 964
 965 /* set i40e TSO context descriptor */
 966 static inline uint64_t
 967 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 968 {
 969         uint64_t ctx_desc = 0;
 970         uint32_t cd_cmd, hdr_len, cd_tso_len;
 971
 972         if (!tx_offload.l4_len) {
 973                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 974                 return ctx_desc;
 975         }
 976
 977         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
 978         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
 979                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
 980
 981         cd_cmd = I40E_TX_CTX_DESC_TSO;
 982         cd_tso_len = mbuf->pkt_len - hdr_len;
 983         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 984                 ((uint64_t)cd_tso_len <<
 985                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 986                 ((uint64_t)mbuf->tso_segsz <<
 987                  I40E_TXD_CTX_QW1_MSS_SHIFT);
 988
 989         return ctx_desc;
 990 }
 991
 992 uint16_t
 993 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 994 {
 995         struct i40e_tx_queue *txq;
 996         struct i40e_tx_entry *sw_ring;
 997         struct i40e_tx_entry *txe, *txn;
 998         volatile struct i40e_tx_desc *txd;
 999         volatile struct i40e_tx_desc *txr;
1000         struct rte_mbuf *tx_pkt;
1001         struct rte_mbuf *m_seg;
1002         uint32_t cd_tunneling_params;
1003         uint16_t tx_id;
1004         uint16_t nb_tx;
1005         uint32_t td_cmd;
1006         uint32_t td_offset;
1007         uint32_t td_tag;
1008         uint64_t ol_flags;
1009         uint16_t nb_used;
1010         uint16_t nb_ctx;
1011         uint16_t tx_last;
1012         uint16_t slen;
1013         uint64_t buf_dma_addr;
1014         union i40e_tx_offload tx_offload = {0};
1015
1016         txq = tx_queue;
1017         sw_ring = txq->sw_ring;
1018         txr = txq->tx_ring;
1019         tx_id = txq->tx_tail;
1020         txe = &sw_ring[tx_id];
1021
1022         /* Check if the descriptor ring needs to be cleaned. */
1023         if (txq->nb_tx_free < txq->tx_free_thresh)
1024                 i40e_xmit_cleanup(txq);
1025
1026         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1027                 td_cmd = 0;
1028                 td_tag = 0;
1029                 td_offset = 0;
1030
1031                 tx_pkt = *tx_pkts++;
1032                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1033
1034                 ol_flags = tx_pkt->ol_flags;
1035                 tx_offload.l2_len = tx_pkt->l2_len;
1036                 tx_offload.l3_len = tx_pkt->l3_len;
1037                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1038                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1039                 tx_offload.l4_len = tx_pkt->l4_len;
1040                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1041
1042                 /* Calculate the number of context descriptors needed. */
1043                 nb_ctx = i40e_calc_context_desc(ol_flags);
1044
1045                 /**
1046                  * The number of descriptors that must be allocated for
1047                  * a packet equals to the number of the segments of that
1048                  * packet plus 1 context descriptor if needed.
1049                  */
1050                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1051                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1052
1053                 /* Circular ring */
1054                 if (tx_last >= txq->nb_tx_desc)
1055                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1056
1057                 if (nb_used > txq->nb_tx_free) {
1058                         if (i40e_xmit_cleanup(txq) != 0) {
1059                                 if (nb_tx == 0)
1060                                         return 0;
1061                                 goto end_of_tx;
1062                         }
1063                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1064                                 while (nb_used > txq->nb_tx_free) {
1065                                         if (i40e_xmit_cleanup(txq) != 0) {
1066                                                 if (nb_tx == 0)
1067                                                         return 0;
1068                                                 goto end_of_tx;
1069                                         }
1070                                 }
1071                         }
1072                 }
1073
1074                 /* Descriptor based VLAN insertion */
1075                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1076                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1077                         td_tag = tx_pkt->vlan_tci;
1078                 }
1079
1080                 /* Always enable CRC offload insertion */
1081                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1082
1083                 /* Fill in tunneling parameters if necessary */
1084                 cd_tunneling_params = 0;
1085                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1086                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1087                                                     &cd_tunneling_params);
1088                 /* Enable checksum offloading */
1089                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1090                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1091                                                  &td_offset, tx_offload);
1092
1093                 if (nb_ctx) {
1094                         /* Setup TX context descriptor if required */
1095                         volatile struct i40e_tx_context_desc *ctx_txd =
1096                                 (volatile struct i40e_tx_context_desc *)\
1097                                                         &txr[tx_id];
1098                         uint16_t cd_l2tag2 = 0;
1099                         uint64_t cd_type_cmd_tso_mss =
1100                                 I40E_TX_DESC_DTYPE_CONTEXT;
1101
1102                         txn = &sw_ring[txe->next_id];
1103                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1104                         if (txe->mbuf != NULL) {
1105                                 rte_pktmbuf_free_seg(txe->mbuf);
1106                                 txe->mbuf = NULL;
1107                         }
1108
1109                         /* TSO enabled means no timestamp */
1110                         if (ol_flags & PKT_TX_TCP_SEG)
1111                                 cd_type_cmd_tso_mss |=
1112                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1113                         else {
1114 #ifdef RTE_LIBRTE_IEEE1588
1115                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1116                                         cd_type_cmd_tso_mss |=
1117                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1118                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1119 #endif
1120                         }
1121
1122                         ctx_txd->tunneling_params =
1123                                 rte_cpu_to_le_32(cd_tunneling_params);
1124                         if (ol_flags & PKT_TX_QINQ_PKT) {
1125                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1126                                 cd_type_cmd_tso_mss |=
1127                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1128                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1129                         }
1130                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1131                         ctx_txd->type_cmd_tso_mss =
1132                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1133
1134                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1135                                 "tunneling_params: %#x;\n"
1136                                 "l2tag2: %#hx;\n"
1137                                 "rsvd: %#hx;\n"
1138                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1139                                 tx_pkt, tx_id,
1140                                 ctx_txd->tunneling_params,
1141                                 ctx_txd->l2tag2,
1142                                 ctx_txd->rsvd,
1143                                 ctx_txd->type_cmd_tso_mss);
1144
1145                         txe->last_id = tx_last;
1146                         tx_id = txe->next_id;
1147                         txe = txn;
1148                 }
1149
1150                 m_seg = tx_pkt;
1151                 do {
1152                         txd = &txr[tx_id];
1153                         txn = &sw_ring[txe->next_id];
1154
1155                         if (txe->mbuf)
1156                                 rte_pktmbuf_free_seg(txe->mbuf);
1157                         txe->mbuf = m_seg;
1158
1159                         /* Setup TX Descriptor */
1160                         slen = m_seg->data_len;
1161                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1162
1163                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1164                                 "buf_dma_addr: %#"PRIx64";\n"
1165                                 "td_cmd: %#x;\n"
1166                                 "td_offset: %#x;\n"
1167                                 "td_len: %u;\n"
1168                                 "td_tag: %#x;\n",
1169                                 tx_pkt, tx_id, buf_dma_addr,
1170                                 td_cmd, td_offset, slen, td_tag);
1171
1172                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1173                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1174                                                 td_offset, slen, td_tag);
1175                         txe->last_id = tx_last;
1176                         tx_id = txe->next_id;
1177                         txe = txn;
1178                         m_seg = m_seg->next;
1179                 } while (m_seg != NULL);
1180
1181                 /* The last packet data descriptor needs End Of Packet (EOP) */
1182                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1183                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1184                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1185
1186                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1187                         PMD_TX_FREE_LOG(DEBUG,
1188                                         "Setting RS bit on TXD id="
1189                                         "%4u (port=%d queue=%d)",
1190                                         tx_last, txq->port_id, txq->queue_id);
1191
1192                         td_cmd |= I40E_TX_DESC_CMD_RS;
1193
1194                         /* Update txq RS bit counters */
1195                         txq->nb_tx_used = 0;
1196                 }
1197
1198                 txd->cmd_type_offset_bsz |=
1199                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1200                                         I40E_TXD_QW1_CMD_SHIFT);
1201         }
1202
1203 end_of_tx:
1204         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1205                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1206                    (unsigned) tx_id, (unsigned) nb_tx);
1207
1208         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1209         txq->tx_tail = tx_id;
1210
1211         return nb_tx;
1212 }
1213
1214 static __rte_always_inline int
1215 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1216 {
1217         struct i40e_tx_entry *txep;
1218         uint16_t i;
1219
1220         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1221                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1222                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1223                 return 0;
1224
1225         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1226
1227         for (i = 0; i < txq->tx_rs_thresh; i++)
1228                 rte_prefetch0((txep + i)->mbuf);
1229
1230         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1231                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1232                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1233                         txep->mbuf = NULL;
1234                 }
1235         } else {
1236                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1237                         rte_pktmbuf_free_seg(txep->mbuf);
1238                         txep->mbuf = NULL;
1239                 }
1240         }
1241
1242         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1243         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1244         if (txq->tx_next_dd >= txq->nb_tx_desc)
1245                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1246
1247         return txq->tx_rs_thresh;
1248 }
1249
1250 /* Populate 4 descriptors with data from 4 mbufs */
1251 static inline void
1252 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1253 {
1254         uint64_t dma_addr;
1255         uint32_t i;
1256
1257         for (i = 0; i < 4; i++, txdp++, pkts++) {
1258                 dma_addr = rte_mbuf_data_iova(*pkts);
1259                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1260                 txdp->cmd_type_offset_bsz =
1261                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1262                                         (*pkts)->data_len, 0);
1263         }
1264 }
1265
1266 /* Populate 1 descriptor with data from 1 mbuf */
1267 static inline void
1268 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1269 {
1270         uint64_t dma_addr;
1271
1272         dma_addr = rte_mbuf_data_iova(*pkts);
1273         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1274         txdp->cmd_type_offset_bsz =
1275                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1276                                 (*pkts)->data_len, 0);
1277 }
1278
1279 /* Fill hardware descriptor ring with mbuf data */
1280 static inline void
1281 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1282                      struct rte_mbuf **pkts,
1283                      uint16_t nb_pkts)
1284 {
1285         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1286         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1287         const int N_PER_LOOP = 4;
1288         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1289         int mainpart, leftover;
1290         int i, j;
1291
1292         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1293         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1294         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1295                 for (j = 0; j < N_PER_LOOP; ++j) {
1296                         (txep + i + j)->mbuf = *(pkts + i + j);
1297                 }
1298                 tx4(txdp + i, pkts + i);
1299         }
1300         if (unlikely(leftover > 0)) {
1301                 for (i = 0; i < leftover; ++i) {
1302                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1303                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1304                 }
1305         }
1306 }
1307
1308 static inline uint16_t
1309 tx_xmit_pkts(struct i40e_tx_queue *txq,
1310              struct rte_mbuf **tx_pkts,
1311              uint16_t nb_pkts)
1312 {
1313         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1314         uint16_t n = 0;
1315
1316         /**
1317          * Begin scanning the H/W ring for done descriptors when the number
1318          * of available descriptors drops below tx_free_thresh. For each done
1319          * descriptor, free the associated buffer.
1320          */
1321         if (txq->nb_tx_free < txq->tx_free_thresh)
1322                 i40e_tx_free_bufs(txq);
1323
1324         /* Use available descriptor only */
1325         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1326         if (unlikely(!nb_pkts))
1327                 return 0;
1328
1329         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1330         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1331                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1332                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1333                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1334                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1335                                                 I40E_TXD_QW1_CMD_SHIFT);
1336                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1337                 txq->tx_tail = 0;
1338         }
1339
1340         /* Fill hardware descriptor ring with mbuf data */
1341         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1342         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1343
1344         /* Determin if RS bit needs to be set */
1345         if (txq->tx_tail > txq->tx_next_rs) {
1346                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1347                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1348                                                 I40E_TXD_QW1_CMD_SHIFT);
1349                 txq->tx_next_rs =
1350                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1351                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1352                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1353         }
1354
1355         if (txq->tx_tail >= txq->nb_tx_desc)
1356                 txq->tx_tail = 0;
1357
1358         /* Update the tx tail register */
1359         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1360
1361         return nb_pkts;
1362 }
1363
1364 static uint16_t
1365 i40e_xmit_pkts_simple(void *tx_queue,
1366                       struct rte_mbuf **tx_pkts,
1367                       uint16_t nb_pkts)
1368 {
1369         uint16_t nb_tx = 0;
1370
1371         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1372                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1373                                                 tx_pkts, nb_pkts);
1374
1375         while (nb_pkts) {
1376                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1377                                                 I40E_TX_MAX_BURST);
1378
1379                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1380                                                 &tx_pkts[nb_tx], num);
1381                 nb_tx = (uint16_t)(nb_tx + ret);
1382                 nb_pkts = (uint16_t)(nb_pkts - ret);
1383                 if (ret < num)
1384                         break;
1385         }
1386
1387         return nb_tx;
1388 }
1389
1390 static uint16_t
1391 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1392                    uint16_t nb_pkts)
1393 {
1394         uint16_t nb_tx = 0;
1395         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1396
1397         while (nb_pkts) {
1398                 uint16_t ret, num;
1399
1400                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1401                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1402                                                 num);
1403                 nb_tx += ret;
1404                 nb_pkts -= ret;
1405                 if (ret < num)
1406                         break;
1407         }
1408
1409         return nb_tx;
1410 }
1411
1412 /*********************************************************************
1413  *
1414  *  TX prep functions
1415  *
1416  **********************************************************************/
1417 uint16_t
1418 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1419                 uint16_t nb_pkts)
1420 {
1421         int i, ret;
1422         uint64_t ol_flags;
1423         struct rte_mbuf *m;
1424
1425         for (i = 0; i < nb_pkts; i++) {
1426                 m = tx_pkts[i];
1427                 ol_flags = m->ol_flags;
1428
1429                 /* Check for m->nb_segs to not exceed the limits. */
1430                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1431                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1432                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1433                                 rte_errno = EINVAL;
1434                                 return i;
1435                         }
1436                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1437                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1438                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1439                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1440                         /* MSS outside the range (256B - 9674B) are considered
1441                          * malicious
1442                          */
1443                         rte_errno = EINVAL;
1444                         return i;
1445                 }
1446
1447                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1448                         rte_errno = ENOTSUP;
1449                         return i;
1450                 }
1451
1452                 /* check the size of packet */
1453                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1454                         rte_errno = EINVAL;
1455                         return i;
1456                 }
1457
1458 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1459                 ret = rte_validate_tx_offload(m);
1460                 if (ret != 0) {
1461                         rte_errno = -ret;
1462                         return i;
1463                 }
1464 #endif
1465                 ret = rte_net_intel_cksum_prepare(m);
1466                 if (ret != 0) {
1467                         rte_errno = -ret;
1468                         return i;
1469                 }
1470         }
1471         return i;
1472 }
1473
1474 /*
1475  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1476  * application used, which assume having sequential ones. But from driver's
1477  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1478  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1479  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1480  * use queue_idx from 0 to 95 to access queues, while real queue would be
1481  * different. This function will do a queue mapping to find VSI the queue
1482  * belongs to.
1483  */
1484 static struct i40e_vsi*
1485 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1486 {
1487         /* the queue in MAIN VSI range */
1488         if (queue_idx < pf->main_vsi->nb_qps)
1489                 return pf->main_vsi;
1490
1491         queue_idx -= pf->main_vsi->nb_qps;
1492
1493         /* queue_idx is greater than VMDQ VSIs range */
1494         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1495                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1496                 return NULL;
1497         }
1498
1499         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1500 }
1501
1502 static uint16_t
1503 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1504 {
1505         /* the queue in MAIN VSI range */
1506         if (queue_idx < pf->main_vsi->nb_qps)
1507                 return queue_idx;
1508
1509         /* It's VMDQ queues */
1510         queue_idx -= pf->main_vsi->nb_qps;
1511
1512         if (pf->nb_cfg_vmdq_vsi)
1513                 return queue_idx % pf->vmdq_nb_qps;
1514         else {
1515                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1516                 return (uint16_t)(-1);
1517         }
1518 }
1519
1520 int
1521 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1522 {
1523         struct i40e_rx_queue *rxq;
1524         int err;
1525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1526
1527         PMD_INIT_FUNC_TRACE();
1528
1529         rxq = dev->data->rx_queues[rx_queue_id];
1530
1531         err = i40e_alloc_rx_queue_mbufs(rxq);
1532         if (err) {
1533                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1534                 return err;
1535         }
1536
1537         /* Init the RX tail regieter. */
1538         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1539
1540         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1541         if (err) {
1542                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1543                             rx_queue_id);
1544
1545                 i40e_rx_queue_release_mbufs(rxq);
1546                 i40e_reset_rx_queue(rxq);
1547                 return err;
1548         }
1549         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1550
1551         return 0;
1552 }
1553
1554 int
1555 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1556 {
1557         struct i40e_rx_queue *rxq;
1558         int err;
1559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560
1561         rxq = dev->data->rx_queues[rx_queue_id];
1562
1563         /*
1564          * rx_queue_id is queue id application refers to, while
1565          * rxq->reg_idx is the real queue index.
1566          */
1567         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1568         if (err) {
1569                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1570                             rx_queue_id);
1571                 return err;
1572         }
1573         i40e_rx_queue_release_mbufs(rxq);
1574         i40e_reset_rx_queue(rxq);
1575         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1576
1577         return 0;
1578 }
1579
1580 int
1581 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1582 {
1583         int err;
1584         struct i40e_tx_queue *txq;
1585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586
1587         PMD_INIT_FUNC_TRACE();
1588
1589         txq = dev->data->tx_queues[tx_queue_id];
1590
1591         /*
1592          * tx_queue_id is queue id application refers to, while
1593          * rxq->reg_idx is the real queue index.
1594          */
1595         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1596         if (err) {
1597                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1598                             tx_queue_id);
1599                 return err;
1600         }
1601         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1602
1603         return 0;
1604 }
1605
1606 int
1607 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1608 {
1609         struct i40e_tx_queue *txq;
1610         int err;
1611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612
1613         txq = dev->data->tx_queues[tx_queue_id];
1614
1615         /*
1616          * tx_queue_id is queue id application refers to, while
1617          * txq->reg_idx is the real queue index.
1618          */
1619         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1620         if (err) {
1621                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1622                             tx_queue_id);
1623                 return err;
1624         }
1625
1626         i40e_tx_queue_release_mbufs(txq);
1627         i40e_reset_tx_queue(txq);
1628         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1629
1630         return 0;
1631 }
1632
1633 const uint32_t *
1634 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1635 {
1636         static const uint32_t ptypes[] = {
1637                 /* refers to i40e_rxd_pkt_type_mapping() */
1638                 RTE_PTYPE_L2_ETHER,
1639                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1640                 RTE_PTYPE_L2_ETHER_LLDP,
1641                 RTE_PTYPE_L2_ETHER_ARP,
1642                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1643                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1644                 RTE_PTYPE_L4_FRAG,
1645                 RTE_PTYPE_L4_ICMP,
1646                 RTE_PTYPE_L4_NONFRAG,
1647                 RTE_PTYPE_L4_SCTP,
1648                 RTE_PTYPE_L4_TCP,
1649                 RTE_PTYPE_L4_UDP,
1650                 RTE_PTYPE_TUNNEL_GRENAT,
1651                 RTE_PTYPE_TUNNEL_IP,
1652                 RTE_PTYPE_INNER_L2_ETHER,
1653                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1654                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1655                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1656                 RTE_PTYPE_INNER_L4_FRAG,
1657                 RTE_PTYPE_INNER_L4_ICMP,
1658                 RTE_PTYPE_INNER_L4_NONFRAG,
1659                 RTE_PTYPE_INNER_L4_SCTP,
1660                 RTE_PTYPE_INNER_L4_TCP,
1661                 RTE_PTYPE_INNER_L4_UDP,
1662                 RTE_PTYPE_UNKNOWN
1663         };
1664
1665         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1666 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1667             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1668 #endif
1669             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1670             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1671             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1672             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1673             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1674                 return ptypes;
1675         return NULL;
1676 }
1677
1678 static int
1679 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1680 {
1681         uint16_t i;
1682
1683         for (i = 0; i < num; i++) {
1684                 if (i != idx && queues[i])
1685                         return 0;
1686         }
1687
1688         return 1;
1689 }
1690
1691 static int
1692 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1693                                 struct i40e_rx_queue *rxq)
1694 {
1695         struct i40e_adapter *ad =
1696                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1697         int use_def_burst_func =
1698                 check_rx_burst_bulk_alloc_preconditions(rxq);
1699         uint16_t buf_size =
1700                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1701                            RTE_PKTMBUF_HEADROOM);
1702         int use_scattered_rx =
1703                 (rxq->max_pkt_len > buf_size);
1704
1705         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1706                 PMD_DRV_LOG(ERR,
1707                             "Failed to do RX queue initialization");
1708                 return -EINVAL;
1709         }
1710
1711         if (i40e_dev_first_queue(rxq->queue_id,
1712                                  dev->data->rx_queues,
1713                                  dev->data->nb_rx_queues)) {
1714                 /**
1715                  * If it is the first queue to setup,
1716                  * set all flags to default and call
1717                  * i40e_set_rx_function.
1718                  */
1719                 ad->rx_bulk_alloc_allowed = true;
1720                 ad->rx_vec_allowed = true;
1721                 dev->data->scattered_rx = use_scattered_rx;
1722                 if (use_def_burst_func)
1723                         ad->rx_bulk_alloc_allowed = false;
1724                 i40e_set_rx_function(dev);
1725                 return 0;
1726         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1727                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1728                             " number %d of queue %d isn't power of 2",
1729                             rxq->nb_rx_desc, rxq->queue_id);
1730                 return -EINVAL;
1731         }
1732
1733         /* check bulk alloc conflict */
1734         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1735                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1736                 return -EINVAL;
1737         }
1738         /* check scatterred conflict */
1739         if (!dev->data->scattered_rx && use_scattered_rx) {
1740                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1741                 return -EINVAL;
1742         }
1743         /* check vector conflict */
1744         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1745                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1746                 return -EINVAL;
1747         }
1748
1749         return 0;
1750 }
1751
1752 int
1753 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1754                         uint16_t queue_idx,
1755                         uint16_t nb_desc,
1756                         unsigned int socket_id,
1757                         const struct rte_eth_rxconf *rx_conf,
1758                         struct rte_mempool *mp)
1759 {
1760         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761         struct i40e_adapter *ad =
1762                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1763         struct i40e_vsi *vsi;
1764         struct i40e_pf *pf = NULL;
1765         struct i40e_vf *vf = NULL;
1766         struct i40e_rx_queue *rxq;
1767         const struct rte_memzone *rz;
1768         uint32_t ring_size;
1769         uint16_t len, i;
1770         uint16_t reg_idx, base, bsf, tc_mapping;
1771         int q_offset, use_def_burst_func = 1;
1772         uint64_t offloads;
1773
1774         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1775
1776         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1777                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1778                 vsi = &vf->vsi;
1779                 if (!vsi)
1780                         return -EINVAL;
1781                 reg_idx = queue_idx;
1782         } else {
1783                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1784                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1785                 if (!vsi)
1786                         return -EINVAL;
1787                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1788                 if (q_offset < 0)
1789                         return -EINVAL;
1790                 reg_idx = vsi->base_queue + q_offset;
1791         }
1792
1793         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1794             (nb_desc > I40E_MAX_RING_DESC) ||
1795             (nb_desc < I40E_MIN_RING_DESC)) {
1796                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1797                             "invalid", nb_desc);
1798                 return -EINVAL;
1799         }
1800
1801         /* Free memory if needed */
1802         if (dev->data->rx_queues[queue_idx]) {
1803                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1804                 dev->data->rx_queues[queue_idx] = NULL;
1805         }
1806
1807         /* Allocate the rx queue data structure */
1808         rxq = rte_zmalloc_socket("i40e rx queue",
1809                                  sizeof(struct i40e_rx_queue),
1810                                  RTE_CACHE_LINE_SIZE,
1811                                  socket_id);
1812         if (!rxq) {
1813                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1814                             "rx queue data structure");
1815                 return -ENOMEM;
1816         }
1817         rxq->mp = mp;
1818         rxq->nb_rx_desc = nb_desc;
1819         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1820         rxq->queue_id = queue_idx;
1821         rxq->reg_idx = reg_idx;
1822         rxq->port_id = dev->data->port_id;
1823         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1824                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1825         else
1826                 rxq->crc_len = 0;
1827         rxq->drop_en = rx_conf->rx_drop_en;
1828         rxq->vsi = vsi;
1829         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1830         rxq->offloads = offloads;
1831
1832         /* Allocate the maximun number of RX ring hardware descriptor. */
1833         len = I40E_MAX_RING_DESC;
1834
1835         /**
1836          * Allocating a little more memory because vectorized/bulk_alloc Rx
1837          * functions doesn't check boundaries each time.
1838          */
1839         len += RTE_PMD_I40E_RX_MAX_BURST;
1840
1841         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1842                               I40E_DMA_MEM_ALIGN);
1843
1844         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1845                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1846         if (!rz) {
1847                 i40e_dev_rx_queue_release(rxq);
1848                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1849                 return -ENOMEM;
1850         }
1851
1852         /* Zero all the descriptors in the ring. */
1853         memset(rz->addr, 0, ring_size);
1854
1855         rxq->rx_ring_phys_addr = rz->iova;
1856         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1857
1858         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1859
1860         /* Allocate the software ring. */
1861         rxq->sw_ring =
1862                 rte_zmalloc_socket("i40e rx sw ring",
1863                                    sizeof(struct i40e_rx_entry) * len,
1864                                    RTE_CACHE_LINE_SIZE,
1865                                    socket_id);
1866         if (!rxq->sw_ring) {
1867                 i40e_dev_rx_queue_release(rxq);
1868                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1869                 return -ENOMEM;
1870         }
1871
1872         i40e_reset_rx_queue(rxq);
1873         rxq->q_set = TRUE;
1874
1875         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1876                 if (!(vsi->enabled_tc & (1 << i)))
1877                         continue;
1878                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1879                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1880                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1881                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1882                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1883
1884                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1885                         rxq->dcb_tc = i;
1886         }
1887
1888         if (dev->data->dev_started) {
1889                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1890                         i40e_dev_rx_queue_release(rxq);
1891                         return -EINVAL;
1892                 }
1893         } else {
1894                 use_def_burst_func =
1895                         check_rx_burst_bulk_alloc_preconditions(rxq);
1896                 if (!use_def_burst_func) {
1897 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1898                         PMD_INIT_LOG(DEBUG,
1899                           "Rx Burst Bulk Alloc Preconditions are "
1900                           "satisfied. Rx Burst Bulk Alloc function will be "
1901                           "used on port=%d, queue=%d.",
1902                           rxq->port_id, rxq->queue_id);
1903 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1904                 } else {
1905                         PMD_INIT_LOG(DEBUG,
1906                           "Rx Burst Bulk Alloc Preconditions are "
1907                           "not satisfied, Scattered Rx is requested, "
1908                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1909                           "not enabled on port=%d, queue=%d.",
1910                           rxq->port_id, rxq->queue_id);
1911                         ad->rx_bulk_alloc_allowed = false;
1912                 }
1913         }
1914
1915         dev->data->rx_queues[queue_idx] = rxq;
1916         return 0;
1917 }
1918
1919 void
1920 i40e_dev_rx_queue_release(void *rxq)
1921 {
1922         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1923
1924         if (!q) {
1925                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1926                 return;
1927         }
1928
1929         i40e_rx_queue_release_mbufs(q);
1930         rte_free(q->sw_ring);
1931         rte_free(q);
1932 }
1933
1934 uint32_t
1935 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1936 {
1937 #define I40E_RXQ_SCAN_INTERVAL 4
1938         volatile union i40e_rx_desc *rxdp;
1939         struct i40e_rx_queue *rxq;
1940         uint16_t desc = 0;
1941
1942         rxq = dev->data->rx_queues[rx_queue_id];
1943         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1944         while ((desc < rxq->nb_rx_desc) &&
1945                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1946                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1947                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1948                 /**
1949                  * Check the DD bit of a rx descriptor of each 4 in a group,
1950                  * to avoid checking too frequently and downgrading performance
1951                  * too much.
1952                  */
1953                 desc += I40E_RXQ_SCAN_INTERVAL;
1954                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1955                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1956                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1957                                         desc - rxq->nb_rx_desc]);
1958         }
1959
1960         return desc;
1961 }
1962
1963 int
1964 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1965 {
1966         volatile union i40e_rx_desc *rxdp;
1967         struct i40e_rx_queue *rxq = rx_queue;
1968         uint16_t desc;
1969         int ret;
1970
1971         if (unlikely(offset >= rxq->nb_rx_desc)) {
1972                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1973                 return 0;
1974         }
1975
1976         desc = rxq->rx_tail + offset;
1977         if (desc >= rxq->nb_rx_desc)
1978                 desc -= rxq->nb_rx_desc;
1979
1980         rxdp = &(rxq->rx_ring[desc]);
1981
1982         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1983                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1984                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1985
1986         return ret;
1987 }
1988
1989 int
1990 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1991 {
1992         struct i40e_rx_queue *rxq = rx_queue;
1993         volatile uint64_t *status;
1994         uint64_t mask;
1995         uint32_t desc;
1996
1997         if (unlikely(offset >= rxq->nb_rx_desc))
1998                 return -EINVAL;
1999
2000         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2001                 return RTE_ETH_RX_DESC_UNAVAIL;
2002
2003         desc = rxq->rx_tail + offset;
2004         if (desc >= rxq->nb_rx_desc)
2005                 desc -= rxq->nb_rx_desc;
2006
2007         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2008         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2009                 << I40E_RXD_QW1_STATUS_SHIFT);
2010         if (*status & mask)
2011                 return RTE_ETH_RX_DESC_DONE;
2012
2013         return RTE_ETH_RX_DESC_AVAIL;
2014 }
2015
2016 int
2017 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2018 {
2019         struct i40e_tx_queue *txq = tx_queue;
2020         volatile uint64_t *status;
2021         uint64_t mask, expect;
2022         uint32_t desc;
2023
2024         if (unlikely(offset >= txq->nb_tx_desc))
2025                 return -EINVAL;
2026
2027         desc = txq->tx_tail + offset;
2028         /* go to next desc that has the RS bit */
2029         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2030                 txq->tx_rs_thresh;
2031         if (desc >= txq->nb_tx_desc) {
2032                 desc -= txq->nb_tx_desc;
2033                 if (desc >= txq->nb_tx_desc)
2034                         desc -= txq->nb_tx_desc;
2035         }
2036
2037         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2038         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2039         expect = rte_cpu_to_le_64(
2040                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2041         if ((*status & mask) == expect)
2042                 return RTE_ETH_TX_DESC_DONE;
2043
2044         return RTE_ETH_TX_DESC_FULL;
2045 }
2046
2047 static int
2048 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2049                                 struct i40e_tx_queue *txq)
2050 {
2051         struct i40e_adapter *ad =
2052                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2053
2054         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2055                 PMD_DRV_LOG(ERR,
2056                             "Failed to do TX queue initialization");
2057                 return -EINVAL;
2058         }
2059
2060         if (i40e_dev_first_queue(txq->queue_id,
2061                                  dev->data->tx_queues,
2062                                  dev->data->nb_tx_queues)) {
2063                 /**
2064                  * If it is the first queue to setup,
2065                  * set all flags and call
2066                  * i40e_set_tx_function.
2067                  */
2068                 i40e_set_tx_function_flag(dev, txq);
2069                 i40e_set_tx_function(dev);
2070                 return 0;
2071         }
2072
2073         /* check vector conflict */
2074         if (ad->tx_vec_allowed) {
2075                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2076                     i40e_txq_vec_setup(txq)) {
2077                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2078                         return -EINVAL;
2079                 }
2080         }
2081         /* check simple tx conflict */
2082         if (ad->tx_simple_allowed) {
2083                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2084                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2085                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2086                         return -EINVAL;
2087                 }
2088         }
2089
2090         return 0;
2091 }
2092
2093 int
2094 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2095                         uint16_t queue_idx,
2096                         uint16_t nb_desc,
2097                         unsigned int socket_id,
2098                         const struct rte_eth_txconf *tx_conf)
2099 {
2100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101         struct i40e_vsi *vsi;
2102         struct i40e_pf *pf = NULL;
2103         struct i40e_vf *vf = NULL;
2104         struct i40e_tx_queue *txq;
2105         const struct rte_memzone *tz;
2106         uint32_t ring_size;
2107         uint16_t tx_rs_thresh, tx_free_thresh;
2108         uint16_t reg_idx, i, base, bsf, tc_mapping;
2109         int q_offset;
2110         uint64_t offloads;
2111
2112         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2113
2114         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2115                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2116                 vsi = &vf->vsi;
2117                 if (!vsi)
2118                         return -EINVAL;
2119                 reg_idx = queue_idx;
2120         } else {
2121                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2122                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2123                 if (!vsi)
2124                         return -EINVAL;
2125                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2126                 if (q_offset < 0)
2127                         return -EINVAL;
2128                 reg_idx = vsi->base_queue + q_offset;
2129         }
2130
2131         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2132             (nb_desc > I40E_MAX_RING_DESC) ||
2133             (nb_desc < I40E_MIN_RING_DESC)) {
2134                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2135                             "invalid", nb_desc);
2136                 return -EINVAL;
2137         }
2138
2139         /**
2140          * The following two parameters control the setting of the RS bit on
2141          * transmit descriptors. TX descriptors will have their RS bit set
2142          * after txq->tx_rs_thresh descriptors have been used. The TX
2143          * descriptor ring will be cleaned after txq->tx_free_thresh
2144          * descriptors are used or if the number of descriptors required to
2145          * transmit a packet is greater than the number of free TX descriptors.
2146          *
2147          * The following constraints must be satisfied:
2148          *  - tx_rs_thresh must be greater than 0.
2149          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2150          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2151          *  - tx_rs_thresh must be a divisor of the ring size.
2152          *  - tx_free_thresh must be greater than 0.
2153          *  - tx_free_thresh must be less than the size of the ring minus 3.
2154          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2155          *
2156          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2157          * race condition, hence the maximum threshold constraints. When set
2158          * to zero use default values.
2159          */
2160         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2161                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2162         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2163         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2164                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2165         if (tx_conf->tx_rs_thresh > 0)
2166                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2167         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2168                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2169                                 "exceed nb_desc. (tx_rs_thresh=%u "
2170                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2171                                 (unsigned int)tx_rs_thresh,
2172                                 (unsigned int)tx_free_thresh,
2173                                 (unsigned int)nb_desc,
2174                                 (int)dev->data->port_id,
2175                                 (int)queue_idx);
2176                 return I40E_ERR_PARAM;
2177         }
2178         if (tx_rs_thresh >= (nb_desc - 2)) {
2179                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2180                              "number of TX descriptors minus 2. "
2181                              "(tx_rs_thresh=%u port=%d queue=%d)",
2182                              (unsigned int)tx_rs_thresh,
2183                              (int)dev->data->port_id,
2184                              (int)queue_idx);
2185                 return I40E_ERR_PARAM;
2186         }
2187         if (tx_free_thresh >= (nb_desc - 3)) {
2188                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2189                              "number of TX descriptors minus 3. "
2190                              "(tx_free_thresh=%u port=%d queue=%d)",
2191                              (unsigned int)tx_free_thresh,
2192                              (int)dev->data->port_id,
2193                              (int)queue_idx);
2194                 return I40E_ERR_PARAM;
2195         }
2196         if (tx_rs_thresh > tx_free_thresh) {
2197                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2198                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2199                              " tx_rs_thresh=%u port=%d queue=%d)",
2200                              (unsigned int)tx_free_thresh,
2201                              (unsigned int)tx_rs_thresh,
2202                              (int)dev->data->port_id,
2203                              (int)queue_idx);
2204                 return I40E_ERR_PARAM;
2205         }
2206         if ((nb_desc % tx_rs_thresh) != 0) {
2207                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2208                              "number of TX descriptors. (tx_rs_thresh=%u"
2209                              " port=%d queue=%d)",
2210                              (unsigned int)tx_rs_thresh,
2211                              (int)dev->data->port_id,
2212                              (int)queue_idx);
2213                 return I40E_ERR_PARAM;
2214         }
2215         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2216                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2217                              "tx_rs_thresh is greater than 1. "
2218                              "(tx_rs_thresh=%u port=%d queue=%d)",
2219                              (unsigned int)tx_rs_thresh,
2220                              (int)dev->data->port_id,
2221                              (int)queue_idx);
2222                 return I40E_ERR_PARAM;
2223         }
2224
2225         /* Free memory if needed. */
2226         if (dev->data->tx_queues[queue_idx]) {
2227                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2228                 dev->data->tx_queues[queue_idx] = NULL;
2229         }
2230
2231         /* Allocate the TX queue data structure. */
2232         txq = rte_zmalloc_socket("i40e tx queue",
2233                                   sizeof(struct i40e_tx_queue),
2234                                   RTE_CACHE_LINE_SIZE,
2235                                   socket_id);
2236         if (!txq) {
2237                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2238                             "tx queue structure");
2239                 return -ENOMEM;
2240         }
2241
2242         /* Allocate TX hardware ring descriptors. */
2243         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2244         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2245         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2246                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2247         if (!tz) {
2248                 i40e_dev_tx_queue_release(txq);
2249                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2250                 return -ENOMEM;
2251         }
2252
2253         txq->nb_tx_desc = nb_desc;
2254         txq->tx_rs_thresh = tx_rs_thresh;
2255         txq->tx_free_thresh = tx_free_thresh;
2256         txq->pthresh = tx_conf->tx_thresh.pthresh;
2257         txq->hthresh = tx_conf->tx_thresh.hthresh;
2258         txq->wthresh = tx_conf->tx_thresh.wthresh;
2259         txq->queue_id = queue_idx;
2260         txq->reg_idx = reg_idx;
2261         txq->port_id = dev->data->port_id;
2262         txq->offloads = offloads;
2263         txq->vsi = vsi;
2264         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2265
2266         txq->tx_ring_phys_addr = tz->iova;
2267         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2268
2269         /* Allocate software ring */
2270         txq->sw_ring =
2271                 rte_zmalloc_socket("i40e tx sw ring",
2272                                    sizeof(struct i40e_tx_entry) * nb_desc,
2273                                    RTE_CACHE_LINE_SIZE,
2274                                    socket_id);
2275         if (!txq->sw_ring) {
2276                 i40e_dev_tx_queue_release(txq);
2277                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2278                 return -ENOMEM;
2279         }
2280
2281         i40e_reset_tx_queue(txq);
2282         txq->q_set = TRUE;
2283
2284         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2285                 if (!(vsi->enabled_tc & (1 << i)))
2286                         continue;
2287                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2288                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2289                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2290                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2291                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2292
2293                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2294                         txq->dcb_tc = i;
2295         }
2296
2297         if (dev->data->dev_started) {
2298                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2299                         i40e_dev_tx_queue_release(txq);
2300                         return -EINVAL;
2301                 }
2302         } else {
2303                 /**
2304                  * Use a simple TX queue without offloads or
2305                  * multi segs if possible
2306                  */
2307                 i40e_set_tx_function_flag(dev, txq);
2308         }
2309         dev->data->tx_queues[queue_idx] = txq;
2310
2311         return 0;
2312 }
2313
2314 void
2315 i40e_dev_tx_queue_release(void *txq)
2316 {
2317         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2318
2319         if (!q) {
2320                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2321                 return;
2322         }
2323
2324         i40e_tx_queue_release_mbufs(q);
2325         rte_free(q->sw_ring);
2326         rte_free(q);
2327 }
2328
2329 const struct rte_memzone *
2330 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2331 {
2332         const struct rte_memzone *mz;
2333
2334         mz = rte_memzone_lookup(name);
2335         if (mz)
2336                 return mz;
2337
2338         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2339                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2340         return mz;
2341 }
2342
2343 void
2344 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2345 {
2346         uint16_t i;
2347
2348         /* SSE Vector driver has a different way of releasing mbufs. */
2349         if (rxq->rx_using_sse) {
2350                 i40e_rx_queue_release_mbufs_vec(rxq);
2351                 return;
2352         }
2353
2354         if (!rxq->sw_ring) {
2355                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2356                 return;
2357         }
2358
2359         for (i = 0; i < rxq->nb_rx_desc; i++) {
2360                 if (rxq->sw_ring[i].mbuf) {
2361                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2362                         rxq->sw_ring[i].mbuf = NULL;
2363                 }
2364         }
2365 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2366         if (rxq->rx_nb_avail == 0)
2367                 return;
2368         for (i = 0; i < rxq->rx_nb_avail; i++) {
2369                 struct rte_mbuf *mbuf;
2370
2371                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2372                 rte_pktmbuf_free_seg(mbuf);
2373         }
2374         rxq->rx_nb_avail = 0;
2375 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2376 }
2377
2378 void
2379 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2380 {
2381         unsigned i;
2382         uint16_t len;
2383
2384         if (!rxq) {
2385                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2386                 return;
2387         }
2388
2389 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2390         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2391                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2392         else
2393 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2394                 len = rxq->nb_rx_desc;
2395
2396         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2397                 ((volatile char *)rxq->rx_ring)[i] = 0;
2398
2399         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2400         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2401                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2402
2403 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2404         rxq->rx_nb_avail = 0;
2405         rxq->rx_next_avail = 0;
2406         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2407 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2408         rxq->rx_tail = 0;
2409         rxq->nb_rx_hold = 0;
2410         rxq->pkt_first_seg = NULL;
2411         rxq->pkt_last_seg = NULL;
2412
2413         rxq->rxrearm_start = 0;
2414         rxq->rxrearm_nb = 0;
2415 }
2416
2417 void
2418 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2419 {
2420         struct rte_eth_dev *dev;
2421         uint16_t i;
2422
2423         if (!txq || !txq->sw_ring) {
2424                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2425                 return;
2426         }
2427
2428         dev = &rte_eth_devices[txq->port_id];
2429
2430         /**
2431          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2432          *  so need to free remains more carefully.
2433          */
2434         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2435                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2436                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2437                 if (txq->tx_tail < i) {
2438                         for (; i < txq->nb_tx_desc; i++) {
2439                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2440                                 txq->sw_ring[i].mbuf = NULL;
2441                         }
2442                         i = 0;
2443                 }
2444                 for (; i < txq->tx_tail; i++) {
2445                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2446                         txq->sw_ring[i].mbuf = NULL;
2447                 }
2448         } else {
2449                 for (i = 0; i < txq->nb_tx_desc; i++) {
2450                         if (txq->sw_ring[i].mbuf) {
2451                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2452                                 txq->sw_ring[i].mbuf = NULL;
2453                         }
2454                 }
2455         }
2456 }
2457
2458 void
2459 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2460 {
2461         struct i40e_tx_entry *txe;
2462         uint16_t i, prev, size;
2463
2464         if (!txq) {
2465                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2466                 return;
2467         }
2468
2469         txe = txq->sw_ring;
2470         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2471         for (i = 0; i < size; i++)
2472                 ((volatile char *)txq->tx_ring)[i] = 0;
2473
2474         prev = (uint16_t)(txq->nb_tx_desc - 1);
2475         for (i = 0; i < txq->nb_tx_desc; i++) {
2476                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2477
2478                 txd->cmd_type_offset_bsz =
2479                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2480                 txe[i].mbuf =  NULL;
2481                 txe[i].last_id = i;
2482                 txe[prev].next_id = i;
2483                 prev = i;
2484         }
2485
2486         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2487         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2488
2489         txq->tx_tail = 0;
2490         txq->nb_tx_used = 0;
2491
2492         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2493         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2494 }
2495
2496 /* Init the TX queue in hardware */
2497 int
2498 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2499 {
2500         enum i40e_status_code err = I40E_SUCCESS;
2501         struct i40e_vsi *vsi = txq->vsi;
2502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2503         uint16_t pf_q = txq->reg_idx;
2504         struct i40e_hmc_obj_txq tx_ctx;
2505         uint32_t qtx_ctl;
2506
2507         /* clear the context structure first */
2508         memset(&tx_ctx, 0, sizeof(tx_ctx));
2509         tx_ctx.new_context = 1;
2510         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2511         tx_ctx.qlen = txq->nb_tx_desc;
2512
2513 #ifdef RTE_LIBRTE_IEEE1588
2514         tx_ctx.timesync_ena = 1;
2515 #endif
2516         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2517         if (vsi->type == I40E_VSI_FDIR)
2518                 tx_ctx.fd_ena = TRUE;
2519
2520         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2521         if (err != I40E_SUCCESS) {
2522                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2523                 return err;
2524         }
2525
2526         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2527         if (err != I40E_SUCCESS) {
2528                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2529                 return err;
2530         }
2531
2532         /* Now associate this queue with this PCI function */
2533         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2534         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2535                                         I40E_QTX_CTL_PF_INDX_MASK);
2536         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2537         I40E_WRITE_FLUSH(hw);
2538
2539         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2540
2541         return err;
2542 }
2543
2544 int
2545 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2546 {
2547         struct i40e_rx_entry *rxe = rxq->sw_ring;
2548         uint64_t dma_addr;
2549         uint16_t i;
2550
2551         for (i = 0; i < rxq->nb_rx_desc; i++) {
2552                 volatile union i40e_rx_desc *rxd;
2553                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2554
2555                 if (unlikely(!mbuf)) {
2556                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2557                         return -ENOMEM;
2558                 }
2559
2560                 rte_mbuf_refcnt_set(mbuf, 1);
2561                 mbuf->next = NULL;
2562                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2563                 mbuf->nb_segs = 1;
2564                 mbuf->port = rxq->port_id;
2565
2566                 dma_addr =
2567                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2568
2569                 rxd = &rxq->rx_ring[i];
2570                 rxd->read.pkt_addr = dma_addr;
2571                 rxd->read.hdr_addr = 0;
2572 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2573                 rxd->read.rsvd1 = 0;
2574                 rxd->read.rsvd2 = 0;
2575 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2576
2577                 rxe[i].mbuf = mbuf;
2578         }
2579
2580         return 0;
2581 }
2582
2583 /*
2584  * Calculate the buffer length, and check the jumbo frame
2585  * and maximum packet length.
2586  */
2587 static int
2588 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2589 {
2590         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2591         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2592         struct rte_eth_dev_data *data = pf->dev_data;
2593         uint16_t buf_size;
2594
2595         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2596                 RTE_PKTMBUF_HEADROOM);
2597
2598         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2599                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2600         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2601                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2602                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2603                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2604                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2605                 rxq->hs_mode = i40e_header_split_enabled;
2606                 break;
2607         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2608         default:
2609                 rxq->rx_hdr_len = 0;
2610                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2611                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2612                 rxq->hs_mode = i40e_header_split_none;
2613                 break;
2614         }
2615
2616         rxq->max_pkt_len =
2617                 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2618                         rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2619         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2620                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
2621                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2622                         PMD_DRV_LOG(ERR, "maximum packet length must "
2623                                     "be larger than %u and smaller than %u,"
2624                                     "as jumbo frame is enabled",
2625                                     (uint32_t)RTE_ETHER_MAX_LEN,
2626                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2627                         return I40E_ERR_CONFIG;
2628                 }
2629         } else {
2630                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2631                         rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
2632                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2633                                     "larger than %u and smaller than %u, "
2634                                     "as jumbo frame is disabled",
2635                                     (uint32_t)RTE_ETHER_MIN_LEN,
2636                                     (uint32_t)RTE_ETHER_MAX_LEN);
2637                         return I40E_ERR_CONFIG;
2638                 }
2639         }
2640
2641         return 0;
2642 }
2643
2644 /* Init the RX queue in hardware */
2645 int
2646 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2647 {
2648         int err = I40E_SUCCESS;
2649         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2650         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2651         uint16_t pf_q = rxq->reg_idx;
2652         uint16_t buf_size;
2653         struct i40e_hmc_obj_rxq rx_ctx;
2654
2655         err = i40e_rx_queue_config(rxq);
2656         if (err < 0) {
2657                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2658                 return err;
2659         }
2660
2661         /* Clear the context structure first */
2662         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2663         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2664         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2665
2666         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2667         rx_ctx.qlen = rxq->nb_rx_desc;
2668 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2669         rx_ctx.dsize = 1;
2670 #endif
2671         rx_ctx.dtype = rxq->hs_mode;
2672         if (rxq->hs_mode)
2673                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2674         else
2675                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2676         rx_ctx.rxmax = rxq->max_pkt_len;
2677         rx_ctx.tphrdesc_ena = 1;
2678         rx_ctx.tphwdesc_ena = 1;
2679         rx_ctx.tphdata_ena = 1;
2680         rx_ctx.tphhead_ena = 1;
2681         rx_ctx.lrxqthresh = 2;
2682         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2683         rx_ctx.l2tsel = 1;
2684         /* showiv indicates if inner VLAN is stripped inside of tunnel
2685          * packet. When set it to 1, vlan information is stripped from
2686          * the inner header, but the hardware does not put it in the
2687          * descriptor. So set it zero by default.
2688          */
2689         rx_ctx.showiv = 0;
2690         rx_ctx.prefena = 1;
2691
2692         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2693         if (err != I40E_SUCCESS) {
2694                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2695                 return err;
2696         }
2697         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2698         if (err != I40E_SUCCESS) {
2699                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2700                 return err;
2701         }
2702
2703         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2704
2705         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2706                 RTE_PKTMBUF_HEADROOM);
2707
2708         /* Check if scattered RX needs to be used. */
2709         if (rxq->max_pkt_len > buf_size)
2710                 dev_data->scattered_rx = 1;
2711
2712         /* Init the RX tail regieter. */
2713         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2714
2715         return 0;
2716 }
2717
2718 void
2719 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2720 {
2721         uint16_t i;
2722
2723         PMD_INIT_FUNC_TRACE();
2724
2725         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2726                 if (!dev->data->tx_queues[i])
2727                         continue;
2728                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2729                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2730         }
2731
2732         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2733                 if (!dev->data->rx_queues[i])
2734                         continue;
2735                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2736                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2737         }
2738 }
2739
2740 void
2741 i40e_dev_free_queues(struct rte_eth_dev *dev)
2742 {
2743         uint16_t i;
2744
2745         PMD_INIT_FUNC_TRACE();
2746
2747         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2748                 if (!dev->data->rx_queues[i])
2749                         continue;
2750                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2751                 dev->data->rx_queues[i] = NULL;
2752         }
2753
2754         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2755                 if (!dev->data->tx_queues[i])
2756                         continue;
2757                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2758                 dev->data->tx_queues[i] = NULL;
2759         }
2760 }
2761
2762 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2763 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2764
2765 enum i40e_status_code
2766 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2767 {
2768         struct i40e_tx_queue *txq;
2769         const struct rte_memzone *tz = NULL;
2770         uint32_t ring_size;
2771         struct rte_eth_dev *dev;
2772
2773         if (!pf) {
2774                 PMD_DRV_LOG(ERR, "PF is not available");
2775                 return I40E_ERR_BAD_PTR;
2776         }
2777
2778         dev = pf->adapter->eth_dev;
2779
2780         /* Allocate the TX queue data structure. */
2781         txq = rte_zmalloc_socket("i40e fdir tx queue",
2782                                   sizeof(struct i40e_tx_queue),
2783                                   RTE_CACHE_LINE_SIZE,
2784                                   SOCKET_ID_ANY);
2785         if (!txq) {
2786                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2787                                         "tx queue structure.");
2788                 return I40E_ERR_NO_MEMORY;
2789         }
2790
2791         /* Allocate TX hardware ring descriptors. */
2792         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2793         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2794
2795         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2796                                       I40E_FDIR_QUEUE_ID, ring_size,
2797                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2798         if (!tz) {
2799                 i40e_dev_tx_queue_release(txq);
2800                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2801                 return I40E_ERR_NO_MEMORY;
2802         }
2803
2804         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2805         txq->queue_id = I40E_FDIR_QUEUE_ID;
2806         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2807         txq->vsi = pf->fdir.fdir_vsi;
2808
2809         txq->tx_ring_phys_addr = tz->iova;
2810         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2811         /*
2812          * don't need to allocate software ring and reset for the fdir
2813          * program queue just set the queue has been configured.
2814          */
2815         txq->q_set = TRUE;
2816         pf->fdir.txq = txq;
2817
2818         return I40E_SUCCESS;
2819 }
2820
2821 enum i40e_status_code
2822 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2823 {
2824         struct i40e_rx_queue *rxq;
2825         const struct rte_memzone *rz = NULL;
2826         uint32_t ring_size;
2827         struct rte_eth_dev *dev;
2828
2829         if (!pf) {
2830                 PMD_DRV_LOG(ERR, "PF is not available");
2831                 return I40E_ERR_BAD_PTR;
2832         }
2833
2834         dev = pf->adapter->eth_dev;
2835
2836         /* Allocate the RX queue data structure. */
2837         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2838                                   sizeof(struct i40e_rx_queue),
2839                                   RTE_CACHE_LINE_SIZE,
2840                                   SOCKET_ID_ANY);
2841         if (!rxq) {
2842                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2843                                         "rx queue structure.");
2844                 return I40E_ERR_NO_MEMORY;
2845         }
2846
2847         /* Allocate RX hardware ring descriptors. */
2848         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2849         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2850
2851         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2852                                       I40E_FDIR_QUEUE_ID, ring_size,
2853                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2854         if (!rz) {
2855                 i40e_dev_rx_queue_release(rxq);
2856                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2857                 return I40E_ERR_NO_MEMORY;
2858         }
2859
2860         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2861         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2862         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2863         rxq->vsi = pf->fdir.fdir_vsi;
2864
2865         rxq->rx_ring_phys_addr = rz->iova;
2866         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2867         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2868
2869         /*
2870          * Don't need to allocate software ring and reset for the fdir
2871          * rx queue, just set the queue has been configured.
2872          */
2873         rxq->q_set = TRUE;
2874         pf->fdir.rxq = rxq;
2875
2876         return I40E_SUCCESS;
2877 }
2878
2879 void
2880 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2881         struct rte_eth_rxq_info *qinfo)
2882 {
2883         struct i40e_rx_queue *rxq;
2884
2885         rxq = dev->data->rx_queues[queue_id];
2886
2887         qinfo->mp = rxq->mp;
2888         qinfo->scattered_rx = dev->data->scattered_rx;
2889         qinfo->nb_desc = rxq->nb_rx_desc;
2890
2891         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2892         qinfo->conf.rx_drop_en = rxq->drop_en;
2893         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2894         qinfo->conf.offloads = rxq->offloads;
2895 }
2896
2897 void
2898 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2899         struct rte_eth_txq_info *qinfo)
2900 {
2901         struct i40e_tx_queue *txq;
2902
2903         txq = dev->data->tx_queues[queue_id];
2904
2905         qinfo->nb_desc = txq->nb_tx_desc;
2906
2907         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2908         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2909         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2910
2911         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2912         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2913         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2914         qinfo->conf.offloads = txq->offloads;
2915 }
2916
2917 static eth_rx_burst_t
2918 i40e_get_latest_rx_vec(bool scatter)
2919 {
2920 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2921         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
2922                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2923                                  i40e_recv_pkts_vec_avx2;
2924 #endif
2925         return scatter ? i40e_recv_scattered_pkts_vec :
2926                          i40e_recv_pkts_vec;
2927 }
2928
2929 static eth_rx_burst_t
2930 i40e_get_recommend_rx_vec(bool scatter)
2931 {
2932 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2933         /*
2934          * since AVX frequency can be different to base frequency, limit
2935          * use of AVX2 version to later plaforms, not all those that could
2936          * theoretically run it.
2937          */
2938         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2939                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2940                                  i40e_recv_pkts_vec_avx2;
2941 #endif
2942         return scatter ? i40e_recv_scattered_pkts_vec :
2943                          i40e_recv_pkts_vec;
2944 }
2945
2946 void __attribute__((cold))
2947 i40e_set_rx_function(struct rte_eth_dev *dev)
2948 {
2949         struct i40e_adapter *ad =
2950                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2951         uint16_t rx_using_sse, i;
2952         /* In order to allow Vector Rx there are a few configuration
2953          * conditions to be met and Rx Bulk Allocation should be allowed.
2954          */
2955         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2956                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2957                     !ad->rx_bulk_alloc_allowed) {
2958                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2959                                      " Vector Rx preconditions",
2960                                      dev->data->port_id);
2961
2962                         ad->rx_vec_allowed = false;
2963                 }
2964                 if (ad->rx_vec_allowed) {
2965                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2966                                 struct i40e_rx_queue *rxq =
2967                                         dev->data->rx_queues[i];
2968
2969                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2970                                         ad->rx_vec_allowed = false;
2971                                         break;
2972                                 }
2973                         }
2974                 }
2975         }
2976
2977         if (ad->rx_vec_allowed) {
2978                 /* Vec Rx path */
2979                 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
2980                                 dev->data->port_id);
2981                 if (ad->use_latest_vec)
2982                         dev->rx_pkt_burst =
2983                         i40e_get_latest_rx_vec(dev->data->scattered_rx);
2984                 else
2985                         dev->rx_pkt_burst =
2986                         i40e_get_recommend_rx_vec(dev->data->scattered_rx);
2987         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
2988                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2989                                     "satisfied. Rx Burst Bulk Alloc function "
2990                                     "will be used on port=%d.",
2991                              dev->data->port_id);
2992
2993                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2994         } else {
2995                 /* Simple Rx Path. */
2996                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
2997                              dev->data->port_id);
2998                 dev->rx_pkt_burst = dev->data->scattered_rx ?
2999                                         i40e_recv_scattered_pkts :
3000                                         i40e_recv_pkts;
3001         }
3002
3003         /* Propagate information about RX function choice through all queues. */
3004         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3005                 rx_using_sse =
3006                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3007                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3008                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3009                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3010
3011                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3012                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3013
3014                         if (rxq)
3015                                 rxq->rx_using_sse = rx_using_sse;
3016                 }
3017         }
3018 }
3019
3020 static const struct {
3021         eth_rx_burst_t pkt_burst;
3022         const char *info;
3023 } i40e_rx_burst_infos[] = {
3024         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3025         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3026         { i40e_recv_pkts,                    "Scalar" },
3027 #ifdef RTE_ARCH_X86
3028         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3029         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3030         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3031         { i40e_recv_pkts_vec,                "Vector SSE" },
3032 #elif defined(RTE_ARCH_ARM64)
3033         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3034         { i40e_recv_pkts_vec,                "Vector Neon" },
3035 #elif defined(RTE_ARCH_PPC_64)
3036         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3037         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3038 #endif
3039 };
3040
3041 int
3042 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3043                        struct rte_eth_burst_mode *mode)
3044 {
3045         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3046         int ret = -EINVAL;
3047         unsigned int i;
3048
3049         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3050                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3051                         snprintf(mode->info, sizeof(mode->info), "%s",
3052                                  i40e_rx_burst_infos[i].info);
3053                         ret = 0;
3054                         break;
3055                 }
3056         }
3057
3058         return ret;
3059 }
3060
3061 void __attribute__((cold))
3062 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3063 {
3064         struct i40e_adapter *ad =
3065                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3066
3067         /* Use a simple Tx queue if possible (only fast free is allowed) */
3068         ad->tx_simple_allowed =
3069                 (txq->offloads ==
3070                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3071                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3072         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3073                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3074
3075         if (ad->tx_vec_allowed)
3076                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3077                                 txq->queue_id);
3078         else if (ad->tx_simple_allowed)
3079                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3080                                 txq->queue_id);
3081         else
3082                 PMD_INIT_LOG(DEBUG,
3083                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3084                                 txq->queue_id);
3085 }
3086
3087 static eth_tx_burst_t
3088 i40e_get_latest_tx_vec(void)
3089 {
3090 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3091         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3092                 return i40e_xmit_pkts_vec_avx2;
3093 #endif
3094         return i40e_xmit_pkts_vec;
3095 }
3096
3097 static eth_tx_burst_t
3098 i40e_get_recommend_tx_vec(void)
3099 {
3100 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3101         /*
3102          * since AVX frequency can be different to base frequency, limit
3103          * use of AVX2 version to later plaforms, not all those that could
3104          * theoretically run it.
3105          */
3106         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3107                 return i40e_xmit_pkts_vec_avx2;
3108 #endif
3109         return i40e_xmit_pkts_vec;
3110 }
3111
3112 void __attribute__((cold))
3113 i40e_set_tx_function(struct rte_eth_dev *dev)
3114 {
3115         struct i40e_adapter *ad =
3116                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3117         int i;
3118
3119         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3120                 if (ad->tx_vec_allowed) {
3121                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3122                                 struct i40e_tx_queue *txq =
3123                                         dev->data->tx_queues[i];
3124
3125                                 if (txq && i40e_txq_vec_setup(txq)) {
3126                                         ad->tx_vec_allowed = false;
3127                                         break;
3128                                 }
3129                         }
3130                 }
3131         }
3132
3133         if (ad->tx_simple_allowed) {
3134                 if (ad->tx_vec_allowed) {
3135                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3136                         if (ad->use_latest_vec)
3137                                 dev->tx_pkt_burst =
3138                                         i40e_get_latest_tx_vec();
3139                         else
3140                                 dev->tx_pkt_burst =
3141                                         i40e_get_recommend_tx_vec();
3142                 } else {
3143                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3144                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3145                 }
3146                 dev->tx_pkt_prepare = NULL;
3147         } else {
3148                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3149                 dev->tx_pkt_burst = i40e_xmit_pkts;
3150                 dev->tx_pkt_prepare = i40e_prep_pkts;
3151         }
3152 }
3153
3154 static const struct {
3155         eth_tx_burst_t pkt_burst;
3156         const char *info;
3157 } i40e_tx_burst_infos[] = {
3158         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3159         { i40e_xmit_pkts,          "Scalar" },
3160 #ifdef RTE_ARCH_X86
3161         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3162         { i40e_xmit_pkts_vec,      "Vector SSE" },
3163 #elif defined(RTE_ARCH_ARM64)
3164         { i40e_xmit_pkts_vec,      "Vector Neon" },
3165 #elif defined(RTE_ARCH_PPC_64)
3166         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3167 #endif
3168 };
3169
3170 int
3171 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3172                        struct rte_eth_burst_mode *mode)
3173 {
3174         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3175         int ret = -EINVAL;
3176         unsigned int i;
3177
3178         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3179                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3180                         snprintf(mode->info, sizeof(mode->info), "%s",
3181                                  i40e_tx_burst_infos[i].info);
3182                         ret = 0;
3183                         break;
3184                 }
3185         }
3186
3187         return ret;
3188 }
3189
3190 void __attribute__((cold))
3191 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3192 {
3193         struct i40e_adapter *ad =
3194                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3195         int i;
3196
3197         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3198                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3199 }
3200
3201 void __attribute__((cold))
3202 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3203 {
3204         struct i40e_adapter *ad =
3205                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3207         int i;
3208
3209         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3210                 ad->pctypes_tbl[i] = 0ULL;
3211         ad->flow_types_mask = 0ULL;
3212         ad->pctypes_mask = 0ULL;
3213
3214         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3215                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3216         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3217                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3218         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3219                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3220         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3221                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3222         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3223                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3224         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3225                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3226         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3227                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3228         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3229                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3230         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3231                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3232         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3233                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3234         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3235                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3236
3237         if (hw->mac.type == I40E_MAC_X722 ||
3238                 hw->mac.type == I40E_MAC_X722_VF) {
3239                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3240                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3241                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3242                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3243                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3244                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3245                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3246                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3247                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3248                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3249                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3250                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3251         }
3252
3253         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3254                 if (ad->pctypes_tbl[i])
3255                         ad->flow_types_mask |= (1ULL << i);
3256                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3257         }
3258 }
3259
3260 #ifndef RTE_LIBRTE_I40E_INC_VECTOR
3261 /* Stubs needed for linkage when CONFIG_RTE_LIBRTE_I40E_INC_VECTOR is set to 'n' */
3262 int
3263 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3264 {
3265         return -1;
3266 }
3267
3268 uint16_t
3269 i40e_recv_pkts_vec(
3270         void __rte_unused *rx_queue,
3271         struct rte_mbuf __rte_unused **rx_pkts,
3272         uint16_t __rte_unused nb_pkts)
3273 {
3274         return 0;
3275 }
3276
3277 uint16_t
3278 i40e_recv_scattered_pkts_vec(
3279         void __rte_unused *rx_queue,
3280         struct rte_mbuf __rte_unused **rx_pkts,
3281         uint16_t __rte_unused nb_pkts)
3282 {
3283         return 0;
3284 }
3285
3286 int
3287 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3288 {
3289         return -1;
3290 }
3291
3292 int
3293 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3294 {
3295         return -1;
3296 }
3297
3298 void
3299 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3300 {
3301         return;
3302 }
3303
3304 uint16_t
3305 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3306                           struct rte_mbuf __rte_unused **tx_pkts,
3307                           uint16_t __rte_unused nb_pkts)
3308 {
3309         return 0;
3310 }
3311 #endif /* ifndef RTE_LIBRTE_I40E_INC_VECTOR */
3312
3313 #ifndef CC_AVX2_SUPPORT
3314 uint16_t
3315 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3316                         struct rte_mbuf __rte_unused **rx_pkts,
3317                         uint16_t __rte_unused nb_pkts)
3318 {
3319         return 0;
3320 }
3321
3322 uint16_t
3323 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3324                         struct rte_mbuf __rte_unused **rx_pkts,
3325                         uint16_t __rte_unused nb_pkts)
3326 {
3327         return 0;
3328 }
3329
3330 uint16_t
3331 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3332                           struct rte_mbuf __rte_unused **tx_pkts,
3333                           uint16_t __rte_unused nb_pkts)
3334 {
3335         return 0;
3336 }
3337 #endif /* ifndef CC_AVX2_SUPPORT */