In the current state, when preforming read/write
transactions we must wait for a completion in order
to run the next transaction, and all transactions are
performed by order.
Relaxed Ordering is a PCI optimization which by enabling it
we allow the system to perform read/writes in a different
order without having to wait for completion and improve
the performance in that matter.
This commit introduces the creation of relaxed ordering
memory regions in mlx5.
As relaxed ordering is an optimization, drivers that
do not support it can simply ignore it and therefore
it is enabled by default.
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Updated Mellanox mlx5 driver with new features and improvements, including:
* Added support for matching on IPv4 Time To Live and IPv6 Hop Limit.
Updated Mellanox mlx5 driver with new features and improvements, including:
* Added support for matching on IPv4 Time To Live and IPv6 Hop Limit.
+ * Added support for creating Relaxed Ordering Memory Regions.
* **Updated the AESNI MB crypto PMD.**
* **Updated the AESNI MB crypto PMD.**
MLX5_SET(mkc, mkc, pd, attr->pd);
MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
MLX5_SET(mkc, mkc, pd, attr->pd);
MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
+ if (attr->relaxed_ordering == 1) {
+ MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1);
+ MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1);
+ }
MLX5_SET64(mkc, mkc, start_addr, attr->addr);
MLX5_SET64(mkc, mkc, len, attr->size);
mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
MLX5_SET64(mkc, mkc, start_addr, attr->addr);
MLX5_SET64(mkc, mkc, len, attr->size);
mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
uint32_t pd;
uint32_t log_entity_size;
uint32_t pg_access:1;
uint32_t pd;
uint32_t log_entity_size;
uint32_t pg_access:1;
+ uint32_t relaxed_ordering:1;
struct mlx5_klm *klm_array;
int klm_num;
};
struct mlx5_klm *klm_array;
int klm_num;
};
uint64_t comp_mask; };
#endif
uint64_t comp_mask; };
#endif
+#ifndef IBV_ACCESS_RELAXED_ORDERING
+#define IBV_ACCESS_RELAXED_ORDERING 0
+#endif
+
/* LIB_GLUE_VERSION must be updated every time this structure is modified. */
struct mlx5_glue {
const char *version;
/* LIB_GLUE_VERSION must be updated every time this structure is modified. */
struct mlx5_glue {
const char *version;
u8 translations_octword_size[0x20];
u8 translations_octword_size[0x20];
- u8 reserved_at_1c0[0x1b];
+ u8 reserved_at_1c0[0x19];
+ u8 relaxed_ordering_read[0x1];
+ u8 reserved_at_1da[0x1];
u8 log_page_size[0x5];
u8 reserved_at_1e0[0x20];
u8 log_page_size[0x5];
u8 reserved_at_1e0[0x20];
mkey_attr.pg_access = 0;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
mkey_attr.pg_access = 0;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
+ mkey_attr.relaxed_ordering = 1;
mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
if (!mem_mng->dm) {
mlx5_glue->devx_umem_dereg(mem_mng->umem);
mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
if (!mem_mng->dm) {
mlx5_glue->devx_umem_dereg(mem_mng->umem);
* through mlx5_alloc_verbs_buf().
*/
mr->ibv_mr = mlx5_glue->reg_mr(sh->pd, (void *)data.start, len,
* through mlx5_alloc_verbs_buf().
*/
mr->ibv_mr = mlx5_glue->reg_mr(sh->pd, (void *)data.start, len,
- IBV_ACCESS_LOCAL_WRITE);
+ IBV_ACCESS_LOCAL_WRITE |
+ IBV_ACCESS_RELAXED_ORDERING);
if (mr->ibv_mr == NULL) {
DEBUG("port %u fail to create a verbs MR for address (%p)",
dev->data->port_id, (void *)addr);
if (mr->ibv_mr == NULL) {
DEBUG("port %u fail to create a verbs MR for address (%p)",
dev->data->port_id, (void *)addr);
if (mr == NULL)
return NULL;
mr->ibv_mr = mlx5_glue->reg_mr(priv->sh->pd, (void *)addr, len,
if (mr == NULL)
return NULL;
mr->ibv_mr = mlx5_glue->reg_mr(priv->sh->pd, (void *)addr, len,
- IBV_ACCESS_LOCAL_WRITE);
+ IBV_ACCESS_LOCAL_WRITE |
+ IBV_ACCESS_RELAXED_ORDERING);
if (mr->ibv_mr == NULL) {
DRV_LOG(WARNING,
"port %u fail to create a verbs MR for address (%p)",
if (mr->ibv_mr == NULL) {
DRV_LOG(WARNING,
"port %u fail to create a verbs MR for address (%p)",
.pg_access = 1,
.klm_array = NULL,
.klm_num = 0,
.pg_access = 1,
.klm_array = NULL,
.klm_num = 0,
};
struct mlx5_devx_virtq_attr attr = {
.type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS,
};
struct mlx5_devx_virtq_attr attr = {
.type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS,
mkey_attr.pg_access = 1;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
mkey_attr.pg_access = 1;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
+ mkey_attr.relaxed_ordering = 0;
entry->mkey = mlx5_devx_cmd_mkey_create(priv->ctx, &mkey_attr);
if (!entry->mkey) {
DRV_LOG(ERR, "Failed to create direct Mkey.");
entry->mkey = mlx5_devx_cmd_mkey_create(priv->ctx, &mkey_attr);
if (!entry->mkey) {
DRV_LOG(ERR, "Failed to create direct Mkey.");