Since selftest now depends on dynamic mbuf fields it is not
feasible to run selftest on device probe.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
-a 0002:0e:00.0,qos=[1-50-50-50]
-a 0002:0e:00.0,qos=[1-50-50-50]
-- ``Selftest``
-
- The functionality of OCTEON TX2 eventdev can be verified using this option,
- various unit and functional tests are run to verify the sanity.
- The tests are run once the vdev creation is successfully complete.
- For example::
-
- -a 0002:0e:00.0,selftest=1
-
- ``TIM disable NPA``
By default chunks are allocated from NPA then TIM can automatically free
- ``TIM disable NPA``
By default chunks are allocated from NPA then TIM can automatically free
#define OTX2_SSO_XAE_CNT "xae_cnt"
#define OTX2_SSO_SINGLE_WS "single_ws"
#define OTX2_SSO_GGRP_QOS "qos"
#define OTX2_SSO_XAE_CNT "xae_cnt"
#define OTX2_SSO_SINGLE_WS "single_ws"
#define OTX2_SSO_GGRP_QOS "qos"
-#define OTX2_SSO_SELFTEST "selftest"
static void
parse_queue_param(char *value, void *opaque)
static void
parse_queue_param(char *value, void *opaque)
if (kvlist == NULL)
return;
if (kvlist == NULL)
return;
- rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
- &dev->selftest);
rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
&dev->xae_cnt);
rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
&dev->xae_cnt);
rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
event_dev->data->name, dev->max_event_queues,
dev->max_event_ports);
otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
event_dev->data->name, dev->max_event_queues,
dev->max_event_ports);
- if (dev->selftest) {
- event_dev->dev->driver = &pci_sso.driver;
- event_dev->dev_ops->dev_selftest();
- }
otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
OTX2_SSO_SINGLE_WS "=1"
OTX2_SSO_GGRP_QOS "=<string>"
RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
OTX2_SSO_SINGLE_WS "=1"
OTX2_SSO_GGRP_QOS "=<string>"
OTX2_NPA_LOCK_MASK "=<1-65535>");
OTX2_NPA_LOCK_MASK "=<1-65535>");
uint64_t *timer_adptr_sz;
/* Dev args */
uint8_t dual_ws;
uint64_t *timer_adptr_sz;
/* Dev args */
uint8_t dual_ws;
uint32_t xae_cnt;
uint8_t qos_queue_cnt;
struct otx2_sso_qos *qos_parse_data;
uint32_t xae_cnt;
uint8_t qos_queue_cnt;
struct otx2_sso_qos *qos_parse_data;