dpdk.git
3 years agonet/mlx5: wrap default miss flow action per OS
Ophir Munk [Mon, 28 Dec 2020 12:32:49 +0000 (14:32 +0200)]
net/mlx5: wrap default miss flow action per OS

Wrap glue call dr_create_flow_action_default_miss() with an OS API. This
commit is a follow up on [1].

[1]
commit d4d85aa6f13a ("common/mlx5: add default miss action")
commit b293fbf9672b ("net/mlx5: add OS specific flow actions operations")

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: wrap adjust flow priority per OS
Ophir Munk [Mon, 28 Dec 2020 12:32:48 +0000 (14:32 +0200)]
net/mlx5: wrap adjust flow priority per OS

mlx5_flow_adjust_priority() is used to adjust priorities according to
priorities levels. It is Verbs based and it is called from shared code
(mlx5_flow_dv.c). Therefore, wrap it in an OS API.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support VF PCI address on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:47 +0000 (14:32 +0200)]
net/mlx5: support VF PCI address on Windows

Support VF BDF scanning by checking both the BDF and raw BDF provided by
DevX. In Linux a PCI address is formatted as: domain, bus, device,
function (DBDF).  This is right for both a PF and a VF. In Windows a PF
also has a DBDF format, but the domain is always 0, while a VF has a
special "domain" called "Virtual PCI Bus, Serial" (for example: "Virtual
PCI Bus Slot 2 Serial 2") or segment.  The full VF format under Windows
is called raw DBF.  Windows special domain must be considered and DevX
must be called to support it.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: spawn ethdev ports on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:46 +0000 (14:32 +0200)]
net/mlx5: spawn ethdev ports on Windows

This commit implements mlx5_dev_spawn() API which allocates an eth
device (struct rte_eth_dev) for each PCI device. When working with
representors virtual functions (as in Linux), one PCI device may spawn
several eth devices: the master device for the main physical function
(PF) and several representors for the virtual functions (VFs).  However,
currently Windows does not work in switch dev mode, therefore, no VFs
are created and no representors are spawned. In this case one eth device
is created per one PCI main port.  In addition to device creation - the
device configuration must be correctly set. The device arguments
(devargs - set by the user) are parsed but they may be overridden by
Windows limitations or hardware configurations. Some associated network
parameters are stored in eth device (e.g. ifindex, MAC address, MTU) and
some callback (e.g. burst functions) are set.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: probe on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:45 +0000 (14:32 +0200)]
net/mlx5: probe on Windows

This commit implements mlx5_os_pci_probe API under Windows. It does all
required initializations then it gets the PCI device list using glue API
get_device_list().  Next, all non MLX5 matched devices are filtered out.
The supported NIC types are: CONNECTX4VF, CONNECTX4LXVF, CONNECTX5VF,
CONNECTX5EXVF, CONNECTX5BFVF, CONNECTX6VF, MELLANOX_CONNECTX6DXVF.  Each
device in the list is assigned with default configuration parameters,
most of them are 0. The default dv_flow_en parameter value is 1 (which
means Windows match and action flows are based on DV code). Next for
each PCI device call mlx5_dev_spawn() to create an eth device (struct
rte_ethdev). The implementation of device spawn is in the follow up
commit.  Finally, the device list is free.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: open device on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:44 +0000 (14:32 +0200)]
net/mlx5: open device on Windows

This commit implements mlx5_os_open_device() API. It calls glue API
open_device() then glue API query_device() to fill in 'struct
mlx5_context' with data for later usage.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support getting PDN on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:43 +0000 (14:32 +0200)]
net/mlx5: support getting PDN on Windows

Implement OS function call to get pdn.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: add VLAN stubs on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:42 +0000 (14:32 +0200)]
net/mlx5: add VLAN stubs on Windows

This commit adds stubs to VLAN VM operations.  It is the Windows
equivalent implementation of [1].  The Linux implementation was based on
Netlink APIs which are not supported in Windows.

[1]
commit 7af10d29a4a0 ("net/mlx5/linux: refactor VLAN")

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support device removed query on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:41 +0000 (14:32 +0200)]
net/mlx5: support device removed query on Windows

This commit implements mlx5_is_removed() API. A new glue call
'init_shutdown_event' is added to support the new API.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support getting interface name on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:40 +0000 (14:32 +0200)]
net/mlx5: support getting interface name on Windows

This commit copies the interface name as saved in the device context
since its creation.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support getting MTU on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:39 +0000 (14:32 +0200)]
net/mlx5: support getting MTU on Windows

This commit implements API mlx5_get_mtu(). It returns the MTU size as
saved in the device context since its creation.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support clock read on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:38 +0000 (14:32 +0200)]
net/mlx5: support clock read on Windows

This commit adds a new glue function query_rt_values to support the new
API mlx5_read_clock().

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support link update on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:37 +0000 (14:32 +0200)]
net/mlx5: support link update on Windows

Add support for mlx5_link_update() to get link speed and link state.
Other parameters are currently hard-coded.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: add stubs on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:36 +0000 (14:32 +0200)]
net/mlx5: add stubs on Windows

This commits adds ethdev stubs. These APIs are called from shared code
that must compile under Linux and Windows. The following stubs are added:
mlx5_set_mtu
mlx5_os_read_dev_counters
mlx5_intr_callback_unregister
mlx5_os_get_stats_n
mlx5_os_stats_init
mlx5_set_link_down
mlx5_set_link_up
mlx5_dev_get_flow_ctrl
mlx5_dev_set_flow_ctrl
mlx5_get_module_info
mlx5_get_module_eeprom

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support getting MAC on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:35 +0000 (14:32 +0200)]
net/mlx5: support getting MAC on Windows

This commits implements API mlx5_get_mac().  It returns the MAC address
saved in the device context since its creation.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: add stubs for MP requests on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:34 +0000 (14:32 +0200)]
net/mlx5: add stubs for MP requests on Windows

Windows supports the primary process with no secondary process control.
This commit adds stubs for requests to start/stop the data-path to the
secondary process and for requests to start/stop a queue of the primary
process.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: add memory region callbacks on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:33 +0000 (14:32 +0200)]
net/mlx5: add memory region callbacks on Windows

This commit is the Windows part implementation of
commit d5ed8aa9449d ("net/mlx5: add memory region callbacks in per-device cache")

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: wrap event channel functions on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:32 +0000 (14:32 +0200)]
common/mlx5: wrap event channel functions on Windows

This commit is the Windows equivalent of the Linux implementation.
Windows returns an error ENOTSUP for the APIs to create/destroy event
channel or to subscribe an event.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add DevX UAR getters on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:31 +0000 (14:32 +0200)]
common/mlx5: add DevX UAR getters on Windows

The following getters are added: mlx5_os_get_devx_uar_mmap_offset,
mlx5_os_get_devx_uar_base_addr, mlx5_os_get_devx_uar_reg_addr,
mlx5_os_get_devx_uar_page_id.  This commit is the Windows equivalent of
the Linux implementation in [1].

[1]
commit 1f66ac5bbe89 ("net/mlx5: remove more Direct Verbs dependencies")

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: include compatibility header file
Ophir Munk [Mon, 28 Dec 2020 12:32:30 +0000 (14:32 +0200)]
common/mlx5: include compatibility header file

Add #include <rte_compat.h> to file mlx5_devx_cmds.h. It is required for
Windows to identify the  __rte_internal definition.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: add macros for file name and path
Tal Shnaiderman [Mon, 28 Dec 2020 12:32:29 +0000 (14:32 +0200)]
net/mlx5: add macros for file name and path

ibdev_name and ibdev_path sizes are defined in Windows DevX
differently from the sizes used in Linux with
IBV_SYSFS_NAME_MAX and IBV_SYSFS_PATH_MAX.

Added MLX5_FS_NAME_MAX and MLX5_FS_NAME_PATH in mlx5_os.h for both OSs.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add missing Verbs definitions on Windows
Ophir Munk [Mon, 28 Dec 2020 12:32:28 +0000 (14:32 +0200)]
common/mlx5: add missing Verbs definitions on Windows

Add missing DV and IBV definition to file mlx5_win_defs.h. The
definitions originated from rdma-core library which is not part of
Windows. They are referenced in shared files that must compile under
Windows such as mlx5_flow_dv.c and mlx5_rxtx.c.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: refactor ops for Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:36 +0000 (11:54 +0200)]
net/mlx5: refactor ops for Windows

There are two types of eth_dev_ops used under Windows: primary and
isolate mode. Their function calls initialization is added to the OS
specific file mlx5_os.c. Secondary process eth_dev_ops is nullified.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support adding MAC address on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:35 +0000 (11:54 +0200)]
net/mlx5: support adding MAC address on Windows

Get the list of MAC addresses and verify if the input mac parameter
already exists. If not - return -ENOTSUP (as Windows does not support
adding new MAC addresses). If the MAC address exists (EEXIST) return 0
(the equivalent of Linux implementation of this API).

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: add Windows stubs
Ophir Munk [Mon, 28 Dec 2020 09:54:34 +0000 (11:54 +0200)]
net/mlx5: add Windows stubs

mlx5_os_set_nonblock_channel_fd
mlx5_os_dev_shared_handler_install
mlx5_os_dev_shared_handler_uninstall
mlx5_os_read_dev_stat
mlx5_os_mac_addr_flush
mlx5_os_mac_addr_remove
mlx5_os_vf_mac_addr_modify
mlx5_os_set_promisc
mlx5_os_set_allmulti

Set struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops with NULL
pointers.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: implement device attribute getter on Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:33 +0000 (11:54 +0200)]
net/mlx5: implement device attribute getter on Windows

This commit is the Windows implementation of mlx5_os_get_dev_attr() API.
It follows the commit in [1]. A new file named mlx5_os.c is added under
windows directory as its Linux counterpart file: linux/mlx5_os.c.

[1].
commit e85f623e13ea ("net/mlx5: remove attributes dependency on Verbs")

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add reg/dereg MR on Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:32 +0000 (11:54 +0200)]
common/mlx5: add reg/dereg MR on Windows

This commits implements Windows API for MR registration and
deregistration. It is based on DevX.  Is support the relaxed ordering
flow in Windows by checking the capabilities and machine type.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: prepare MR prototypes for DevX
Ophir Munk [Mon, 28 Dec 2020 09:54:31 +0000 (11:54 +0200)]
net/mlx5: prepare MR prototypes for DevX

Currently MR operations are Verbs based. This commit updates MR
operations prototypes such that DevX MR operations callbacks can be used
as well.  Rename 'struct mlx5_verbs_ops' as 'struct mlx5_mr_ops' and
move it to shared file mlx5.h.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add UMEM reg/dereg functions on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:30 +0000 (11:54 +0200)]
common/mlx5: add UMEM reg/dereg functions on Windows

Implement Windows API mlx5_os_umem_reg() and mlx5_os_umem_dereg(). They
are equivalent to the Linux implementation.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add alloc/dealloc PD on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:29 +0000 (11:54 +0200)]
common/mlx5: add alloc/dealloc PD on Windows

Implement Windows API mlx5_os_alloc_pd() and mlx5_os_dealloc_pd().
They are equivalent to the Linux implementation in [1].

[1] ("net/mlx5: wrap glue alloc/dealloc PD with OS calls")

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add getter functions on Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:28 +0000 (11:54 +0200)]
common/mlx5: add getter functions on Windows

Add file mlx5/windows/mlx5_common_os.h the equivalent of Linux file
mlx5/linux/mlx5_common_os.h. It contains getters functions
mlx5_os_get_dev_device_name, mlx5_os_get_ctx_device_name,
mlx5_os_get_ctx_device_path, mlx5_os_get_umem_id,
mlx5_os_get_devx_channel_fd.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: adjust PRM struct size on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:27 +0000 (11:54 +0200)]
common/mlx5: adjust PRM struct size on Windows

Add reserved size to PRM 'struct mlx5_ifc_fte_match_param_bits' for non
Linux OS.  Windows drivers require this extension since their expected
size should match the actual struct size. Linux drivers do not require
this extension and already use calculations based on the shorter size.
Use a static assert to verify that the PRM fte_match_param struct size
remains correct.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: generate autoconf file on Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:26 +0000 (11:54 +0200)]
common/mlx5: generate autoconf file on Windows

File mlx5_autoconf.h is generated under Windows to maintain
compatibility with the Linux build system.  This file is included in
Linux/Windows shared source files therefore it is required. Currently
the file is created empty.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add init for external lib on Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:25 +0000 (11:54 +0200)]
common/mlx5: add init for external lib on Windows

Add function mlx5_glue_constructor() as an initialization routine for
run-time dependency on external lib.  Currently the routine has an empty
body. It is used for compatibility with Linux.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add Windows meson file
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:24 +0000 (11:54 +0200)]
common/mlx5: add Windows meson file

File drivers/common/mlx5/windows/meson.build is added to enable mlx5
source files compilation under common windows directory.
A Devx SDK tool must be installed to export two external H files:
mlx5devx.h and mlx5_ifc_devx.h. The installation is based on environment
variable DEVX_INC_PATH. In addition a DLL lib file is installed based on
environment variable DEVX_LIB_PATH. The meson file is using the
environment variables for compilation and linkage.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add glue functions on Windows
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:23 +0000 (11:54 +0200)]
common/mlx5: add glue functions on Windows

Windows glue functions are added to file mlx5/windows/mlx5_glue.c.
The following APIs are supported:
get_device_list, free_device_list, open_device, close_device,
query_device, query_hca_iseg, devx_obj_create, devx_obj_destroy,
devx_obj_query, devx_obj_modify, devx_general_cmd, devx_umem_reg,
devx_umem_dereg, devx_alloc_uar, devx_free_uar, devx_fs_rule_add,
devx_fs_rule_del, devx_query_eqn
New added files:
mlx5_win_defs.h - this file imports missing definitions from Linux
rdma-core library and Linux OS.
mlx5_win_ext.h - this file contains structs that enable a unified
Linux/Windows API. Each struct has an equivalent (but different) Linux
struct. By calling with 'void *' pointers - the Linux/Windows API is
identical.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add DevX PD allocation command
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:22 +0000 (11:54 +0200)]
common/mlx5: add DevX PD allocation command

Add a new DevX API mlx5_devx_cmd_alloc_pd() that creates a new protection
domain (PD).

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: extend DevX HCA attributes query
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:21 +0000 (11:54 +0200)]
common/mlx5: extend DevX HCA attributes query

Extend DevX API mlx5_devx_cmd_query_hca_attr() to report on max number
of available objects including: CQ, QP, PD, SRQ.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add Windows exports file
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:20 +0000 (11:54 +0200)]
common/mlx5: add Windows exports file

File drivers/common/mlx5/rte_common_mlx5_exports.def contains mlx5
Windows exported symbols under common/mlx5 directory (DLL file
name librte_common_mlx5*.dll). It is the equivalent of Linux map
file version.map but the list of symbols may be
different between the two operating systems.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: wrap event channel functions per OS
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:19 +0000 (11:54 +0200)]
common/mlx5: wrap event channel functions per OS

Wrap the API to create/destroy event channel and to subscribe an event
with OS calls. In Linux those calls are implemented by glue functions
while in Windows they are not supported.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: wrap memory allocation on Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:18 +0000 (11:54 +0200)]
common/mlx5: wrap memory allocation on Windows

This commit is the Windows equivalent of the Linux implementation.  The
APIs included in this commit: mlx5_os_malloc(), mlx5_os_free(). For
memory allocations (with or without alignment) we always call
_aligned_malloc(). Even if zero alignment was requested in the first
place - we always select a minimal alignment value. In this way when the
memory is free - it is always safe to call _aligned_free().

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: wrap memory allocation on Linux
Ophir Munk [Mon, 28 Dec 2020 09:54:17 +0000 (11:54 +0200)]
common/mlx5: wrap memory allocation on Linux

mlx5_malloc() API has an alignment parameter for system memory
allocations. malloc() is called for non-aligned allocations and
posix_memalign() is called for aligned allocations. When calling
mlx5_free() there is no distinction whether the memory was originally
allocated with or without alignment. Freeing a memory may be handled
differently by operating systems. Therefore this commit wraps these APIs
with OS specific calls: mlx5_os_malloc(), mlx5_os_free().

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/mlx5: add Verbs usage flag
Ophir Munk [Mon, 28 Dec 2020 09:54:16 +0000 (11:54 +0200)]
common/mlx5: add Verbs usage flag

Add a Verbs file presence indication. Under Linux it is required that
file infiniband/verbs.h is installed for building DPDK.  Other
operating systems (e.g. Windows) ignore Verbs completely.  This commit
adds definition HAVE_INFINIBAND_VERBS_H (file mlx5_autoconf.h) to
indicate whether DPDK compiles with Verbs or not.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: fix flow action destroy wrapper
Ophir Munk [Mon, 28 Dec 2020 09:54:15 +0000 (11:54 +0200)]
net/mlx5: fix flow action destroy wrapper

Glue function destroy_flow_action() was wrapped by OS specific operation
mlx5_flow_os_destroy_flow_action(). It was skipped in file mlx5.c.

Fixes: b293fbf9672b ("net/mlx5: add OS specific flow actions operations")
Cc: stable@dpdk.org
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: wrap glue reg/dereg UMEM per OS
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:14 +0000 (11:54 +0200)]
net/mlx5: wrap glue reg/dereg UMEM per OS

Wrap glue calls for UMEM registration and deregistration with generic OS
calls since each OS (Linux or Windows) has a different glue API
parameters.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: wrap glue alloc/dealloc PD per OS
Ophir Munk [Mon, 28 Dec 2020 09:54:13 +0000 (11:54 +0200)]
net/mlx5: wrap glue alloc/dealloc PD per OS

Wrap glue calls alloc_pd() and dealloc_pd() with generic OS calls.  In
Linux - protection domain allocations are implemented by Verbs glue API
while in Windows it is by DevX API.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: move static asserts to global scope
Ophir Munk [Mon, 28 Dec 2020 09:54:12 +0000 (11:54 +0200)]
net/mlx5: move static asserts to global scope

Some Windows compilers consider static_assert() as calls to another
function rather than a compiler directive which allows checking type
information at compile time.  This only occurs if the static_assert call
appears inside another function scope. To solve it move the
static_assert calls to global scope in the files where they are used.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: do not define static assert in Windows
Ophir Munk [Mon, 28 Dec 2020 09:54:11 +0000 (11:54 +0200)]
net/mlx5: do not define static assert in Windows

In Linux 'static_assert' is defined in file mlx5_defs.h:

 #ifndef HAVE_STATIC_ASSERT
    #define static_assert _Static_assert
 #endif

The same definition can originate from Linux file /usr/include/assert.h.

In Windows static_assert is used while _Static_assert is unknown.
Therefore update the definition condition to be:

 #if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS)
    #define static_assert _Static_assert
 #endif

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: define MPRQ functions as static inline
Ophir Munk [Mon, 28 Dec 2020 09:54:10 +0000 (11:54 +0200)]
net/mlx5: define MPRQ functions as static inline

Functions mlx5_check_mprq_support(), mlx5_rxq_mprq_enabled(),
mlx5_mprq_enabled() are moved from source file mlx5_rxq.c to header file
mlx5_rxtx.h and their type is updated to 'static __rte_always_inline'.
Previously the functions were declared as 'inline' in the source file
which was reported as 'unresolved external symbol' error by some Windows
linkers.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: replace Linux sleep
Ophir Munk [Mon, 28 Dec 2020 09:54:09 +0000 (11:54 +0200)]
net/mlx5: replace Linux sleep

Replace Linux API usleep() and nanosleep() with rte_delay_us_sleep().
The replacement occurs in shared files compiled under different
operating systems.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: fix freeing packet pacing
Ophir Munk [Mon, 28 Dec 2020 09:54:08 +0000 (11:54 +0200)]
net/mlx5: fix freeing packet pacing

Packet pacing is allocated under condition #ifdef HAVE_MLX5DV_PP_ALLOC.
In a similar way - free packet pacing index under the same condition.
This update is required to successfully compile under operating systems
which do not support packet pacing.

Fixes: aef1e20ebeb2 ("net/mlx5: allocate packet pacing context")
Cc: stable@dpdk.org
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: remove Linux files from Windows compilation
Ophir Munk [Mon, 28 Dec 2020 09:54:07 +0000 (11:54 +0200)]
net/mlx5: remove Linux files from Windows compilation

This commit removes Linux files flow_verbs.c and mlx5_rxtx_vec.c
from Windows compilation.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: extend device attributes getter
Ophir Munk [Mon, 28 Dec 2020 09:54:06 +0000 (11:54 +0200)]
net/mlx5: extend device attributes getter

This commit adds device attributes parameters to be reported by
mlx5_os_get_dev_attr(): max_cqe, max_mr, max_pd, max_srq, max_srq_wr

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: fix constant array size
Tal Shnaiderman [Mon, 28 Dec 2020 09:54:05 +0000 (11:54 +0200)]
net/mlx5: fix constant array size

Before this commit the PMD used:
   const int elt_n = 8
   const int *stack[elt_n];

In Windows clang compiler complains:
net/mlx5/mlx5_flow.c:215:19: error: variable length array folded
to constant array as an extension [-Werror,-Wgnu-folding-constant]

Fix it by using a constant macro definition instead of a variable:
   #define MLX5_RSS_EXP_ELT_N 8
   const int *stack[MLX5_RSS_EXP_ELT_N];

Fixes: c7870bfe09dc ("ethdev: move RSS expansion code to mlx5 driver")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: fix tunnel rules validation on VF representor
Gregory Etelson [Fri, 11 Dec 2020 14:46:14 +0000 (16:46 +0200)]
net/mlx5: fix tunnel rules validation on VF representor

MLX5 PMD implicitly adds vxlan_decap flow action to tunnel offload
match type rules. However, VXLAN decap action on VF representors is
not supported on MLX5 PMD hardware.

The patch rejects attempt to create tunnel offload flow rules on VF
representor.

Refer commit 9c4971e5231d ("net/mlx5: update VLAN and encap actions validation")

Fixes: 4ec6360de37d ("net/mlx5: implement tunnel offload")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/iavf: support TCP/UDP flow item without input set
Yuying Zhang [Wed, 6 Jan 2021 10:49:13 +0000 (10:49 +0000)]
net/iavf: support TCP/UDP flow item without input set

This patch adds an input set refinement function to support outer
and inner TCP/UDP patterns without input set for flow director filter.

For example:
1. flow create 0 ingress pattern eth / ipv4 / udp / end
   actions rss queues 0 1 2 3 end / end
2. flow create 0 ingress pattern eth / ipv6 / tcp / end
   actions queue index 3 / end

This patch will refine the input set when it is empty and generate
a dummy proto type as input set in L3 header which is required
by the hardware.

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agoapp/testpmd: release flows left before port stop
Gregory Etelson [Thu, 26 Nov 2020 16:43:02 +0000 (18:43 +0200)]
app/testpmd: release flows left before port stop

According to RTE flow user guide, PMD will not keep flow rules after
port stop. Application resources that refer to flow rules become
obsolete after port stop and must not be used.
Testpmd maintains linked list of active flows for each port. Entries in
that list are allocated dynamically and must be explicitly released to
prevent memory leak.
The patch releases testpmd port flow_list that holds remaining flows
before port is stopped.

Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agonet/bnxt: set correct checksum status in mbuf
Lance Richardson [Fri, 18 Dec 2020 20:28:37 +0000 (15:28 -0500)]
net/bnxt: set correct checksum status in mbuf

The setting of the mbuf ol_flags field for tunneled packets
should be different depending upon whether DEV_RX_OFFLOAD_OUTER_*
offloads are enabled. Initialize ol_flags mappings based on
the receive offload configuration when the receive ring is
initialized.

Cc: stable@dpdk.org
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agonet/bnxt: make offload flags mapping per-ring
Lance Richardson [Fri, 18 Dec 2020 20:28:36 +0000 (15:28 -0500)]
net/bnxt: make offload flags mapping per-ring

Refactor offload flags mapping table to be dynamic  and
per-ring instead of static and global.

Cc: stable@dpdk.org
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agonet/bnxt: remove support for some PCI IDs
Ajit Khaparde [Fri, 18 Dec 2020 01:10:54 +0000 (17:10 -0800)]
net/bnxt: remove support for some PCI IDs

As announced the deprecation notice during the 20.11 release,
remove support for NetXtreme devices belonging to BCM573xx and
BCM5740x families. Specifically the support for the following Broadcom
PCI device IDs: 0x16c8, 0x16c9, 0x16ca, 0x16ce, 0x16cf, 0x16df, 0x16d0,
0x16d1, 0x16d2, 0x16d4, 0x16d5, 0x16e7, 0x16e8, 0x16e9 has been removed.

Deprecation notice has been removed and release notes for 21.02 has
been updated accordingly.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
3 years agonet/bnxt: fix outer UDP checksum Rx offload capability
Lance Richardson [Thu, 17 Dec 2020 19:24:31 +0000 (14:24 -0500)]
net/bnxt: fix outer UDP checksum Rx offload capability

Rx outer UDP checksum offload has been supported for
some time, but this has not been advertised in offload
capability flags. Fix this, and allow vector mode
receive to be enabled when DEV_RX_OFFLOAD_OUTER_UDP_CKSUM
is requested.

Fixes: 04a681426d49 ("net/bnxt: fix L4 checksum error indication in Rx")
Cc: stable@dpdk.org
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agonet/bnxt: fix fallback mbuf allocation logic
Lance Richardson [Wed, 16 Dec 2020 15:06:18 +0000 (10:06 -0500)]
net/bnxt: fix fallback mbuf allocation logic

Fixes for fallback mbuf allocation logic.
   - Preserve raw (unmasked) producer index.
   - Iterate over all processed descriptors (representor and
     non-representor) when checking allocation status.
   - Invoke fallback allocation logic when an allocation
     failure has occurred for any received packet, not
     just the last.

Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
Fixes: d9dd0b29ed31 ("net/bnxt: fix Rx handling and buffer allocation logic")
Fixes: c7de4195cc4c ("net/bnxt: modify ring index logic")
Cc: stable@dpdk.org
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agonet/bnxt: fix doorbell write ordering
Lance Richardson [Mon, 14 Dec 2020 18:56:38 +0000 (13:56 -0500)]
net/bnxt: fix doorbell write ordering

Write completion queue doorbell before receive descriptor
doorbell to avoid possibility of completion queue overflow
when completion queue size is equal to receive descriptor
ring size. Remove unnecessary compiler barriers (db write
functions have the necessary barriers.)

Fixes: 637e34befd9c ("net/bnxt: optimize Rx processing")
Cc: stable@dpdk.org
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
3 years agonet/bnxt: limit Rx representor packets per poll
Lance Richardson [Mon, 14 Dec 2020 18:53:52 +0000 (13:53 -0500)]
net/bnxt: limit Rx representor packets per poll

Without some limit on the number of packets transferred from the
HW ring to the representor ring per burst receive call, an entire ring's
worth of packets can be transferred. This can break assumptions
about ring indices (index on return could be identical to the index
on entry, which is assumed to mean that no packets were processed),
and can result in representor packets being dropped unnecessarily
due to representor ring overflow.

Fix by limiting the number of representor packets transferred per
poll to requested burst size.

Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
Cc: stable@dpdk.org
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
3 years agonet/i40e: fix flex payload rule conflict
Beilei Xing [Tue, 5 Jan 2021 03:12:56 +0000 (11:12 +0800)]
net/i40e: fix flex payload rule conflict

With the following commands, the second flow can't
be created successfully.

1. flow create 0 ingress pattern eth / ipv4 / udp /
   raw relative is 1 pattern is 0102030405 / end
   actions drop / end
2. flow destroy 0 rule 0
3. flow create 0 ingress pattern eth / ipv4 / udp /
   raw relative is 1 pattern is 010203040506 / end
   actions drop / end

The root cause is that a flag for flex pit isn't reset.

Fixes: 6ced3dd72f5f ("net/i40e: support flexible payload parsing for FDIR")
Cc: stable@dpdk.org
Reported-by: Chenmin Sun <chenmin.sun@intel.com>
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>
3 years agonet/iavf: fix GTPU UL and DL support for flow director
Junfeng Guo [Thu, 31 Dec 2020 05:13:07 +0000 (13:13 +0800)]
net/iavf: fix GTPU UL and DL support for flow director

For AVF FDIR, GTPU uplink and downlink are not supported in previous
code. This patch distinguishes GTPU with IP/EH/DL/UL for AVF FDIR.

Fixes: 4c7a41ae6b23 ("net/iavf: support flow director GTPU outer IPv4/IPv6")
Cc: stable@dpdk.org
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Tested-by: Hailin Xu <hailinx.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: fix queue pairs configuration
Alvin Zhang [Wed, 23 Dec 2020 05:29:36 +0000 (13:29 +0800)]
net/iavf: fix queue pairs configuration

Check if there are enough queue pairs currently allocated, and if not,
request PF to allocate them.

Fixes: e436cd43835b ("net/iavf: negotiate large VF and request more queues")
Cc: stable@dpdk.org
Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Tested-by: Zhimin Huang <zhiminx.huang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ixgbe: clear all queues on VF reset
Simon Ellmann [Thu, 17 Dec 2020 17:14:52 +0000 (18:14 +0100)]
net/ixgbe: clear all queues on VF reset

ixgbe devices support up to 8 Rx and Tx queues per virtual function.
Currently, the registers of only seven queues are set to default when
resetting a VF.

Signed-off-by: Simon Ellmann <simon.ellmann@tum.de>
Acked-by: Haiyue Wang <haiyue.wang@intel.com>
3 years agonet/ice/base: refactor structure field
Qi Zhang [Tue, 15 Dec 2020 05:30:57 +0000 (13:30 +0800)]
net/ice/base: refactor structure field

The change is for kernel driver RDMA usage, DPDK driver does not
enable RDMA, just for code sync.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: remove unused struct member
Qi Zhang [Tue, 15 Dec 2020 05:27:45 +0000 (13:27 +0800)]
net/ice/base: remove unused struct member

The only time you can ever have a rq_last_status is if
a firmware event was somehow reporting a status on the receive
queue, which are generally firmware initiated events or
mailbox messages from a VF.  Mostly this struct member was unused.

Fix this problem by still printing the value of the field in a debug
print, but don't store the value forever in a struct, potentially
creating opportunities for callers to use the wrong struct member.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: support eCPRI over UDP type 0 flow
Qi Zhang [Tue, 15 Dec 2020 05:25:04 +0000 (13:25 +0800)]
net/ice/base: support eCPRI over UDP type 0 flow

This patch adds extracting field for flow type eCPRI over UDP message
type 0 and field PC_ID which is used for FDIR/RSS packet steering.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: support eCPRI over MAC type 0 flow
Qi Zhang [Tue, 15 Dec 2020 05:18:27 +0000 (13:18 +0800)]
net/ice/base: support eCPRI over MAC type 0 flow

This patch adds extracting field for flow type eCPRI over mac message
type 0 and field PC_ID which is used for FDIR/RSS packet steering.

This patch also removes redundant hdr bitmask ops for PPPOE hdr.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: align macro names to specification
Qi Zhang [Tue, 15 Dec 2020 05:08:20 +0000 (13:08 +0800)]
net/ice/base: align macro names to specification

For get PHY abilities AQ, the specification defines "report modes"
as "with media", "without media" and "active configuration". For
clarity, rename macros to align with the specification.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: use report default config to get PHY capa
Qi Zhang [Tue, 15 Dec 2020 04:58:27 +0000 (12:58 +0800)]
net/ice/base: use report default config to get PHY capa

In case of new link establishment flow we should use
Report Default Configuration if FW AQ API version
supports it. This patch adds check function for Report
Default Configuration support and updates ice_set_fc(),
ice_cfg_phy_fec() and ice_aq_get_phy_caps() accordingly.

Signed-off-by: Mateusz Pacuszka <mateuszx.pacuszka@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: fix null pointer dereference
Qi Zhang [Tue, 15 Dec 2020 04:42:46 +0000 (12:42 +0800)]
net/ice/base: fix null pointer dereference

Added handling of allocation fault for ice_vsi_list_map_info
Should also check dereference of NULL pointer to filters VSI list
information for FWD_TO_VSI_LISt type only, otherwise, the FWD_TO_VSI type
filters by the given VSI can't be located.

Also the point *pi should not be NULL pointer, it is a reference to raw
data field, so remove this variable, use the reference directly.

Fixes: c7dd15931183 ("net/ice/base: add virtual switch code")
Cc: stable@dpdk.org
Signed-off-by: Jacek BuĊ‚atek <jacekx.bulatek@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: modify recursive way of adding nodes
Qi Zhang [Tue, 15 Dec 2020 04:33:53 +0000 (12:33 +0800)]
net/ice/base: modify recursive way of adding nodes

Remove the recursive way of adding the nodes to the layer in order
to reduce the stack usage. Instead the algorithm is modified to use
a while loop.

The previous code was scanning recursively the nodes horizontally.
The total stack consumption will be based on number of nodes present
on that layer. In some cases it can consume more stack.

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: change get PHY capability log level
Qi Zhang [Tue, 15 Dec 2020 04:30:32 +0000 (12:30 +0800)]
net/ice/base: change get PHY capability log level

As the user may be expected to take action on this issue, change the
message to a warning so that the message is more easily accessible than
a debug. Also, add the error code to further aide in identifying the
problem.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: resend some AQ commands when EBUSY
Qi Zhang [Tue, 15 Dec 2020 04:26:12 +0000 (12:26 +0800)]
net/ice/base: resend some AQ commands when EBUSY

Retry sending some AQ commands, as result of EBUSY AQ error.
This change follows the latest guidelines from HW. It is better
to retry the same AQ command several times, as the result of
EBUSY, instead of returning error to the caller right away.

Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: support checking double VLAN mode
Qi Zhang [Tue, 15 Dec 2020 04:21:21 +0000 (12:21 +0800)]
net/ice/base: support checking double VLAN mode

If a driver wants to configure double VLAN mode (DVM) it needs to
first check if the DDP supports DVM. To do this the driver needs to read
the package metadata section via the upload section AQ (0x04C1).

If the DDP doesn't support configuring double VLAN mode (DVM), then
there is nothing to do regarding configuring the VLAN mode of the
device.

The set_svm() or set_dvm() ops should only be called if the current
configuration supports configuring the VLAN mode of the device.

Suggested-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: fix tunnel destroy
Qi Zhang [Tue, 15 Dec 2020 04:13:57 +0000 (12:13 +0800)]
net/ice/base: fix tunnel destroy

The TCAM information in AQ command buffer is not correct when destroying
the tunnel entries. The TCAM count was always ONE even multiple entries
are destroyed, and the offset of TCAM memory was also incorrect.
This patch is to fix this issue.

Fixes: 884efe3ca1f3 ("net/ice/base: add VXLAN/generic tunnel management")
Cc: stable@dpdk.org
Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: support VXLAN VNI field in flow director
Qi Zhang [Tue, 15 Dec 2020 04:10:40 +0000 (12:10 +0800)]
net/ice/base: support VXLAN VNI field in flow director

Enable VXLAN VNI field in FDIR.

Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add interface to support configuring VLAN mode
Qi Zhang [Tue, 15 Dec 2020 04:00:55 +0000 (12:00 +0800)]
net/ice/base: add interface to support configuring VLAN mode

The VLAN mode of the device has to be configured while the global
configuration lock is held while downloading the DDP, specifically after
the DDP has been downloaded. In order to support this a VLAN mode
interface was added. By default the device will stay in single VLAN
mode (SVM), which is the current implementation. However, this can be
changed by implementing the .set_dvm op.

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add condition to copy module info into memory
Qi Zhang [Tue, 15 Dec 2020 03:29:46 +0000 (11:29 +0800)]
net/ice/base: add condition to copy module info into memory

There is added condition,to copy information about used module into
memory

Signed-off-by: Szymon T Cudzilo <szymon.t.cudzilo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add function for NVM checksum verification
Qi Zhang [Tue, 15 Dec 2020 03:22:08 +0000 (11:22 +0800)]
net/ice/base: add function for NVM checksum verification

AQ 0x0706 lets user to verify and recalculate NVM checksum. The usage
depends on command flags.

Signed-off-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add definitions for FW health status codes
Qi Zhang [Tue, 15 Dec 2020 03:14:25 +0000 (11:14 +0800)]
net/ice/base: add definitions for FW health status codes

Add definitions for the various health status codes that can be reported
by firmware.

Signed-off-by: Nick Nunley <nicholas.d.nunley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: cleanup some macros
Qi Zhang [Tue, 15 Dec 2020 03:12:12 +0000 (11:12 +0800)]
net/ice/base: cleanup some macros

Replaced the netlist related macro and removed some unused macro

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add GTP filtering via advanced switch filter
Qi Zhang [Tue, 15 Dec 2020 03:05:01 +0000 (11:05 +0800)]
net/ice/base: add GTP filtering via advanced switch filter

Add support to enable GTP filtering using advanced switch filter mechanism.
Example of GTP filter criteria:
  Outer UDP + GTP (Optional) + Inner IPv4[6] + Inner TCP/UDP

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: implement inactive NVM version get
Qi Zhang [Tue, 15 Dec 2020 02:44:39 +0000 (10:44 +0800)]
net/ice/base: implement inactive NVM version get

Similar to ice_get_inactive_orom_ver, add a function to read the NVM
version data from the inactive section of flash. The primary motivation
of this function is to allow the driver to report the version of
a pending update that has not yet been activated.

To do this, refactor ice_get_nvm_ver_info to allow it to take a bank
parameter. Read from the copy of the Shadow RAM in the NVM bank, rather
than reading from the RAM copy that is loaded by the device. This
ensures we get the accurate value when reading the inactive section.

Note that the start of the Shadow RAM copy is not directly following the
CSS header, but is actually aligned to the next 64-byte boundary. The
correct word offset must be rounded up to 32-bytes.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: read option ROM combo version from CIVD
Qi Zhang [Tue, 15 Dec 2020 02:39:28 +0000 (10:39 +0800)]
net/ice/base: read option ROM combo version from CIVD

The driver currently reads the combo image version data from within the
Boot Configuration TLV block of the PFA area of the NVM. This allows
access to the active Option ROM version data, assuming that it has been
properly copied into this section.

There is no equivalent method for reading the Option ROM version data
from a pending Option ROM update, as it will not yet have been copied
into the PFA boot configuration block. Instead, replace this
implementation with one which scans for the CIVD data section of the
Option ROM image data.

This CIVD data is stored in a packed structured format within the Option
ROM. It is always aligned to a 512 byte boundary, and starts with
a special '$CIV' 4-byte signature. Data integrity is checked using
a simple modulo 256 sum of the structure bytes.

Implement a new ice_get_orom_civd_data function which allows reading
from the selected flash bank (active or inactive), and scans for valid
CIVD data. Use this instead of the boot configuration TLV in order to
report the combo version data of precisely what is in the Option ROM
data.

To allow access to reading the inactive Option ROM bank, introduce a new
ice_get_inactive_orom_ver function. Use of a new function is done in
order to avoid leaking the bank selection abstraction outside of
ice_nvm.c

With this new function, the driver can now read and display the version
of the to-be-activated Option ROM when an update has been initiated but
not yet finalized.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: allow flash read with arbitrary size
Qi Zhang [Tue, 15 Dec 2020 02:29:16 +0000 (10:29 +0800)]
net/ice/base: allow flash read with arbitrary size

Refactor ice_read_flash_module so that it takes a size and a length
value, rather than always reading in 2-byte increments. The
ice_read_nvm_module and ice_read_orom_module wrapper functions will
still read a u16 with the byte-swapping enabled.

This will be used in a future change to implement reading of the CIVD
data from the Option ROM module.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: allow reading inactive flash security revision
Qi Zhang [Tue, 15 Dec 2020 02:25:32 +0000 (10:25 +0800)]
net/ice/base: allow reading inactive flash security revision

Modify ice_get_nvm_srev and ice_get_orom_srev to take the
ice_flash_bank enumeration that specifies whether to read from the
active or the inactive flash module. Rename and refactor the
ice_read_active_nvm_module and ice_read_active_orom_module functions to
take the bank enum value as well.

With this change, ice_get_nvm_srev and ice_get_orom_srev will be usable
in a future change to implement reading the version data for a pending
flash image.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: refactor interface for flash read
Qi Zhang [Tue, 15 Dec 2020 01:45:41 +0000 (09:45 +0800)]
net/ice/base: refactor interface for flash read

The ice_read_flash_module interface for reading from the various NVM
modules was introduced.

It's purpose is two-fold. First, it enables reading data from the CSS
header, used to allow accessing the image security revisions. Second, it
allowed reading from either the 1st or the 2nd NVM bank. This interface
was necessary because the device has two copies of each module. Only one
bank is active at a time, but it could be different for each module. The
driver had to determine which bank was active and then use that to
calculate the offset into the flash to read.

Future plans include allowing access to read not just from the active
flash bank, but also the inactive bank. This will be useful for enabling
display of the version information for a pending flash update.

The current abstraction in ice_read_flash_module is to specify the exact
bank to read. This requires callers to know whether to read from the 1st
or 2nd flash bank. This is the wrong abstraction level, since in most
cases the decision point from a caller's perspective is whether to read
from the active bank or the inactive bank.

Add a new ice_bank_select enumeration, used to indicate whether a flow
wants to read from the active, or inactive flash bank. Refactor
ice_read_flash_module to take this new enumeration instead of a raw
flash bank.

Have ice_read_flash_module select which bank to read from based on the
cached data we load during NVM initialization. With this change, it will
be come easier to implement reading version data from the inactive flash
banks in a future change.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: read more security revision options
Qi Zhang [Tue, 15 Dec 2020 01:14:30 +0000 (09:14 +0800)]
net/ice/base: read more security revision options

Added read of security revision disabled and updated disabled.

Signed-off-by: Fabio Pricoco <fabio.pricoco@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: increase control queue timeout
Qi Zhang [Tue, 15 Dec 2020 01:09:01 +0000 (09:09 +0800)]
net/ice/base: increase control queue timeout

250 msec timeout is insufficient for some AQ commands. Advice from FW
team was to increase the timeout. Increased to 1 second.

Signed-off-by: Fabio Pricoco <fabio.pricoco@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: modify ptype map for UDP
Qi Zhang [Tue, 15 Dec 2020 01:04:11 +0000 (09:04 +0800)]
net/ice/base: modify ptype map for UDP

Add below ptypes into ice_ptypes_udp_il.

MAC_IPV4_GTPC_TEID
MAC_IPV6_GTPC_TEID
MAC_IPV4_GTPC
MAC_IPV6_GTPC
MAC_IPV4_GTPU
MAC_IPV6_GTPU

So outer UDP can also be selected as input set for GTPC and
GTPU non IP packet.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice: check Rx queue number on RSS init
Dapeng Yu [Wed, 23 Dec 2020 05:30:18 +0000 (13:30 +0800)]
net/ice: check Rx queue number on RSS init

When RSS is initialized, rx queues number is used as denominator to set
default value into the RSS lookup table. If it is zero, there will be
error of being divided by 0. So add value check to avoid the error.

Fixes: 50370662b727 ("net/ice: support device and queue ops")
Cc: stable@dpdk.org
Signed-off-by: Dapeng Yu <dapengx.yu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: improve default RSS
Xuan Ding [Wed, 23 Dec 2020 12:52:28 +0000 (12:52 +0000)]
net/iavf: improve default RSS

Add support to actively configure the RSS through port config.

Any kernel PF enabled default RSS will be disabled during
initialization.

Besides, default RSS will be configured based on
rte_eth_rss_conf->rss_hf.
Currently supported default rss_type: ipv4[6], ipv4[6]_udp, ipv4[6]_tcp,
ipv4[6]_sctp.

Signed-off-by: Xuan Ding <xuan.ding@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: support eCPRI message type 0 for RSS
Simei Su [Mon, 14 Dec 2020 06:49:13 +0000 (14:49 +0800)]
net/iavf: support eCPRI message type 0 for RSS

This patch enables eCPRI Message Type 0 with input set physical
channel ID in rte_flow for RSS.

Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: support eCPRI message type 0 for flow director
Junfeng Guo [Mon, 14 Dec 2020 06:49:12 +0000 (14:49 +0800)]
net/iavf: support eCPRI message type 0 for flow director

For eCPRI MSG Type 0, ecpriRtcid/ecpriPcid field within the eCPRI
header will be extracted to Field Vector for AVF FDIR.

SPEC for eCPRI:
http://www.cpri.info/downloads/eCPRI_v_2.0_2019_05_10c.pdf

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: support eCPRI flow patterns
Simei Su [Mon, 14 Dec 2020 06:49:10 +0000 (14:49 +0800)]
net/iavf: support eCPRI flow patterns

Add patterns support for eCPRI.
Added patterns are as follows:
        eth_ecpri
        eth_ipv4_ecpri

Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>